Stats: Update stats for cache timings in cycles

This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.

3 files changed, 25 insertions, 25 deletions

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
index aad21c6d0..feb13ce30 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.042001                       # Nu
 sim_ticks                                 42001440000                       # Number of ticks simulated
 final_tick                                42001440000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  75192                       # Simulator instruction rate (inst/s)
-host_op_rate                                    75192                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               34364250                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223172                       # Number of bytes of host memory used
-host_seconds                                  1222.24                       # Real time elapsed on the host
+host_inst_rate                                 134131                       # Simulator instruction rate (inst/s)
+host_op_rate                                   134131                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               61300636                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 216520                       # Number of bytes of host memory used
+host_seconds                                   685.17                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            178816                       # Number of bytes read from this memory
@@ -174,11 +174,11 @@ system.cpu.icache.demand_avg_miss_latency::total 24215.288412
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 24215.288412                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::total 24215.288412                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets        92000                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          184                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               6                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 15333.333333                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    30.666667                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1742                       # number of ReadReq MSHR hits
@@ -270,11 +270,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 54653.714005
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 54653.714005                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total 54653.714005                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets     41228500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        82457                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets             827                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 49853.083434                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    99.706167                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          107                       # number of writebacks
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 4339a22dc..c18f0c43e 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.023660                       # Nu
 sim_ticks                                 23659827000                       # Number of ticks simulated
 final_tick                                23659827000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 114539                       # Simulator instruction rate (inst/s)
-host_op_rate                                   114539                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               32192844                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224192                       # Number of bytes of host memory used
-host_seconds                                   734.94                       # Real time elapsed on the host
+host_inst_rate                                 188397                       # Simulator instruction rate (inst/s)
+host_op_rate                                   188397                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               52951506                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217548                       # Number of bytes of host memory used
+host_seconds                                   446.82                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            197632                       # Number of bytes read from this memory
@@ -481,11 +481,11 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 35694.911504
 system.cpu.dcache.demand_avg_miss_latency::total 35694.911504                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 35694.911504                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total 35694.911504                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         5500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs           11                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs         5500                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs           11                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -623,11 +623,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 36749.952390
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35341.806995                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38760.286639                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::total 36749.952390                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs         1500                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs            3                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                1                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs         1500                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs            3                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index e11bd02ec..a5a9d98b7 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.075929                       # Nu
 sim_ticks                                 75929256000                       # Number of ticks simulated
 final_tick                                75929256000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  99785                       # Simulator instruction rate (inst/s)
-host_op_rate                                   109254                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               43964821                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 238132                       # Number of bytes of host memory used
-host_seconds                                  1727.05                       # Real time elapsed on the host
+host_inst_rate                                 126863                       # Simulator instruction rate (inst/s)
+host_op_rate                                   138901                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               55895176                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231880                       # Number of bytes of host memory used
+host_seconds                                  1358.42                       # Real time elapsed on the host
 sim_insts                                   172333091                       # Number of instructions simulated
 sim_ops                                     188686573                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            132864                       # Number of bytes read from this memory
@@ -497,11 +497,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 31016.696141
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 31016.696141                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total 31016.696141                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         4500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            9                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets         4500                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets            9                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           18                       # number of writebacks