diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/long/se/70.twolf | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/long/se/70.twolf')
5 files changed, 2683 insertions, 2623 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 874972c77..f4338fb5a 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.052048 # Number of seconds simulated -sim_ticks 52048460500 # Number of ticks simulated -final_tick 52048460500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.052057 # Number of seconds simulated +sim_ticks 52057006500 # Number of ticks simulated +final_tick 52057006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 350030 # Simulator instruction rate (inst/s) -host_op_rate 350030 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 198236020 # Simulator tick rate (ticks/s) -host_mem_usage 300292 # Number of bytes of host memory used -host_seconds 262.56 # Real time elapsed on the host +host_inst_rate 338250 # Simulator instruction rate (inst/s) +host_op_rate 338250 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 191596351 # Simulator tick rate (ticks/s) +host_mem_usage 300296 # Number of bytes of host memory used +host_seconds 271.70 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 202688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory -system.physmem.bytes_read::total 340352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202688 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 340480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 202816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202816 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3169 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5318 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3894217 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2644920 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6539137 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3894217 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3894217 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3894217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2644920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6539137 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5318 # Number of read requests accepted +system.physmem.num_reads::total 5320 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3896037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2644486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6540522 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3896037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3896037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3896037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2644486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6540522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5320 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5318 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5320 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 340352 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 340480 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 340352 # Total read bytes from the system interface side +system.physmem.bytesReadSys 340480 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -49,11 +49,11 @@ system.physmem.perBankRdBursts::4 224 # Pe system.physmem.perBankRdBursts::5 238 # Per bank write bursts system.physmem.perBankRdBursts::6 222 # Per bank write bursts system.physmem.perBankRdBursts::7 289 # Per bank write bursts -system.physmem.perBankRdBursts::8 251 # Per bank write bursts +system.physmem.perBankRdBursts::8 252 # Per bank write bursts system.physmem.perBankRdBursts::9 282 # Per bank write bursts system.physmem.perBankRdBursts::10 255 # Per bank write bursts system.physmem.perBankRdBursts::11 261 # Per bank write bursts -system.physmem.perBankRdBursts::12 409 # Per bank write bursts +system.physmem.perBankRdBursts::12 410 # Per bank write bursts system.physmem.perBankRdBursts::13 344 # Per bank write bursts system.physmem.perBankRdBursts::14 500 # Per bank write bursts system.physmem.perBankRdBursts::15 448 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 52048372000 # Total gap between requests +system.physmem.totGap 52056919000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5318 # Read request sizes (log2) +system.physmem.readPktSize::6 5320 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 378 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 976 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 347.672131 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.149483 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.651264 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 303 31.05% 31.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 210 21.52% 52.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 100 10.25% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 92 9.43% 72.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 71 7.27% 79.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 39 4.00% 83.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 30 3.07% 86.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 1.95% 88.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 112 11.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 976 # Bytes accessed per row activation -system.physmem.totQLat 32254250 # Total ticks spent queuing -system.physmem.totMemAccLat 131966750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26590000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6065.11 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 973 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.809866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.712248 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.458818 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 301 30.94% 30.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 209 21.48% 52.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 98 10.07% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 92 9.46% 71.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 72 7.40% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 45 4.62% 83.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 24 2.47% 86.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 19 1.95% 88.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 113 11.61% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 973 # Bytes accessed per row activation +system.physmem.totQLat 31528250 # Total ticks spent queuing +system.physmem.totMemAccLat 131278250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26600000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5926.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24815.11 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24676.36 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.54 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.54 # Average system read bandwidth in MiByte/s @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4336 # Number of row buffer hits during reads +system.physmem.readRowHits 4340 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.53 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9787207.97 # Average gap between requests -system.physmem.pageHitRate 81.53 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3515400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1918125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19851000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 9785135.15 # Average gap between requests +system.physmem.pageHitRate 81.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3492720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1905750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19843200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3399215040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1773582930 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29670358500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34868440995 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.985765 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49355972750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1737840000 # Time in different power states +system.physmem_0.refreshEnergy 3399723600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1761174315 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29685915000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34872054585 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.954967 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49382007750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1738100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 949756000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 931384250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 3825360 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2087250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 21231600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3399215040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1774901340 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29669193750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34870438740 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.024328 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49353927250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1737840000 # Time in different power states +system.physmem_1.refreshEnergy 3399723600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1805818995 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29646744750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34879431555 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.096868 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49317281000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1738100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 951967750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 996955000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 11467285 # Number of BP lookups -system.cpu.branchPred.condPredicted 8228909 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 787075 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6498554 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5367359 # Number of BTB hits +system.cpu.branchPred.lookups 11466165 # Number of BP lookups +system.cpu.branchPred.condPredicted 8229222 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 788767 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 6698071 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5372970 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.593128 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1175694 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 80.216677 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1174312 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20428735 # DTB read hits -system.cpu.dtb.read_misses 47112 # DTB read misses +system.cpu.dtb.read_hits 20431374 # DTB read hits +system.cpu.dtb.read_misses 46957 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20475847 # DTB read accesses -system.cpu.dtb.write_hits 6580361 # DTB write hits -system.cpu.dtb.write_misses 271 # DTB write misses +system.cpu.dtb.read_accesses 20478331 # DTB read accesses +system.cpu.dtb.write_hits 6580300 # DTB write hits +system.cpu.dtb.write_misses 270 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6580632 # DTB write accesses -system.cpu.dtb.data_hits 27009096 # DTB hits -system.cpu.dtb.data_misses 47383 # DTB misses +system.cpu.dtb.write_accesses 6580570 # DTB write accesses +system.cpu.dtb.data_hits 27011674 # DTB hits +system.cpu.dtb.data_misses 47227 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 27056479 # DTB accesses -system.cpu.itb.fetch_hits 23055300 # ITB hits -system.cpu.itb.fetch_misses 88 # ITB misses +system.cpu.dtb.data_accesses 27058901 # DTB accesses +system.cpu.itb.fetch_hits 23067346 # ITB hits +system.cpu.itb.fetch_misses 89 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 23055388 # ITB accesses +system.cpu.itb.fetch_accesses 23067435 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,26 +293,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 104096921 # number of cpu cycles simulated +system.cpu.numCycles 104114013 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2232007 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2234090 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.132681 # CPI: cycles per instruction -system.cpu.ipc 0.882861 # IPC: instructions per cycle -system.cpu.tickCycles 102361178 # Number of cycles that the object actually ticked -system.cpu.idleCycles 1735743 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.132867 # CPI: cycles per instruction +system.cpu.ipc 0.882716 # IPC: instructions per cycle +system.cpu.tickCycles 102384742 # Number of cycles that the object actually ticked +system.cpu.idleCycles 1729271 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.464460 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26584631 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1448.483845 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26587292 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11921.359193 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11922.552466 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1448.464460 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353629 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353629 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1448.483845 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353634 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353634 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id @@ -320,56 +320,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53178348 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53178348 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20086436 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20086436 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6498195 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6498195 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26584631 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26584631 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26584631 # number of overall hits -system.cpu.dcache.overall_hits::total 26584631 # number of overall hits +system.cpu.dcache.tags.tag_accesses 53183674 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53183674 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20089099 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20089099 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6498193 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6498193 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26587292 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26587292 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26587292 # number of overall hits +system.cpu.dcache.overall_hits::total 26587292 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 520 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 520 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2908 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2908 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3428 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3428 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3428 # number of overall misses -system.cpu.dcache.overall_misses::total 3428 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 41644750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 41644750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 214147250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 214147250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 255792000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 255792000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 255792000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 255792000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20086956 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20086956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 2910 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2910 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3430 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3430 # number of overall misses +system.cpu.dcache.overall_misses::total 3430 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40189000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40189000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 213917000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 213917000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 254106000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 254106000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 254106000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 254106000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20089619 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20089619 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26588059 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26588059 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26588059 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26588059 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26590722 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26590722 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26590722 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26590722 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000447 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000448 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000448 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80086.057692 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 80086.057692 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73640.732462 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73640.732462 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 74618.436406 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 74618.436406 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 74618.436406 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 74618.436406 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77286.538462 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77286.538462 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73510.996564 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73510.996564 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74083.381924 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74083.381924 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74083.381924 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74083.381924 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,12 +382,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 35 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1163 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1163 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1198 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1198 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1198 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1198 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1165 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1165 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1200 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1200 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1200 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1200 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 485 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1745 # number of WriteReq MSHR misses @@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2230 system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38003250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 38003250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 129542250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 129542250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167545500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 167545500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 167545500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 167545500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36729500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36729500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 130660500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 130660500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167390000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 167390000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 167390000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 167390000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -412,69 +412,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78357.216495 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78357.216495 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74236.246418 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74236.246418 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75132.511211 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75132.511211 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75132.511211 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75132.511211 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75730.927835 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75730.927835 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74877.077364 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74877.077364 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75062.780269 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75062.780269 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75062.780269 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75062.780269 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13853 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.586076 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23039482 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15817 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1456.627806 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13848 # number of replacements +system.cpu.icache.tags.tagsinuse 1641.495432 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23051532 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15813 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1457.758300 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.586076 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801067 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801067 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1641.495432 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801511 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801511 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 669 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 148 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 948 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 46126417 # Number of tag accesses -system.cpu.icache.tags.data_accesses 46126417 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23039482 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23039482 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23039482 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23039482 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23039482 # number of overall hits -system.cpu.icache.overall_hits::total 23039482 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15818 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15818 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15818 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15818 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15818 # number of overall misses -system.cpu.icache.overall_misses::total 15818 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 408417500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 408417500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 408417500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 408417500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 408417500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 408417500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 23055300 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 23055300 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 23055300 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 23055300 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 23055300 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 23055300 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 668 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 950 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 46150505 # Number of tag accesses +system.cpu.icache.tags.data_accesses 46150505 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23051532 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23051532 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23051532 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23051532 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23051532 # number of overall hits +system.cpu.icache.overall_hits::total 23051532 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15814 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15814 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15814 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15814 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15814 # number of overall misses +system.cpu.icache.overall_misses::total 15814 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 406574500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 406574500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 406574500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 406574500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 406574500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 406574500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 23067346 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 23067346 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 23067346 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 23067346 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 23067346 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 23067346 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000686 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000686 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000686 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000686 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000686 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000686 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25819.793906 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25819.793906 # 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number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -483,123 +483,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15818 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15818 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15818 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15818 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15818 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15818 # 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number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5318 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3167 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5320 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5318 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195052500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 31544750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 226597250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 106089750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 106089750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195052500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137634500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 332687000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195052500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137634500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 332687000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200228 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.220770 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 5320 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 110580000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 110580000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 202589500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 202589500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31119500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31119500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 202589500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 141699500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 344289000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202589500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 141699500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 344289000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200228 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200405 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200405 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.890722 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200405 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.294675 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200228 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.294851 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200405 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.294675 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61589.043259 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73020.254630 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62961.169769 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61715.968586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61715.968586 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61589.043259 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63986.285449 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62558.668672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61589.043259 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63986.285449 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62558.668672 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.294851 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64328.097731 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64328.097731 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63928.526349 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63928.526349 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72035.879630 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72035.879630 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63928.526349 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65876.104138 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64715.977444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63928.526349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65876.104138 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64715.977444 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 16302 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 16302 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 16298 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 13898 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31634 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4567 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 36201 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15813 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 485 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45474 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4617 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 50091 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012032 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1161856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1161600 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 18154 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 32048 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18154 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 32048 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 18154 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 9184000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 32048 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 16131000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24412500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 23719500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3745500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3599 # Transaction distribution -system.membus.trans_dist::ReadResp 3599 # Transaction distribution +system.membus.trans_dist::ReadResp 3601 # Transaction distribution system.membus.trans_dist::ReadExReq 1719 # Transaction distribution system.membus.trans_dist::ReadExResp 1719 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10636 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10636 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340352 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 340352 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3601 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10640 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10640 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 340480 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5318 # Request fanout histogram +system.membus.snoop_fanout::samples 5320 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5318 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5320 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5318 # Request fanout histogram -system.membus.reqLayer0.occupancy 6399500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5320 # Request fanout histogram +system.membus.reqLayer0.occupancy 6410500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28155000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28166750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index f5ac38df0..2afb0af07 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022229 # Number of seconds simulated -sim_ticks 22228749500 # Number of ticks simulated -final_tick 22228749500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022173 # Number of seconds simulated +sim_ticks 22172615500 # Number of ticks simulated +final_tick 22172615500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 192800 # Simulator instruction rate (inst/s) -host_op_rate 192800 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50911418 # Simulator tick rate (ticks/s) -host_mem_usage 230228 # Number of bytes of host memory used -host_seconds 436.62 # Real time elapsed on the host +host_inst_rate 207826 # Simulator instruction rate (inst/s) +host_op_rate 207826 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54740698 # Simulator tick rate (ticks/s) +host_mem_usage 301824 # Number of bytes of host memory used +host_seconds 405.05 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 196032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory -system.physmem.bytes_read::total 334592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 196032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 196032 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3063 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8818850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6233369 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15052219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8818850 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8818850 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8818850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6233369 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15052219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5228 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 196224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory +system.physmem.bytes_read::total 334656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 196224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 196224 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3066 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5229 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8849836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6243377 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15093213 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8849836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8849836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8849836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6243377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15093213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5229 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5228 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5229 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334592 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334656 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334592 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334656 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -44,18 +44,18 @@ system.physmem.neitherReadNorWriteReqs 0 # Nu system.physmem.perBankRdBursts::0 472 # Per bank write bursts system.physmem.perBankRdBursts::1 290 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts -system.physmem.perBankRdBursts::3 525 # Per bank write bursts -system.physmem.perBankRdBursts::4 219 # Per bank write bursts +system.physmem.perBankRdBursts::3 526 # Per bank write bursts +system.physmem.perBankRdBursts::4 217 # Per bank write bursts system.physmem.perBankRdBursts::5 224 # Per bank write bursts -system.physmem.perBankRdBursts::6 218 # Per bank write bursts +system.physmem.perBankRdBursts::6 217 # Per bank write bursts system.physmem.perBankRdBursts::7 285 # Per bank write bursts -system.physmem.perBankRdBursts::8 238 # Per bank write bursts -system.physmem.perBankRdBursts::9 279 # Per bank write bursts +system.physmem.perBankRdBursts::8 239 # Per bank write bursts +system.physmem.perBankRdBursts::9 278 # Per bank write bursts system.physmem.perBankRdBursts::10 248 # Per bank write bursts -system.physmem.perBankRdBursts::11 252 # Per bank write bursts +system.physmem.perBankRdBursts::11 253 # Per bank write bursts system.physmem.perBankRdBursts::12 398 # Per bank write bursts system.physmem.perBankRdBursts::13 338 # Per bank write bursts -system.physmem.perBankRdBursts::14 491 # Per bank write bursts +system.physmem.perBankRdBursts::14 493 # Per bank write bursts system.physmem.perBankRdBursts::15 449 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22228653000 # Total gap between requests +system.physmem.totGap 22172520500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5228 # Read request sizes (log2) +system.physmem.readPktSize::6 5229 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 383.630485 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 225.895164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 361.482180 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 274 31.64% 31.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 174 20.09% 51.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 79 9.12% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 66 7.62% 68.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 29 3.35% 71.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 37 4.27% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 36 4.16% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 45 5.20% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 126 14.55% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 866 # Bytes accessed per row activation -system.physmem.totQLat 39875750 # Total ticks spent queuing -system.physmem.totMemAccLat 137900750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7627.34 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 385.112399 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 228.773233 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 362.004147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 257 29.78% 29.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 196 22.71% 52.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 76 8.81% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 6.60% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 37 4.29% 72.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 34 3.94% 76.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 29 3.36% 79.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 50 5.79% 85.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 127 14.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 863 # Bytes accessed per row activation +system.physmem.totQLat 43111750 # Total ticks spent queuing +system.physmem.totMemAccLat 141155500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26145000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8244.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26377.34 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.05 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26994.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.09 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.05 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.09 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4353 # Number of row buffer hits during reads +system.physmem.readRowHits 4356 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.26 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4251846.40 # Average gap between requests -system.physmem.pageHitRate 83.26 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3137400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1711875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19476600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 4240298.43 # Average gap between requests +system.physmem.pageHitRate 83.30 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3160080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1724250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19492200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1451430240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 894518100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 12548665500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14918939715 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.352430 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 20873521000 # Time in different power states -system.physmem_0.memoryStateTime::REF 742040000 # Time in different power states +system.physmem_0.refreshEnergy 1447870320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 926205255 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12488167500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14886619605 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.545103 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20772765250 # Time in different power states +system.physmem_0.memoryStateTime::REF 740220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 606815000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 654868750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3349080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1827375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20794800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3311280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1806750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20810400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1451430240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 919030095 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12527163750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14923595340 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.561933 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 20841181500 # Time in different power states -system.physmem_1.memoryStateTime::REF 742040000 # Time in different power states +system.physmem_1.refreshEnergy 1447870320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 909735390 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12502614750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14886148890 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.523868 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20796420250 # Time in different power states +system.physmem_1.memoryStateTime::REF 740220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 642887000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 631087250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16323961 # Number of BP lookups -system.cpu.branchPred.condPredicted 11865379 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 978310 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9045215 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7641567 # Number of BTB hits +system.cpu.branchPred.lookups 16296711 # Number of BP lookups +system.cpu.branchPred.condPredicted 11841199 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 977322 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9230824 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7630427 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 84.481872 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1608650 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 453 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.662469 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1605836 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 456 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24152698 # DTB read hits -system.cpu.dtb.read_misses 236585 # DTB read misses +system.cpu.dtb.read_hits 24148862 # DTB read hits +system.cpu.dtb.read_misses 238971 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 24389283 # DTB read accesses -system.cpu.dtb.write_hits 7160578 # DTB write hits -system.cpu.dtb.write_misses 1214 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7161792 # DTB write accesses -system.cpu.dtb.data_hits 31313276 # DTB hits -system.cpu.dtb.data_misses 237799 # DTB misses -system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 31551075 # DTB accesses -system.cpu.itb.fetch_hits 16159751 # ITB hits -system.cpu.itb.fetch_misses 85 # ITB misses +system.cpu.dtb.read_accesses 24387833 # DTB read accesses +system.cpu.dtb.write_hits 7164238 # DTB write hits +system.cpu.dtb.write_misses 1251 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 7165489 # DTB write accesses +system.cpu.dtb.data_hits 31313100 # DTB hits +system.cpu.dtb.data_misses 240222 # DTB misses +system.cpu.dtb.data_acv 3 # DTB access violations +system.cpu.dtb.data_accesses 31553322 # DTB accesses +system.cpu.itb.fetch_hits 16134293 # ITB hits +system.cpu.itb.fetch_misses 87 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 16159836 # ITB accesses +system.cpu.itb.fetch_accesses 16134380 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,239 +293,239 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 44457500 # number of cpu cycles simulated +system.cpu.numCycles 44345232 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16896881 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 139613933 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16323961 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9250217 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 26293708 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2036816 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 16871286 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 139358892 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16296711 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9236263 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 26208155 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2034698 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 2 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 203 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2338 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 16159751 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 382144 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44211553 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.157861 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.431266 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 152 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2379 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 16134293 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 382507 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44099332 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.160113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.432013 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19722112 44.61% 44.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2663068 6.02% 50.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1345508 3.04% 53.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1957580 4.43% 58.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3052640 6.90% 65.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1306785 2.96% 67.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1385791 3.13% 71.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 896674 2.03% 73.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11881395 26.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19660436 44.58% 44.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2660444 6.03% 50.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1334517 3.03% 53.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1958294 4.44% 58.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3041312 6.90% 64.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1304304 2.96% 67.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1378179 3.13% 71.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 896078 2.03% 73.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11865768 26.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44211553 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367181 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.140391 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13076592 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8324763 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19681975 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2121490 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1006733 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2681054 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12065 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 133596496 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 48387 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1006733 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 14226924 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4752424 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9184 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20532599 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3683689 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 130038627 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 69797 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2001155 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1372929 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 55394 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 95511389 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 168978901 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 161414982 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7563918 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44099332 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367496 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.142590 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13096074 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8205573 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19698619 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2093424 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1005642 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2679978 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12191 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 133453867 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 48806 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1005642 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 14231650 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4726220 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9532 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20537255 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3589033 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 129931841 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 72505 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1962504 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1321371 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 55153 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 95440121 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 168856219 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 161261081 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7595137 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27084028 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 772 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 782 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8280120 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 27136625 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8757663 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3565364 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1670156 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 112744524 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2237 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 100145020 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 122649 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 28567051 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21979359 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1848 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44211553 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.265132 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.094303 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27012760 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 775 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 786 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8114171 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 27101259 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8744711 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3477099 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1649521 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 112647261 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1499 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 100144647 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 120164 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 28469050 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21866284 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1110 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44099332 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.270888 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.097444 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11585483 26.20% 26.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7800031 17.64% 43.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7580714 17.15% 60.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5746471 13.00% 73.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4482670 10.14% 84.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2978699 6.74% 90.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2013201 4.55% 95.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1153505 2.61% 98.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 870779 1.97% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11543505 26.18% 26.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7764590 17.61% 43.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7534716 17.09% 60.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5714671 12.96% 73.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4493321 10.19% 84.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2994712 6.79% 90.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2021459 4.58% 95.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1167850 2.65% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 864508 1.96% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44211553 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44099332 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 481856 20.25% 20.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 20.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 20.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 350 0.01% 20.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 34531 1.45% 21.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 11644 0.49% 22.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1006485 42.29% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 687304 28.88% 93.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 157568 6.62% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 476525 19.98% 19.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 437 0.02% 20.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34852 1.46% 21.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 11487 0.48% 21.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1008602 42.30% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 692685 29.05% 93.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 159938 6.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60921013 60.83% 60.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 491088 0.49% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2841000 2.84% 64.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115643 0.12% 64.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2440640 2.44% 66.71% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 314095 0.31% 67.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 766051 0.76% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24991126 24.95% 92.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7264038 7.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60907964 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 491070 0.49% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2843610 2.84% 64.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115460 0.12% 64.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2441189 2.44% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 314170 0.31% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 765827 0.76% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24997693 24.96% 92.74% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7267338 7.26% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 100145020 # Type of FU issued -system.cpu.iq.rate 2.252601 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2379738 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023763 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 231363005 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 131706335 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 90039702 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15640975 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9649243 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7175345 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 94170320 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8354431 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1902679 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 100144647 # Type of FU issued +system.cpu.iq.rate 2.258296 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2384526 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023811 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 231229628 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 131456710 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 90023404 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15663688 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9702849 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7180664 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 94162135 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8367031 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1912696 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7140427 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11100 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 42139 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2256560 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7105061 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11423 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 42083 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2243608 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42760 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1687 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42789 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1006733 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3731793 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 447885 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 123749930 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 277756 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 27136625 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8757663 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2237 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 43684 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 396903 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 42139 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 560048 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 524506 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1084554 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98770041 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24389817 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1374979 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1005642 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3713444 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 450339 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 123646937 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 273080 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 27101259 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8744711 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1499 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 41770 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 401874 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 42083 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 559712 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 524057 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1083769 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98766968 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24388350 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1377679 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 11003169 # number of nop insts executed -system.cpu.iew.exec_refs 31551638 # number of memory reference insts executed -system.cpu.iew.exec_branches 12536484 # Number of branches executed -system.cpu.iew.exec_stores 7161821 # Number of stores executed -system.cpu.iew.exec_rate 2.221673 # Inst execution rate -system.cpu.iew.wb_sent 97959187 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 97215047 # cumulative count of insts written-back -system.cpu.iew.wb_producers 67118954 # num instructions producing a value -system.cpu.iew.wb_consumers 95176065 # num instructions consuming a value +system.cpu.iew.exec_nop 10998177 # number of nop insts executed +system.cpu.iew.exec_refs 31553871 # number of memory reference insts executed +system.cpu.iew.exec_branches 12528994 # Number of branches executed +system.cpu.iew.exec_stores 7165521 # Number of stores executed +system.cpu.iew.exec_rate 2.227229 # Inst execution rate +system.cpu.iew.wb_sent 97952857 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 97204068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 67107593 # num instructions producing a value +system.cpu.iew.wb_consumers 95129025 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.186696 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705208 # average fanout of values written-back +system.cpu.iew.wb_rate 2.191985 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705438 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 31848480 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 31745312 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 966635 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39567002 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.322720 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.905630 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 965615 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39467684 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.328565 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.908680 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15032687 37.99% 37.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8622118 21.79% 59.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3917590 9.90% 69.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1951695 4.93% 74.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1384336 3.50% 78.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1033619 2.61% 80.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 694183 1.75% 82.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 726057 1.84% 84.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6204717 15.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14970260 37.93% 37.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8589907 21.76% 59.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3909988 9.91% 69.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1952996 4.95% 74.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1374473 3.48% 78.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1034336 2.62% 80.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 694993 1.76% 82.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 731194 1.85% 84.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6209537 15.73% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39567002 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39467684 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -571,344 +571,350 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6204717 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 157112780 # The number of ROB reads -system.cpu.rob.rob_writes 252206838 # The number of ROB writes -system.cpu.timesIdled 4633 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 245947 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6209537 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 156905474 # The number of ROB reads +system.cpu.rob.rob_writes 251988235 # The number of ROB writes +system.cpu.timesIdled 4640 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 245900 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.528126 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.528126 # CPI: Total CPI of All Threads -system.cpu.ipc 1.893487 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.893487 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 133407543 # number of integer regfile reads -system.cpu.int_regfile_writes 73150911 # number of integer regfile writes -system.cpu.fp_regfile_reads 6256040 # number of floating regfile reads -system.cpu.fp_regfile_writes 6161921 # number of floating regfile writes -system.cpu.misc_regfile_reads 718993 # number of misc regfile reads +system.cpu.cpi 0.526792 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.526792 # CPI: Total CPI of All Threads +system.cpu.ipc 1.898281 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.898281 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 133413106 # number of integer regfile reads +system.cpu.int_regfile_writes 73139309 # number of integer regfile writes +system.cpu.fp_regfile_reads 6258544 # number of floating regfile reads +system.cpu.fp_regfile_writes 6168597 # number of floating regfile writes +system.cpu.misc_regfile_reads 718994 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 159 # number of replacements -system.cpu.dcache.tags.tagsinuse 1458.668074 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28697534 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2246 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12777.174533 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1454.905467 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28683797 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2244 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12782.440731 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1458.668074 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.356120 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.356120 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2087 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1454.905467 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355202 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355202 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2085 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57416312 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57416312 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22204643 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22204643 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492628 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492628 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 263 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 263 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28697271 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28697271 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28697271 # number of overall hits -system.cpu.dcache.overall_hits::total 28697271 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1023 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1023 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8475 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8475 # number of WriteReq misses +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1386 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509033 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 57388820 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57388820 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22190893 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22190893 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492625 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492625 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 279 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 279 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28683518 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28683518 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28683518 # number of overall hits +system.cpu.dcache.overall_hits::total 28683518 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1012 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1012 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8478 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8478 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9498 # number of overall misses -system.cpu.dcache.overall_misses::total 9498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 69711000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 69711000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 550954965 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 550954965 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9490 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9490 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9490 # number of overall misses +system.cpu.dcache.overall_misses::total 9490 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 67994000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 67994000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 547632747 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 547632747 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 85000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 620665965 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 620665965 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 620665965 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 620665965 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22205666 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22205666 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 615626747 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 615626747 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 615626747 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 615626747 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22191905 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22191905 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 264 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 264 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28706769 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28706769 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28706769 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28706769 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 280 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 280 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28693008 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28693008 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28693008 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28693008 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001304 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001304 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003788 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003788 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003571 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003571 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000331 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000331 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000331 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000331 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68143.695015 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68143.695015 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65009.435398 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65009.435398 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67187.747036 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67187.747036 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64594.567941 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64594.567941 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65347.016740 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65347.016740 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65347.016740 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65347.016740 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33287 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64871.100843 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64871.100843 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64871.100843 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64871.100843 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33428 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 426 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 398 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.138498 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.989950 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 109 # number of writebacks system.cpu.dcache.writebacks::total 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 512 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 512 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6741 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6741 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7253 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7253 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7253 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7253 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 511 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 511 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 503 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 503 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6744 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6744 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7247 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7247 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7247 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7247 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 509 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 509 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2245 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2245 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2245 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2245 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38736500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 38736500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 136484495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 136484495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 83500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 83500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 175220995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 175220995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 175220995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 175220995 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2243 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2243 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2243 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2243 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39245500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 39245500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 137397495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 137397495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 84000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 84000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 176642995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 176642995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 176642995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 176642995 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # 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average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78710.781430 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78710.781430 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 83500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 83500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78049.440980 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78049.440980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78049.440980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78049.440980 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77103.143418 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77103.143418 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79237.309689 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79237.309689 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 84000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 84000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78753.007133 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78753.007133 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78753.007133 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78753.007133 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 9845 # 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Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.781499 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1599.606485 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 760 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 936 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 32331281 # Number of tag accesses -system.cpu.icache.tags.data_accesses 32331281 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 16144798 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 16144798 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 16144798 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 16144798 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 16144798 # number of overall hits -system.cpu.icache.overall_hits::total 16144798 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14951 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14951 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14951 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14951 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14951 # number of overall misses -system.cpu.icache.overall_misses::total 14951 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 446766000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 446766000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 446766000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 446766000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 446766000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 446766000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 16159749 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 16159749 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 16159749 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 16159749 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29882.014581 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29882.014581 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29882.014581 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 770 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 934 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 32280293 # Number of tag accesses +system.cpu.icache.tags.data_accesses 32280293 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 16119452 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 16119452 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 16119452 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 16119452 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 16119452 # number of overall hits +system.cpu.icache.overall_hits::total 16119452 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14840 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14840 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14840 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14840 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14840 # number of overall misses +system.cpu.icache.overall_misses::total 14840 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 447595000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 447595000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 447595000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 447595000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 447595000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 447595000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 16134292 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 16134292 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 16134292 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 16134292 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 16134292 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 16134292 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000920 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000920 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000920 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000920 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000920 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000920 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30161.388140 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30161.388140 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30161.388140 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30161.388140 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30161.388140 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30161.388140 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 223 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 55.777778 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55.750000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3168 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3168 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3168 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3168 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3168 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3168 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11783 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11783 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11783 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11783 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11783 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11783 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 332403750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 332403750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 332403750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 332403750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 332403750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 332403750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000729 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000729 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000729 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000729 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000729 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000729 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28210.451498 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28210.451498 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28210.451498 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 28210.451498 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28210.451498 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 28210.451498 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3131 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3131 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3131 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3131 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3131 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3131 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11709 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11709 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11709 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11709 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11709 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11709 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 339198000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 339198000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 339198000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 339198000 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28968.998207 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28968.998207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28968.998207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28968.998207 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2407.331968 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8790 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3587 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.450516 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2400.828541 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 18535 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 914 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2430 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109467 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 118425 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 118425 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 8720 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 8775 # number of ReadReq hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2424 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109497 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 196394 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 196394 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200218000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 150720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 350938000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985006 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985006 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.259951 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.372657 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.259951 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.372657 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62309.582109 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70016.411379 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63310.156250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66318.354801 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66318.354801 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62309.582109 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67098.960739 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64292.941852 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62309.582109 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67098.960739 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64292.941852 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.261850 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.261850 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.892157 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.892157 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.261850 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963904 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.374758 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.261850 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963904 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.374758 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68677.400468 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68677.400468 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65302.674494 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65302.674494 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73448.351648 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73448.351648 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65302.674494 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69680.998613 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67113.788487 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65302.674494 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69680.998613 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67113.788487 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 12295 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 12295 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12219 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 9822 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1734 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1734 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23566 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4601 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 28167 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 754112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 904832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 11709 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 510 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33190 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4647 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 37837 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 749376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 899968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 14138 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 23884 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 14138 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 23884 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 14138 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7178000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18279750 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 23884 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12051000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 17563500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3635750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3366000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3520 # Transaction distribution -system.membus.trans_dist::ReadResp 3520 # Transaction distribution +system.membus.trans_dist::ReadResp 3521 # Transaction distribution system.membus.trans_dist::ReadExReq 1708 # Transaction distribution system.membus.trans_dist::ReadExResp 1708 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10456 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10456 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3521 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10458 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10458 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334656 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5228 # Request fanout histogram +system.membus.snoop_fanout::samples 5229 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5228 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5229 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5228 # Request fanout histogram -system.membus.reqLayer0.occupancy 6467500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5229 # Request fanout histogram +system.membus.reqLayer0.occupancy 6267000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 27502000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 27480000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index d21841628..f9aa76ee3 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.131586 # Number of seconds simulated -sim_ticks 131586268500 # Number of ticks simulated -final_tick 131586268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.131585 # Number of seconds simulated +sim_ticks 131584694500 # Number of ticks simulated +final_tick 131584694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 246297 # Simulator instruction rate (inst/s) -host_op_rate 259636 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 188078312 # Simulator tick rate (ticks/s) -host_mem_usage 317920 # Number of bytes of host memory used -host_seconds 699.64 # Real time elapsed on the host +host_inst_rate 242795 # Simulator instruction rate (inst/s) +host_op_rate 255945 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 185402255 # Simulator tick rate (ticks/s) +host_mem_usage 318276 # Number of bytes of host memory used +host_seconds 709.73 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 138368 # Nu system.physmem.num_reads::cpu.inst 2162 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3870 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1051538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 830725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1882263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1051538 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1051538 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1051538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 830725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1882263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1051551 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 830735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1882286 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1051551 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1051551 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1051551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 830735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1882286 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3870 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3870 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 131586174000 # Total gap between requests +system.physmem.totGap 131584601000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 901 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 272.834628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.187503 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 278.027106 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 257 28.52% 28.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 352 39.07% 67.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 83 9.21% 76.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 53 5.88% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 41 4.55% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 20 2.22% 89.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 17 1.89% 91.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 20 2.22% 93.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 58 6.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 901 # Bytes accessed per row activation -system.physmem.totQLat 26462250 # Total ticks spent queuing -system.physmem.totMemAccLat 99024750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 912 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 269.614035 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.051598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 274.679496 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 270 29.61% 29.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 347 38.05% 67.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 87 9.54% 77.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 54 5.92% 83.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 40 4.39% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 20 2.19% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 1.97% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation +system.physmem.totQLat 27229750 # Total ticks spent queuing +system.physmem.totMemAccLat 99792250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6837.79 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7036.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25587.79 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25786.11 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -216,47 +216,47 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2963 # Number of row buffer hits during reads +system.physmem.readRowHits 2952 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.56 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.28 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34001595.35 # Average gap between requests -system.physmem.pageHitRate 76.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3107160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1695375 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 34001188.89 # Average gap between requests +system.physmem.pageHitRate 76.28 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3129840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1707750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 8594155440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3588895845 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75799905000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88003936020 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.824061 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126101706500 # Time in different power states +system.physmem_0.actBackEnergy 3579629355 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75808025250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88002824835 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.815686 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126113612750 # Time in different power states system.physmem_0.memoryStateTime::REF 4393740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1088502500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1075043250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3689280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2013000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3749760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2046000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13774800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 8594155440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3567061710 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75819057750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 87999744180 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.792204 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126130418250 # Time in different power states +system.physmem_1.actBackEnergy 3571830900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75814874250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88000431150 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.797424 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126123074750 # Time in different power states system.physmem_1.memoryStateTime::REF 4393740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1056288250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1063297750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 49889699 # Number of BP lookups -system.cpu.branchPred.condPredicted 39633555 # Number of conditional branches predicted +system.cpu.branchPred.lookups 49889701 # Number of BP lookups +system.cpu.branchPred.condPredicted 39633557 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5745356 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24337780 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 24337782 # Number of BTB lookups system.cpu.branchPred.BTBHits 23279998 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.653745 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 95.653737 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1903300 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 140 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -377,26 +377,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 263172537 # number of cpu cycles simulated +system.cpu.numCycles 263169389 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11983755 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11983759 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.527251 # CPI: cycles per instruction -system.cpu.ipc 0.654771 # IPC: instructions per cycle -system.cpu.tickCycles 256740434 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6432103 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.527233 # CPI: cycles per instruction +system.cpu.ipc 0.654779 # IPC: instructions per cycle +system.cpu.tickCycles 256740818 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6428571 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.700648 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40793912 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1377.711326 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40793911 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22538.072928 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22538.072376 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.700648 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336353 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336353 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.711326 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336355 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336355 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id @@ -408,36 +408,36 @@ system.cpu.dcache.tags.tag_accesses 81594514 # Nu system.cpu.dcache.tags.data_accesses 81594514 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 28385993 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 28385993 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 464 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 464 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40748634 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40748634 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40749098 # number of overall hits -system.cpu.dcache.overall_hits::total 40749098 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 40748633 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40748633 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40749097 # number of overall hits +system.cpu.dcache.overall_hits::total 40749097 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1647 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1647 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2439 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2439 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2440 # number of overall misses -system.cpu.dcache.overall_misses::total 2440 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57815734 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57815734 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 126489000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 126489000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 184304734 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 184304734 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 184304734 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 184304734 # number of overall miss cycles +system.cpu.dcache.demand_misses::cpu.data 2440 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2440 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2441 # number of overall misses +system.cpu.dcache.overall_misses::total 2441 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57382000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57382000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126740000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126740000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184122000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184122000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184122000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184122000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 28386786 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 28386786 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) @@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72907.609079 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72907.609079 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76846.294046 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76846.294046 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75565.696597 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75565.696597 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75534.727049 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75534.727049 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72360.655738 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72360.655738 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76952.034001 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76952.034001 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75459.836066 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75459.836066 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75428.922573 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75428.922573 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks 16 # nu system.cpu.dcache.writebacks::total 16 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 549 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 549 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 631 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 631 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 631 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 631 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses @@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1809 system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51168764 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51168764 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84319000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84319000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 135487764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 135487764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 135557264 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 135557264 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51034000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51034000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85245500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85245500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136279500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 136279500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136349500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 136349500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -518,26 +518,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71967.319269 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71967.319269 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76793.260474 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76793.260474 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74896.497512 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74896.497512 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74893.516022 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74893.516022 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71777.777778 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71777.777778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77637.067395 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77637.067395 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75334.162521 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75334.162521 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75331.215470 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75331.215470 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2889 # number of replacements -system.cpu.icache.tags.tagsinuse 1425.913177 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71538503 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1425.919952 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 71538505 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4687 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15263.175379 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 15263.175805 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1425.913177 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.696247 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.696247 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1425.919952 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.696250 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.696250 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1798 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id @@ -545,44 +545,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 493 system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.877930 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 143091069 # Number of tag accesses -system.cpu.icache.tags.data_accesses 143091069 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71538503 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71538503 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71538503 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71538503 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71538503 # number of overall hits -system.cpu.icache.overall_hits::total 71538503 # number of overall hits +system.cpu.icache.tags.tag_accesses 143091073 # Number of tag accesses +system.cpu.icache.tags.data_accesses 143091073 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 71538505 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 71538505 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 71538505 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 71538505 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 71538505 # number of overall hits +system.cpu.icache.overall_hits::total 71538505 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 4688 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 4688 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 4688 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 4688 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4688 # number of overall misses system.cpu.icache.overall_misses::total 4688 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 200735747 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 200735747 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 200735747 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 200735747 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 200735747 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 200735747 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71543191 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71543191 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71543191 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71543191 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71543191 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71543191 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 199914000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 199914000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 199914000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 199914000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 199914000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 199914000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 71543193 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 71543193 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 71543193 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 71543193 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 71543193 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 71543193 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42819.058660 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42819.058660 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42819.058660 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42819.058660 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42819.058660 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42819.058660 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42643.771331 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42643.771331 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42643.771331 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42643.771331 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42643.771331 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42643.771331 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -597,117 +597,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4688 system.cpu.icache.demand_mshr_misses::total 4688 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4688 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4688 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192780753 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 192780753 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192780753 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 192780753 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192780753 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 192780753 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195227000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 195227000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195227000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 195227000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195227000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 195227000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41122.174275 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41122.174275 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41122.174275 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41122.174275 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41122.174275 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41122.174275 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41643.984642 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41643.984642 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41643.984642 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41643.984642 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41643.984642 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41643.984642 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2002.534339 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2603 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2002.545063 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5192 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2788 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.933644 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.862267 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.029198 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1508.688891 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 490.816250 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 3.029187 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1508.695895 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 490.819981 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046042 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.061112 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.061113 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 2788 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 522 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 523 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 154 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2006 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085083 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 55998 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 55998 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2522 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 80 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2602 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 76702 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 76702 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2522 # number of demand (read+write) hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2523 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2523 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 80 # 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number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 132817250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 294430000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4688 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 712 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5400 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 3887 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83513000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 83513000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161704000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 161704000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49184000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 49184000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 161704000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 132697000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 294401000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 161704000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 132697000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 294401000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4688 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 4688 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 4688 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1810 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 6498 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 4688 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1810 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 6498 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.462031 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887640 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.518148 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992714 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462031 # miss rate for demand accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.461817 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.461817 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461817 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.598338 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462031 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.598184 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461817 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.598338 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74613.457987 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78610.363924 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75516.261615 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76271.100917 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76271.100917 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74613.457987 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77129.645761 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75727.880658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74613.457987 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77129.645761 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75727.880658 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.598184 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76617.431193 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76617.431193 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74690.069284 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74690.069284 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77822.784810 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77822.784810 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74690.069284 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77059.814170 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75739.902238 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74690.069284 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77059.814170 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75739.902238 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -716,93 +722,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 14 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2163 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 618 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2781 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2163 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2163 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 618 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 618 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2163 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 3871 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3871 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134379750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40985000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 175364750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69507000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69507000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134379750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 110492000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 244871750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134379750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 110492000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 244871750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.515000 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72613000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72613000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139936000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139936000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42042000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42042000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139936000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 114655000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 254591000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139936000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 114655000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 254591000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.461391 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.867978 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.595722 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.595722 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62126.560333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66318.770227 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63058.162531 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63767.889908 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63767.889908 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62126.560333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64690.866511 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63258.008267 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62126.560333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64690.866511 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63258.008267 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66617.431193 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66617.431193 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64695.330559 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64695.330559 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68029.126214 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68029.126214 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64695.330559 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67128.220141 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65768.793593 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64695.330559 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67128.220141 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65768.793593 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5400 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5399 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2588 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9375 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 13011 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11943 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3656 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 15599 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 416832 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6514 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 9429 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 6514 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 9429 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6514 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3273000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9429 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4730500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7492747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7031498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3019736 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2721986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 2780 # Transaction distribution system.membus.trans_dist::ReadResp 2780 # Transaction distribution system.membus.trans_dist::ReadExReq 1090 # Transaction distribution system.membus.trans_dist::ReadExResp 1090 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2780 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7740 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 7740 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247680 # Cumulative packet size per connected master and slave (bytes) @@ -818,9 +831,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3870 # Request fanout histogram -system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4532500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20561750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20566750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index a8c1caea2..b441da851 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085032 # Number of seconds simulated -sim_ticks 85032044000 # Number of ticks simulated -final_tick 85032044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085019 # Number of seconds simulated +sim_ticks 85018904000 # Number of ticks simulated +final_tick 85018904000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135904 # Simulator instruction rate (inst/s) -host_op_rate 143266 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67069129 # Simulator tick rate (ticks/s) -host_mem_usage 314096 # Number of bytes of host memory used -host_seconds 1267.83 # Real time elapsed on the host +host_inst_rate 135768 # Simulator instruction rate (inst/s) +host_op_rate 143122 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66991355 # Simulator tick rate (ticks/s) +host_mem_usage 315704 # Number of bytes of host memory used +host_seconds 1269.10 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 127040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 47488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71360 # Number of bytes read from this memory -system.physmem.bytes_read::total 245888 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 127040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 127040 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1985 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 742 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3842 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1494025 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 558472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 839213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2891710 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1494025 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1494025 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1494025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 558472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 839213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2891710 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3842 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 126976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71296 # Number of bytes read from this memory +system.physmem.bytes_read::total 246144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 126976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 126976 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1984 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 748 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1114 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3846 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1493503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 563075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 838590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2895168 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1493503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1493503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1493503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 563075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 838590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2895168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3846 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3842 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3846 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 245888 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 246144 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 245888 # Total read bytes from the system interface side +system.physmem.bytesReadSys 246144 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -48,16 +48,16 @@ system.physmem.neitherReadNorWriteReqs 0 # Nu system.physmem.perBankRdBursts::0 309 # Per bank write bursts system.physmem.perBankRdBursts::1 220 # Per bank write bursts system.physmem.perBankRdBursts::2 142 # Per bank write bursts -system.physmem.perBankRdBursts::3 310 # Per bank write bursts +system.physmem.perBankRdBursts::3 309 # Per bank write bursts system.physmem.perBankRdBursts::4 300 # Per bank write bursts system.physmem.perBankRdBursts::5 302 # Per bank write bursts system.physmem.perBankRdBursts::6 262 # Per bank write bursts -system.physmem.perBankRdBursts::7 233 # Per bank write bursts +system.physmem.perBankRdBursts::7 237 # Per bank write bursts system.physmem.perBankRdBursts::8 252 # Per bank write bursts system.physmem.perBankRdBursts::9 219 # Per bank write bursts -system.physmem.perBankRdBursts::10 292 # Per bank write bursts +system.physmem.perBankRdBursts::10 291 # Per bank write bursts system.physmem.perBankRdBursts::11 194 # Per bank write bursts -system.physmem.perBankRdBursts::12 191 # Per bank write bursts +system.physmem.perBankRdBursts::12 193 # Per bank write bursts system.physmem.perBankRdBursts::13 211 # Per bank write bursts system.physmem.perBankRdBursts::14 211 # Per bank write bursts system.physmem.perBankRdBursts::15 194 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85031900500 # Total gap between requests +system.physmem.totGap 85018760500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3842 # Read request sizes (log2) +system.physmem.readPktSize::6 3846 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,16 +94,16 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 839 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 763 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 320.083879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.433795 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 309.783352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 232 30.41% 30.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 191 25.03% 55.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 88 11.53% 66.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 86 11.27% 78.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 27 3.54% 81.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 37 4.85% 86.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 11 1.44% 88.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17 2.23% 90.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 74 9.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 763 # Bytes accessed per row activation -system.physmem.totQLat 43141443 # Total ticks spent queuing -system.physmem.totMemAccLat 115178943 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19210000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11228.90 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 777 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 316.211068 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 199.877402 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.919917 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 237 30.50% 30.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 193 24.84% 55.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 84 10.81% 66.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 88 11.33% 77.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 4.50% 81.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 40 5.15% 87.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 20 2.57% 89.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13 1.67% 91.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 67 8.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 777 # Bytes accessed per row activation +system.physmem.totQLat 39111678 # Total ticks spent queuing +system.physmem.totMemAccLat 111224178 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19230000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10169.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29978.90 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28919.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.89 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.30 # Average read queue length when enqueuing +system.physmem.avgRdQLen 2.71 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3071 # Number of row buffer hits during reads +system.physmem.readRowHits 3067 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.93 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.75 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 22132196.90 # Average gap between requests -system.physmem.pageHitRate 79.93 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2729160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1489125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 22105761.96 # Average gap between requests +system.physmem.pageHitRate 79.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2744280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1497375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16231800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5553475200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2330695800 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 48971187750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 56875754235 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.921152 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81466351731 # Time in different power states -system.physmem_0.memoryStateTime::REF 2839200000 # Time in different power states +system.physmem_0.refreshEnergy 5552966640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2336092560 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48961790250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 56871322905 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.930183 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81450773508 # Time in different power states +system.physmem_0.memoryStateTime::REF 2838940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 720558269 # Time in different power states +system.physmem_0.memoryStateTime::ACT 728623992 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3016440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1645875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13548600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3129840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1707750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13712400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5553475200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2293230555 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 49004052000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 56868968670 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.841346 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 81522647918 # Time in different power states -system.physmem_1.memoryStateTime::REF 2839200000 # Time in different power states +system.physmem_1.refreshEnergy 5552966640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2289194100 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 49002929250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56863639980 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.839816 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 81519548908 # Time in different power states +system.physmem_1.memoryStateTime::REF 2838940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 665486082 # Time in different power states +system.physmem_1.memoryStateTime::ACT 659848592 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 85925704 # Number of BP lookups -system.cpu.branchPred.condPredicted 68401753 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6018362 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40106814 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39018678 # Number of BTB hits +system.cpu.branchPred.lookups 85912123 # Number of BP lookups +system.cpu.branchPred.condPredicted 68393040 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6015536 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 40101118 # Number of BTB lookups +system.cpu.branchPred.BTBHits 39014565 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.286905 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3705148 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81894 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.290467 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3703089 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81902 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,130 +381,130 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 170064089 # number of cpu cycles simulated +system.cpu.numCycles 170037809 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5613343 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349288276 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85925704 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42723826 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158284040 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12050671 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1737 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5613511 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349250633 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85912123 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42717654 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158261511 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12044973 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1577 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 2225 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78959765 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 17996 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169926703 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.150511 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.047128 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 2368 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78950648 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18008 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169901476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.150563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.047122 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17361476 10.22% 10.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30212798 17.78% 28.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31840839 18.74% 46.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90511590 53.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17358895 10.22% 10.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30204196 17.78% 27.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31835534 18.74% 46.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90502851 53.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169926703 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.505255 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.053863 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17566577 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17110905 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122676579 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6722207 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5850435 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11136607 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 190140 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306627324 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27647944 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5850435 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37756146 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8468505 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 579113 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108935441 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8337063 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278668040 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13416082 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3052051 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 841470 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2187697 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 36000 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 26450 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483113762 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1196983953 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297587542 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3006013 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169901476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.505253 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.053959 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17563828 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17110473 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 122657456 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6722156 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5847563 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11134699 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 190129 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 306600036 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27639970 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5847563 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37745979 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8468798 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 579877 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108923634 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8335625 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 278650711 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13412582 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3051453 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 842711 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2185712 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 35165 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 26489 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 483080894 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1196921588 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 297573906 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3006747 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190136833 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23525 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23424 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13336678 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34143660 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14476609 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2548114 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1810648 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 264825192 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45854 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214913936 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5193552 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 83235092 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219939501 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 638 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169926703 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.264745 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 190103965 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23523 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23430 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13336347 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 34142095 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14476543 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2549376 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1793123 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 264810332 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45855 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214902718 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5190620 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 83220233 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 219925398 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 639 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169901476 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.264867 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.017460 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52848454 31.10% 31.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36099011 21.24% 52.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65787739 38.72% 91.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13574201 7.99% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1569834 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47276 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 188 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52832101 31.10% 31.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36093158 21.24% 52.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65784259 38.72% 91.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13574357 7.99% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1570220 0.92% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47195 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 186 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169926703 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169901476 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35606881 66.11% 66.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 152777 0.28% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1069 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35605011 66.11% 66.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 152712 0.28% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1068 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35731 0.07% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 243 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 1036 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34373 0.06% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35741 0.07% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 1037 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34404 0.06% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14081261 26.14% 92.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3945561 7.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14078469 26.14% 92.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3945889 7.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167354642 77.87% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918991 0.43% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167344164 77.87% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 918970 0.43% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued @@ -525,91 +525,91 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 33018 0.02% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165174 0.08% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165202 0.08% 78.39% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 245708 0.11% 78.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460494 0.21% 78.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206680 0.10% 78.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460547 0.21% 78.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206694 0.10% 78.85% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32007537 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13373732 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32006921 14.89% 93.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13373534 6.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214913936 # Type of FU issued -system.cpu.iq.rate 1.263723 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53859137 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.250608 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654855291 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 346101904 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204603491 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3951973 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2011176 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806361 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266640239 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2132834 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1601131 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214902718 # Type of FU issued +system.cpu.iq.rate 1.263853 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53854775 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.250601 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654798543 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 346070765 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204597394 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3953764 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2012584 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806443 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266623027 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2134466 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1601141 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6247516 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7571 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7104 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1831975 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6245951 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7537 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7067 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1831909 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25920 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 745 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25713 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 804 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5850435 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5682032 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37041 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 264886958 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5847563 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5681873 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 37049 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 264872174 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34143660 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14476609 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23446 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3875 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29998 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7104 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3234550 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3248118 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6482668 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207528127 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30721496 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7385809 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 34142095 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14476543 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23447 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3919 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29963 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7067 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3232804 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3246682 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6479486 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207521850 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30720954 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7380868 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15912 # number of nop insts executed -system.cpu.iew.exec_refs 43861162 # number of memory reference insts executed -system.cpu.iew.exec_branches 44936179 # Number of branches executed -system.cpu.iew.exec_stores 13139666 # Number of stores executed -system.cpu.iew.exec_rate 1.220294 # Inst execution rate -system.cpu.iew.wb_sent 206744895 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206409852 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129477271 # num instructions producing a value -system.cpu.iew.wb_consumers 221697359 # num instructions consuming a value +system.cpu.iew.exec_nop 15987 # number of nop insts executed +system.cpu.iew.exec_refs 43860782 # number of memory reference insts executed +system.cpu.iew.exec_branches 44934590 # Number of branches executed +system.cpu.iew.exec_stores 13139828 # Number of stores executed +system.cpu.iew.exec_rate 1.220445 # Inst execution rate +system.cpu.iew.wb_sent 206738830 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206403837 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129472700 # num instructions producing a value +system.cpu.iew.wb_consumers 221699640 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.213718 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584027 # average fanout of values written-back +system.cpu.iew.wb_rate 1.213870 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.584000 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69541697 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69532932 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5843462 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158482976 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.146182 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.646662 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5840613 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158460459 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146345 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.646701 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73704941 46.51% 46.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41274815 26.04% 72.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22552900 14.23% 86.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9628649 6.08% 92.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3549516 2.24% 95.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2148015 1.36% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1280291 0.81% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 986897 0.62% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3356952 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73681032 46.50% 46.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41276330 26.05% 72.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22553900 14.23% 86.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9626912 6.08% 92.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3550160 2.24% 95.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2147757 1.36% 96.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1281176 0.81% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 986541 0.62% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3356651 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158482976 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158460459 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,374 +655,380 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3356952 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 406312862 # The number of ROB reads -system.cpu.rob.rob_writes 513841850 # The number of ROB writes -system.cpu.timesIdled 3415 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 137386 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3356651 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 406281881 # The number of ROB reads +system.cpu.rob.rob_writes 513821502 # The number of ROB writes +system.cpu.timesIdled 3434 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 136333 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.987006 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.987006 # CPI: Total CPI of All Threads -system.cpu.ipc 1.013165 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.013165 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218961575 # number of integer regfile reads -system.cpu.int_regfile_writes 114515726 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904225 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441500 # number of floating regfile writes -system.cpu.cc_regfile_reads 709589041 # number of cc regfile reads -system.cpu.cc_regfile_writes 229545726 # number of cc regfile writes -system.cpu.misc_regfile_reads 59313943 # number of misc regfile reads +system.cpu.cpi 0.986853 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.986853 # CPI: Total CPI of All Threads +system.cpu.ipc 1.013322 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.013322 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218956398 # number of integer regfile reads +system.cpu.int_regfile_writes 114512064 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904391 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441624 # number of floating regfile writes +system.cpu.cc_regfile_reads 709567727 # number of cc regfile reads +system.cpu.cc_regfile_writes 229536120 # number of cc regfile writes +system.cpu.misc_regfile_reads 59314176 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.replacements 72899 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.418278 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41116599 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73411 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.087712 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 506067250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.418278 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998864 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998864 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 72863 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.419653 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41115439 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73375 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 560.346698 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 504093500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.419653 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998867 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998867 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82531693 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82531693 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28730266 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28730266 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341417 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341417 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82529747 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82529747 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28729201 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28729201 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341321 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341321 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22149 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22149 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41071683 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41071683 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41072044 # number of overall hits -system.cpu.dcache.overall_hits::total 41072044 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89294 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89294 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22870 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22870 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112164 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112164 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112282 # number of overall misses -system.cpu.dcache.overall_misses::total 112282 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 853196487 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 853196487 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 241173427 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 241173427 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2319500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2319500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1094369914 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1094369914 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1094369914 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1094369914 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28819560 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28819560 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 41070522 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41070522 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41070883 # number of overall hits +system.cpu.dcache.overall_hits::total 41070883 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89405 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89405 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22966 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22966 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 117 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 117 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 112371 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112371 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112488 # number of overall misses +system.cpu.dcache.overall_misses::total 112488 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 853901000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 853901000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 240852499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 240852499 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2309500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2309500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1094753499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1094753499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1094753499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1094753499 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28818606 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28818606 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 478 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 478 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22408 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22408 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41183847 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41183847 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41184326 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41184326 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003098 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003098 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001850 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001850 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011603 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011603 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002723 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002723 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002726 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002726 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9554.913958 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9554.913958 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10545.405641 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10545.405641 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8921.153846 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8921.153846 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9756.873097 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9756.873097 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9746.619351 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9746.619351 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 167 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 9765 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41182893 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41182893 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41183371 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41183371 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003102 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003102 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001857 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001857 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.244770 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.244770 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011558 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011558 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002729 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002729 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002731 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002731 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9550.931156 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9550.931156 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10487.350823 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10487.350823 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8916.988417 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8916.988417 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9742.313399 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9742.313399 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9732.180313 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9732.180313 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10552 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 848 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 11.515330 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 865 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 12.198844 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 64878 # number of writebacks -system.cpu.dcache.writebacks::total 64878 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24567 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24567 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14301 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14301 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38868 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38868 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38868 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38868 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64727 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64727 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8569 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8569 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 115 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 115 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 73296 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 73296 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73411 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73411 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 526755010 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 526755010 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81248758 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 81248758 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 920500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 920500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 608003768 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 608003768 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 608924268 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 608924268 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002246 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002246 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.240084 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.240084 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001780 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses +system.cpu.dcache.writebacks::writebacks 64850 # number of writebacks +system.cpu.dcache.writebacks::total 64850 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24706 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24706 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14404 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14404 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 39110 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39110 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39110 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39110 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64699 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64699 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8562 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8562 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 114 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 114 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 73261 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 73261 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73375 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73375 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 558347000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 558347000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85131499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85131499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 970000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 970000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 643478499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 643478499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 644448499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 644448499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.238494 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.238494 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001779 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001782 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8138.103264 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8138.103264 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9481.708251 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9481.708251 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8004.347826 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8004.347826 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8295.183475 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8295.183475 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8294.727875 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8294.727875 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8629.917000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8629.917000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9942.945457 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9942.945457 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8508.771930 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8508.771930 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8783.370402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8783.370402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8782.943768 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8782.943768 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 54462 # number of replacements -system.cpu.icache.tags.tagsinuse 510.603252 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78902001 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54974 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1435.260323 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 84278847250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.603252 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997272 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997272 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 54433 # number of replacements +system.cpu.icache.tags.tagsinuse 510.604366 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78892637 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54945 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1435.847429 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84263927500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.604366 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997274 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997274 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157974458 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157974458 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78902001 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78902001 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78902001 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78902001 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78902001 # number of overall hits -system.cpu.icache.overall_hits::total 78902001 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57741 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57741 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57741 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57741 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57741 # number of overall misses -system.cpu.icache.overall_misses::total 57741 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 606045932 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 606045932 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 606045932 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 606045932 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 606045932 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 606045932 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78959742 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78959742 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78959742 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78959742 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78959742 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78959742 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000731 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000731 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000731 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000731 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000731 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000731 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10495.937583 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10495.937583 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10495.937583 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10495.937583 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10495.937583 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10495.937583 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 55224 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 157956201 # Number of tag accesses +system.cpu.icache.tags.data_accesses 157956201 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78892637 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78892637 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78892637 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78892637 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78892637 # number of overall hits +system.cpu.icache.overall_hits::total 78892637 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57991 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57991 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 57991 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 57991 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 57991 # number of overall misses +system.cpu.icache.overall_misses::total 57991 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 602655456 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 602655456 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 602655456 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 602655456 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 602655456 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 602655456 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78950628 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78950628 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78950628 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78950628 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78950628 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78950628 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000735 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000735 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000735 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000735 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000735 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000735 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10392.223897 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10392.223897 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10392.223897 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10392.223897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10392.223897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10392.223897 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 58612 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2764 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2849 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.979740 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.572833 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2767 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2767 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2767 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2767 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2767 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2767 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54974 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 54974 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 54974 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 54974 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 54974 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 54974 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 508400239 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 508400239 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 508400239 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 508400239 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 508400239 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 508400239 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3046 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3046 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3046 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3046 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3046 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3046 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54945 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 54945 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 54945 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 54945 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 54945 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 54945 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 535420965 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 535420965 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 535420965 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 535420965 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 535420965 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 535420965 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000696 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000696 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000696 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9248.012497 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9248.012497 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9248.012497 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 9248.012497 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9248.012497 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 9248.012497 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9744.671308 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9744.671308 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9744.671308 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 9744.671308 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9744.671308 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.020793 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1818 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1818 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 235 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 235 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1984 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1984 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 513 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 513 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1984 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 748 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2732 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1984 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 748 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1818 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4550 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 70301588 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 70301588 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16173000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16173000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 123686500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 123686500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33594500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33594500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 123686500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 49767500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 173454000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 123686500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 49767500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 70301588 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 243755588 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027443 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027443 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036108 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010107 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.021241 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036108 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010107 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027218 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027218 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.036109 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.007924 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.007924 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010194 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.021291 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010194 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.035300 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60019.776826 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65166.831683 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61063.657430 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39193.573407 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 39193.573407 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67258.438819 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67258.438819 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60019.776826 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65834.905660 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61602.037770 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60019.776826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65834.905660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39193.573407 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52677.219109 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.035458 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38669.740374 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 38669.740374 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68821.276596 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68821.276596 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62341.985887 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62341.985887 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65486.354776 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65486.354776 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62341.985887 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66534.090909 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63489.751098 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62341.985887 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66534.090909 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38669.740374 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53572.656703 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 119749 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 119749 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 64878 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2153 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8636 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8636 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109948 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211700 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 321648 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3518336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8850496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 12368832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2153 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 195416 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.011018 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.104385 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 119686 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 64850 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 51933 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2160 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54945 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64741 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 155973 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217450 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 373423 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8846400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12362880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2160 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 257776 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.008379 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.091155 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 193263 98.90% 98.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2153 1.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 255616 99.16% 99.16% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2160 0.84% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 195416 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 161509500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 257776 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 192658000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82870477 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 82430973 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110219231 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 110066991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3605 # Transaction distribution -system.membus.trans_dist::ReadResp 3605 # Transaction distribution -system.membus.trans_dist::ReadExReq 237 # Transaction distribution -system.membus.trans_dist::ReadExResp 237 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7684 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7684 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 245888 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 245888 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3611 # Transaction distribution +system.membus.trans_dist::ReadExReq 235 # Transaction distribution +system.membus.trans_dist::ReadExResp 235 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3611 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7692 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7692 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 246144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 246144 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3842 # Request fanout histogram +system.membus.snoop_fanout::samples 3846 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3842 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3846 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3842 # Request fanout histogram -system.membus.reqLayer0.occupancy 4969720 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3846 # Request fanout histogram +system.membus.reqLayer0.occupancy 5081597 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20244552 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20277583 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 1d32cdbce..8e968af2a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.081225 # Number of seconds simulated -sim_ticks 81224844500 # Number of ticks simulated -final_tick 81224844500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.081371 # Number of seconds simulated +sim_ticks 81371461000 # Number of ticks simulated +final_tick 81371461000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91947 # Simulator instruction rate (inst/s) -host_op_rate 154111 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56548085 # Simulator tick rate (ticks/s) -host_mem_usage 347388 # Number of bytes of host memory used -host_seconds 1436.39 # Real time elapsed on the host +host_inst_rate 90424 # Simulator instruction rate (inst/s) +host_op_rate 151559 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55711800 # Simulator tick rate (ticks/s) +host_mem_usage 348672 # Number of bytes of host memory used +host_seconds 1460.58 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 224768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125760 # Number of bytes read from this memory -system.physmem.bytes_read::total 350528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 224768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 224768 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3512 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5477 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2767232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1548295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4315527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2767232 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2767232 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2767232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1548295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4315527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5477 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 224128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125504 # Number of bytes read from this memory +system.physmem.bytes_read::total 349632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 224128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 224128 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3502 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1961 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5463 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2754381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1542359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4296740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2754381 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2754381 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2754381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1542359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4296740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5463 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5477 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5463 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 350528 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 349632 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 350528 # Total read bytes from the system interface side +system.physmem.bytesReadSys 349632 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 298 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 295 # Per bank write bursts -system.physmem.perBankRdBursts::1 355 # Per bank write bursts -system.physmem.perBankRdBursts::2 457 # Per bank write bursts -system.physmem.perBankRdBursts::3 353 # Per bank write bursts -system.physmem.perBankRdBursts::4 337 # Per bank write bursts -system.physmem.perBankRdBursts::5 331 # Per bank write bursts -system.physmem.perBankRdBursts::6 400 # Per bank write bursts -system.physmem.perBankRdBursts::7 389 # Per bank write bursts -system.physmem.perBankRdBursts::8 346 # Per bank write bursts -system.physmem.perBankRdBursts::9 296 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 312 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 292 # Per bank write bursts +system.physmem.perBankRdBursts::1 354 # Per bank write bursts +system.physmem.perBankRdBursts::2 456 # Per bank write bursts +system.physmem.perBankRdBursts::3 360 # Per bank write bursts +system.physmem.perBankRdBursts::4 330 # Per bank write bursts +system.physmem.perBankRdBursts::5 342 # Per bank write bursts +system.physmem.perBankRdBursts::6 399 # Per bank write bursts +system.physmem.perBankRdBursts::7 387 # Per bank write bursts +system.physmem.perBankRdBursts::8 324 # Per bank write bursts +system.physmem.perBankRdBursts::9 282 # Per bank write bursts system.physmem.perBankRdBursts::10 240 # Per bank write bursts -system.physmem.perBankRdBursts::11 297 # Per bank write bursts +system.physmem.perBankRdBursts::11 270 # Per bank write bursts system.physmem.perBankRdBursts::12 220 # Per bank write bursts -system.physmem.perBankRdBursts::13 472 # Per bank write bursts -system.physmem.perBankRdBursts::14 395 # Per bank write bursts -system.physmem.perBankRdBursts::15 294 # Per bank write bursts +system.physmem.perBankRdBursts::13 487 # Per bank write bursts +system.physmem.perBankRdBursts::14 392 # Per bank write bursts +system.physmem.perBankRdBursts::15 328 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 81224754500 # Total gap between requests +system.physmem.totGap 81371407000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5477 # Read request sizes (log2) +system.physmem.readPktSize::6 5463 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 914 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,174 +186,173 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1132 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 308.296820 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 177.870491 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.897635 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 457 40.37% 40.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 236 20.85% 61.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 108 9.54% 70.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 58 5.12% 75.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 52 4.59% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 57 5.04% 85.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 15 1.33% 86.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 18 1.59% 88.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 131 11.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1132 # Bytes accessed per row activation -system.physmem.totQLat 39829000 # Total ticks spent queuing -system.physmem.totMemAccLat 142522750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 27385000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7272.05 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1133 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 307.177405 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.606569 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.434363 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 453 39.98% 39.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 241 21.27% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 107 9.44% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 66 5.83% 76.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 42 3.71% 80.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 53 4.68% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 30 2.65% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 18 1.59% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 123 10.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1133 # Bytes accessed per row activation +system.physmem.totQLat 39364000 # Total ticks spent queuing +system.physmem.totMemAccLat 141795250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 27315000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7205.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26022.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25955.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.32 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.30 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4337 # Number of row buffer hits during reads +system.physmem.readRowHits 4322 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.19 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.11 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 14830154.19 # Average gap between requests -system.physmem.pageHitRate 79.19 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4944240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2697750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 22612200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 14895004.03 # Average gap between requests +system.physmem.pageHitRate 79.11 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4898880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2673000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 22627800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5304789360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2574291285 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 46473030000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 54382364835 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.579902 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 77308994750 # Time in different power states -system.physmem_0.memoryStateTime::REF 2712060000 # Time in different power states +system.physmem_0.refreshEnergy 5314452000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2576418525 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 46559935500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 54481005705 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.574677 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 77452365250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2717000000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1198731250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1197234500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3598560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1963500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19773000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3643920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1988250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19640400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5304789360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2411784000 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 46615580250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 54357488670 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.273616 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 77550451000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2712060000 # Time in different power states +system.physmem_1.refreshEnergy 5314452000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2400589485 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 46714163250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 54454477305 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.248755 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 77713281250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2717000000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 960225000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 939125250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 21757824 # Number of BP lookups -system.cpu.branchPred.condPredicted 21757824 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1548941 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 13682195 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12857487 # Number of BTB hits +system.cpu.branchPred.lookups 21769917 # Number of BP lookups +system.cpu.branchPred.condPredicted 21769917 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1549122 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 13731962 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12878566 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.972400 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1522808 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21281 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.785331 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1523299 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21478 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 162449690 # number of cpu cycles simulated +system.cpu.numCycles 162742923 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27167357 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 241462052 # Number of instructions fetch has processed -system.cpu.fetch.Branches 21757824 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 14380295 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 133204520 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3672137 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 11 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 3242 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 32817 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 27183337 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 241535825 # Number of instructions fetch has processed +system.cpu.fetch.Branches 21769917 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 14401865 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 133481172 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3672135 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 7 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 3449 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 35973 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 121 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 26014450 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 320059 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 162244149 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.449323 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.349447 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 110 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 26033005 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 318152 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 162540128 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.445335 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.347989 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 96544935 59.51% 59.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4966288 3.06% 62.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3924303 2.42% 64.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4589791 2.83% 67.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4444336 2.74% 70.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5042325 3.11% 73.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5076481 3.13% 76.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3889378 2.40% 79.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33766312 20.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 96819226 59.57% 59.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4970692 3.06% 62.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3926504 2.42% 65.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4600449 2.83% 67.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4436163 2.73% 70.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5045508 3.10% 73.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5083113 3.13% 76.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3898601 2.40% 79.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33759872 20.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162244149 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.133936 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.486381 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16503411 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96610290 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 25882430 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21411950 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1836068 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 352729241 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1836068 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24442767 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 33233774 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 31009 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 38303751 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 64396780 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 343252745 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1943 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 56953505 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7545423 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 167940 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 397342568 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 949709399 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 627052131 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4618257 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 162540128 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.133769 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.484156 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16504764 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96892991 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 25874540 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21431766 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1836067 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 352818767 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1836067 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24444805 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 33422530 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 30828 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 38315708 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 64490190 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 343379412 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1374 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 57139077 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7429063 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 172376 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 397453727 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 950141626 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 627304694 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4642412 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 137913118 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2151 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2060 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 120010907 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 87039709 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 31137080 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 61853756 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 20927707 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 331596276 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4834 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 264603975 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 77857 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 110237726 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 225639096 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3589 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162244149 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.630900 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.539803 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 138024277 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2171 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2092 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 120106098 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 87123680 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 31143046 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 62089518 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21014033 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 331702995 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4700 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 264529155 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 75427 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 110344311 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 226235086 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3455 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 162540128 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.627470 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.538199 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 42788422 26.37% 26.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 47622129 29.35% 55.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33320454 20.54% 76.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18328192 11.30% 87.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11302199 6.97% 94.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4922011 3.03% 97.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2609014 1.61% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 930397 0.57% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 421331 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 42962851 26.43% 26.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 47766675 29.39% 55.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33381943 20.54% 76.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18299706 11.26% 87.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11254917 6.92% 94.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4928041 3.03% 97.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2601211 1.60% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 925935 0.57% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 418849 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162244149 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 162540128 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 230632 7.18% 7.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 228422 7.18% 7.18% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 7.18% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 7.18% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.18% # attempts to use FU when none available @@ -382,118 +381,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.18% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.18% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.18% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2590896 80.61% 87.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 392432 12.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2563241 80.56% 87.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 390075 12.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211493 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 165364025 62.49% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 786761 0.30% 63.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7038559 2.66% 65.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1211557 0.46% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 66257169 25.04% 91.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22734411 8.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211775 0.46% 0.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 165335672 62.50% 62.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 786316 0.30% 63.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7038827 2.66% 65.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1212035 0.46% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 66231753 25.04% 91.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22712777 8.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 264603975 # Type of FU issued -system.cpu.iq.rate 1.628836 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3213960 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012146 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 689757647 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 437892717 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 258330357 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4986269 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4261617 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2393080 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 264097165 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2509277 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18796485 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 264529155 # Type of FU issued +system.cpu.iq.rate 1.625442 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3181738 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012028 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 689869496 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 438078029 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 258256761 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4986107 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4289171 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2392105 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263990006 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2509112 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18745493 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 30390155 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14027 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 322538 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10621363 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 30474102 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13683 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 322031 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10627329 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 52082 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 52743 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1836068 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 14114838 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 500285 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 331601110 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 108836 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 87039742 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 31137080 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2060 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 401860 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 61208 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 322538 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 680213 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 929259 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1609472 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 262268386 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 65330198 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2335589 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1836067 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 14124717 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 495168 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 331707695 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 107609 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 87123689 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 31143046 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2075 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 394182 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 62934 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 322031 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 682027 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 925981 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1608008 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 262198462 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 65303975 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2330693 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 87858182 # number of memory reference insts executed -system.cpu.iew.exec_branches 14520351 # Number of branches executed -system.cpu.iew.exec_stores 22527984 # Number of stores executed -system.cpu.iew.exec_rate 1.614459 # Inst execution rate -system.cpu.iew.wb_sent 261554043 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 260723437 # cumulative count of insts written-back -system.cpu.iew.wb_producers 208617070 # num instructions producing a value -system.cpu.iew.wb_consumers 375029707 # num instructions consuming a value +system.cpu.iew.exec_refs 87811155 # number of memory reference insts executed +system.cpu.iew.exec_branches 14511685 # Number of branches executed +system.cpu.iew.exec_stores 22507180 # Number of stores executed +system.cpu.iew.exec_rate 1.611121 # Inst execution rate +system.cpu.iew.wb_sent 261483321 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 260648866 # cumulative count of insts written-back +system.cpu.iew.wb_producers 208559295 # num instructions producing a value +system.cpu.iew.wb_consumers 374938421 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.604949 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.556268 # average fanout of values written-back +system.cpu.iew.wb_rate 1.601599 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.556249 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 110244875 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 110351288 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1552031 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147195030 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.503878 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.943897 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1552443 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147477365 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.500999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.940236 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 47434016 32.23% 32.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57618157 39.14% 71.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14262797 9.69% 81.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11889308 8.08% 89.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4213027 2.86% 92.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2877009 1.95% 93.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 914800 0.62% 94.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1061572 0.72% 95.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6924344 4.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 47558134 32.25% 32.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57784481 39.18% 71.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14247523 9.66% 81.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11907169 8.07% 89.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4233466 2.87% 92.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2889588 1.96% 93.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 908406 0.62% 94.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1058674 0.72% 95.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6889924 4.67% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147195030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 147477365 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -539,75 +538,74 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6924344 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 471878945 # The number of ROB reads -system.cpu.rob.rob_writes 678308439 # The number of ROB writes -system.cpu.timesIdled 2694 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 205541 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6889924 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 472302113 # The number of ROB reads +system.cpu.rob.rob_writes 678534776 # The number of ROB writes +system.cpu.timesIdled 2601 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 202795 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.230016 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.230016 # CPI: Total CPI of All Threads -system.cpu.ipc 0.812998 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.812998 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 454025160 # number of integer regfile reads -system.cpu.int_regfile_writes 236935746 # number of integer regfile writes -system.cpu.fp_regfile_reads 3267968 # number of floating regfile reads -system.cpu.fp_regfile_writes 2053127 # number of floating regfile writes -system.cpu.cc_regfile_reads 102766500 # number of cc regfile reads -system.cpu.cc_regfile_writes 60037026 # number of cc regfile writes -system.cpu.misc_regfile_reads 135494920 # number of misc regfile reads +system.cpu.cpi 1.232236 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.232236 # CPI: Total CPI of All Threads +system.cpu.ipc 0.811533 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.811533 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 453858264 # number of integer regfile reads +system.cpu.int_regfile_writes 236894069 # number of integer regfile writes +system.cpu.fp_regfile_reads 3268800 # number of floating regfile reads +system.cpu.fp_regfile_writes 2052370 # number of floating regfile writes +system.cpu.cc_regfile_reads 102728686 # number of cc regfile reads +system.cpu.cc_regfile_writes 60021475 # number of cc regfile writes +system.cpu.misc_regfile_reads 135450288 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.replacements 56 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.236298 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66889390 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2008 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33311.449203 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 22 # number of replacements +system.cpu.dcache.tags.tagsinuse 1449.922463 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 66913357 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1999 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33473.415208 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1448.236298 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353573 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353573 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1952 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 484 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1414 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.476562 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 133785736 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 133785736 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 46375033 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 46375033 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513891 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513891 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66888924 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66888924 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66888924 # number of overall hits -system.cpu.dcache.overall_hits::total 66888924 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1100 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1100 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1840 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1840 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2940 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2940 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2940 # number of overall misses -system.cpu.dcache.overall_misses::total 2940 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 68941167 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 68941167 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 128874548 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 128874548 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 197815715 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 197815715 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 197815715 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 197815715 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 46376133 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 46376133 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1449.922463 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353985 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353985 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1977 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 483 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1444 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.482666 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 133833717 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 133833717 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 46399026 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 46399026 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513875 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513875 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 66912901 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66912901 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66912901 # number of overall hits +system.cpu.dcache.overall_hits::total 66912901 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1102 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1102 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1856 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1856 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2958 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2958 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2958 # number of overall misses +system.cpu.dcache.overall_misses::total 2958 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 70369000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 70369000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 128824000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 128824000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 199193000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 199193000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 199193000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 199193000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 46400128 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 46400128 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66891864 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66891864 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66891864 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66891864 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 66915859 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66915859 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66915859 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66915859 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses @@ -616,258 +614,264 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_miss_rate::total 0.000044 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000044 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000044 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62673.788182 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62673.788182 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70040.515217 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70040.515217 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67284.256803 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67284.256803 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67284.256803 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67284.256803 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 492 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 82 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63855.716878 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63855.716878 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69409.482759 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69409.482759 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67340.432725 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67340.432725 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67340.432725 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67340.432725 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 318 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 52 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 63.600000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 52 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 13 # number of writebacks -system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 632 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 632 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 633 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 633 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 633 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 633 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 468 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 468 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1839 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1839 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2307 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2307 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2307 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2307 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36256250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36256250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125371702 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 125371702 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161627952 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161627952 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161627952 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161627952 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 11 # number of writebacks +system.cpu.dcache.writebacks::total 11 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 641 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 641 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 643 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 643 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 643 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 643 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 461 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 461 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1854 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1854 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2315 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2315 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2315 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2315 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36642000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36642000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126830000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 126830000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163472000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 163472000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163472000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 163472000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000090 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000090 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77470.619658 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77470.619658 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68173.845568 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68173.845568 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70059.797139 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70059.797139 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70059.797139 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70059.797139 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79483.731020 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79483.731020 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68408.845739 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68408.845739 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70614.254860 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70614.254860 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70614.254860 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70614.254860 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5865 # number of replacements -system.cpu.icache.tags.tagsinuse 1646.159130 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 26003921 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 7839 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3317.249777 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5619 # number of replacements +system.cpu.icache.tags.tagsinuse 1637.148267 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 26022644 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 7593 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3427.188726 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1646.159130 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.803789 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.803789 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1637.148267 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.799389 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.799389 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1974 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 898 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 773 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 882 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 786 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.963867 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 52037036 # Number of tag accesses -system.cpu.icache.tags.data_accesses 52037036 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 26003921 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 26003921 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 26003921 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 26003921 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 26003921 # number of overall hits -system.cpu.icache.overall_hits::total 26003921 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 10528 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 10528 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 10528 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 10528 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 10528 # number of overall misses -system.cpu.icache.overall_misses::total 10528 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 430452747 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 430452747 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 430452747 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 430452747 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 430452747 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 430452747 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 26014449 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 26014449 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 26014449 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 26014449 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 26014449 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 26014449 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000405 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000405 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000405 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000405 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000405 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000405 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40886.469130 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 40886.469130 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 40886.469130 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 40886.469130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 40886.469130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 40886.469130 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1891 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 52073916 # Number of tag accesses +system.cpu.icache.tags.data_accesses 52073916 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 26022649 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 26022649 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 26022649 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 26022649 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 26022649 # number of overall hits +system.cpu.icache.overall_hits::total 26022649 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 10355 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 10355 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 10355 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 10355 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 10355 # number of overall misses +system.cpu.icache.overall_misses::total 10355 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 419159499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 419159499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 419159499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 419159499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 419159499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 419159499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 26033004 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 26033004 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 26033004 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 26033004 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 26033004 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 26033004 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000398 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000398 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000398 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000398 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000398 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000398 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40478.947272 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 40478.947272 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 40478.947272 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 40478.947272 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40478.947272 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40478.947272 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1340 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 28 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 67.535714 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 51.538462 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2389 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2389 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2389 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2389 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2389 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2389 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8139 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 8139 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 8139 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 8139 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 8139 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 8139 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322188751 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 322188751 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322188751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 322188751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322188751 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 322188751 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39585.790761 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39585.790761 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39585.790761 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39585.790761 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39585.790761 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39585.790761 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2445 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2445 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2445 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2445 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2445 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2445 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7910 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7910 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7910 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7910 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7910 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7910 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 320594000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 320594000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 320594000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 320594000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 320594000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 320594000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000304 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000304 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000304 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000304 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000304 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000304 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40530.214918 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40530.214918 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40530.214918 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40530.214918 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40530.214918 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40530.214918 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2629.714027 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4366 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3947 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.106157 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2621.537078 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9541 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3929 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.428353 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2.821104 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2311.277195 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 315.615728 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000086 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.070535 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.009632 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.080253 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3947 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 0.832574 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2306.260557 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 314.443947 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000025 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.070381 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.009596 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.080003 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 230285500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 230285500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31255500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31255500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230285500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 130354500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 360640000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230285500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 130354500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 360640000 # number of overall MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987342 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987342 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996101 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996101 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.461285 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.461285 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.930435 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.930435 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461285 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980990 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.569582 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461285 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980990 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.569582 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20717.948718 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20717.948718 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64643.835616 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64643.835616 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65739.508992 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65739.508992 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73026.869159 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73026.869159 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65739.508992 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66473.482917 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66002.928258 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65739.508992 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66473.482917 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66002.928258 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 8606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 8605 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1541 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15978 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4627 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 20605 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 501696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 631040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 299 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10459 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 8368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 5412 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 316 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 316 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7910 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 460 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20904 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4651 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 25555 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 485888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 614528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 316 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 15866 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 10459 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 15866 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10459 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5242500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 15866 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7944000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 12871748 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 11862000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3552548 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3157498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3944 # Transaction distribution -system.membus.trans_dist::ReadResp 3944 # Transaction distribution -system.membus.trans_dist::UpgradeReq 298 # Transaction distribution -system.membus.trans_dist::UpgradeResp 298 # Transaction distribution +system.membus.trans_dist::ReadResp 3929 # Transaction distribution +system.membus.trans_dist::UpgradeReq 312 # Transaction distribution +system.membus.trans_dist::UpgradeResp 312 # Transaction distribution system.membus.trans_dist::ReadExReq 1533 # Transaction distribution system.membus.trans_dist::ReadExResp 1533 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11550 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 350528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 350528 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3930 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11549 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11549 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11549 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 349568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 349568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 349568 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 5775 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram @@ -983,9 +993,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5775 # Request fanout histogram -system.membus.reqLayer0.occupancy 6990000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7111000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 29627952 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 29581688 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |