diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/70.twolf | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/70.twolf')
36 files changed, 2377 insertions, 1601 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 64fd65cd8..1763cd3d7 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -45,6 +52,7 @@ div32RepeatRate=1 div8Latency=1 div8RepeatRate=1 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 @@ -57,6 +65,7 @@ globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 +interrupts=system.cpu.interrupts itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -72,6 +81,7 @@ multRepeatRate=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 stageTracing=false stageWidth=4 @@ -93,20 +103,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -129,20 +132,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -150,6 +146,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -165,20 +164,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -202,7 +194,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout index ab1cbef0e..ddac6bec8 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:57:18 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:36:18 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index db43e1bd8..7525585e3 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.041834 # Nu sim_ticks 41833966000 # Number of ticks simulated final_tick 41833966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111295 # Simulator instruction rate (inst/s) -host_tick_rate 50660994 # Simulator tick rate (ticks/s) -host_mem_usage 211656 # Number of bytes of host memory used -host_seconds 825.76 # Real time elapsed on the host +host_inst_rate 151560 # Simulator instruction rate (inst/s) +host_op_rate 151560 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68989742 # Simulator tick rate (ticks/s) +host_mem_usage 213560 # Number of bytes of host memory used +host_seconds 606.38 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated +sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read 316032 # Number of bytes read from this memory system.physmem.bytes_inst_read 178816 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -68,9 +70,10 @@ system.cpu.comNops 7723346 # Nu system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed system.cpu.comInts 43665352 # Number of Integer instructions committed system.cpu.comFloats 3775974 # Number of Floating Point instructions committed -system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 91903056 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) system.cpu.cpi 0.910393 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 0.910393 # CPI: Total CPI of All Threads @@ -124,26 +127,39 @@ system.cpu.icache.total_refs 9979713 # To system.cpu.icache.sampled_refs 9436 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1057.621132 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1491.782957 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.728410 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 9979713 # number of ReadReq hits -system.cpu.icache.demand_hits 9979713 # number of demand (read+write) hits -system.cpu.icache.overall_hits 9979713 # number of overall hits -system.cpu.icache.ReadReq_misses 11486 # number of ReadReq misses -system.cpu.icache.demand_misses 11486 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11486 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 291407500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 291407500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 291407500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 9991199 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 9991199 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 9991199 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.001150 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.001150 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.001150 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 25370.668640 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 25370.668640 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 25370.668640 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1491.782957 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728410 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728410 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 9979713 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 9979713 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 9979713 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 9979713 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 9979713 # number of overall hits +system.cpu.icache.overall_hits::total 9979713 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11486 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11486 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11486 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11486 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11486 # number of overall misses +system.cpu.icache.overall_misses::total 11486 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 291407500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 291407500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 291407500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 291407500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 291407500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 291407500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9991199 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9991199 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9991199 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9991199 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9991199 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9991199 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001150 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001150 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001150 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25370.668640 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25370.668640 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25370.668640 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 69500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -152,27 +168,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 17375 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 2050 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 2050 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 2050 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 9436 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 9436 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 9436 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 222700000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 222700000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 222700000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000944 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000944 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000944 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23601.102162 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23601.102162 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23601.102162 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2050 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2050 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2050 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2050 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2050 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2050 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9436 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 9436 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 9436 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 9436 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 9436 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 9436 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 222700000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 222700000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 222700000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 222700000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 222700000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 222700000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23601.102162 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23601.102162 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23601.102162 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.tagsinuse 1441.532122 # Cycle average of tags in use @@ -180,32 +199,49 @@ system.cpu.dcache.total_refs 26491206 # To system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11916.871795 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1441.532122 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.351937 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 19995645 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6495561 # number of WriteReq hits -system.cpu.dcache.demand_hits 26491206 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 26491206 # number of overall hits -system.cpu.dcache.ReadReq_misses 553 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 5542 # number of WriteReq misses -system.cpu.dcache.demand_misses 6095 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 6095 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 28393500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 303801000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 332194500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 332194500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000028 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000852 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 51344.484629 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 54817.935763 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54502.789171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54502.789171 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1441.532122 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.351937 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.351937 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995645 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995645 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6495561 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6495561 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26491206 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26491206 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26491206 # number of overall hits +system.cpu.dcache.overall_hits::total 26491206 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 553 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 553 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5542 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5542 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6095 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6095 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6095 # number of overall misses +system.cpu.dcache.overall_misses::total 6095 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28393500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28393500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 303801000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 303801000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 332194500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 332194500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 332194500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 332194500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000852 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000230 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000230 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51344.484629 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54817.935763 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54502.789171 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54502.789171 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 41047000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -214,32 +250,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 49814.320388 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 78 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 3794 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 3872 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 3872 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 23213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 92997500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 116210500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 116210500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48869.473684 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53202.231121 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52276.428250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52276.428250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3794 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3794 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3872 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3872 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3872 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3872 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23213000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23213000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92997500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92997500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116210500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 116210500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116210500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 116210500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48869.473684 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53202.231121 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.428250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.428250 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2189.253602 # Cycle average of tags in use @@ -247,36 +291,75 @@ system.cpu.l2cache.total_refs 6704 # To system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.042657 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2171.415543 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.838059 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.066266 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000544 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 6695 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6721 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6721 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3216 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 4938 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 168327500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 90565000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 258892500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 258892500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 9911 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 11659 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 11659 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.324488 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.423535 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.423535 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52340.640547 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52592.915215 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52428.614824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52428.614824 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 17.838059 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1820.375269 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.040274 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055553 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010713 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066811 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 6642 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6695 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 6642 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6721 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 6642 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits +system.cpu.l2cache.overall_hits::total 6721 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2794 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4938 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses +system.cpu.l2cache.overall_misses::total 4938 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 146193000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22134500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 168327500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90565000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 90565000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 146193000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112699500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 258892500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 146193000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112699500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 258892500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 9436 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 9911 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 9436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 11659 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9436 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 11659 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.296100 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.296100 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.296100 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52323.908375 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52451.421801 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52592.915215 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52323.908375 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52565.065299 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52323.908375 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52565.065299 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -285,30 +368,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3216 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 4938 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 4938 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 129053500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 69344000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 198397500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 198397500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.324488 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.423535 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.423535 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40128.575871 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40269.454123 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40177.703524 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40177.703524 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2794 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3216 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2794 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4938 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112072000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16981500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 129053500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69344000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69344000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112072000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86325500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 198397500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112072000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86325500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 198397500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40111.667860 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40240.521327 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40269.454123 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40111.667860 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40263.759328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40111.667860 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40263.759328 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index a6f9e5430..10359186b 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -497,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index 9901dc40b..f5b2c31fd 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 06:08:28 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:45:24 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 55d9dc21f..221154573 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.029167 # Nu sim_ticks 29167093500 # Number of ticks simulated final_tick 29167093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 155660 # Simulator instruction rate (inst/s) -host_tick_rate 53933893 # Simulator tick rate (ticks/s) -host_mem_usage 212576 # Number of bytes of host memory used -host_seconds 540.79 # Real time elapsed on the host +host_inst_rate 198361 # Simulator instruction rate (inst/s) +host_op_rate 198361 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68729352 # Simulator tick rate (ticks/s) +host_mem_usage 214912 # Number of bytes of host memory used +host_seconds 424.38 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated +sim_ops 84179709 # Number of ops (including micro ops) simulated system.physmem.bytes_read 332416 # Number of bytes read from this memory system.physmem.bytes_inst_read 193856 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -271,6 +273,7 @@ system.cpu.iew.wb_rate 1.710877 # in system.cpu.iew.wb_fanout 0.725137 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions +system.cpu.commit.commitCommittedOps 91903055 # The number of committed instructions system.cpu.commit.commitSquashedInsts 40723267 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1895854 # The number of times a branch was mispredicted @@ -291,7 +294,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 52161479 # Number of insts commited each cycle -system.cpu.commit.count 91903055 # Number of instructions committed +system.cpu.commit.committedInsts 91903055 # Number of instructions committed +system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 26497301 # Number of memory references committed system.cpu.commit.loads 19996198 # Number of loads committed @@ -307,6 +311,7 @@ system.cpu.rob.rob_writes 271380444 # Th system.cpu.timesIdled 2277 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 93138 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated +system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated system.cpu.cpi 0.692972 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.692972 # CPI: Total CPI of All Threads @@ -324,26 +329,39 @@ system.cpu.icache.total_refs 18592194 # To system.cpu.icache.sampled_refs 10628 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1749.359616 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1593.002324 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.777833 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 18592194 # number of ReadReq hits -system.cpu.icache.demand_hits 18592194 # number of demand (read+write) hits -system.cpu.icache.overall_hits 18592194 # number of overall hits -system.cpu.icache.ReadReq_misses 11853 # number of ReadReq misses -system.cpu.icache.demand_misses 11853 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11853 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 188036500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 188036500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 188036500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 18604047 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 18604047 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 18604047 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000637 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000637 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000637 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 15864.042858 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 15864.042858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 15864.042858 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1593.002324 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.777833 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.777833 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 18592194 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 18592194 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 18592194 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 18592194 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 18592194 # number of overall hits +system.cpu.icache.overall_hits::total 18592194 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11853 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11853 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11853 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11853 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11853 # number of overall misses +system.cpu.icache.overall_misses::total 11853 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 188036500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 188036500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 188036500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 188036500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 188036500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 188036500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 18604047 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 18604047 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 18604047 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 18604047 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 18604047 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 18604047 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000637 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000637 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000637 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15864.042858 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15864.042858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15864.042858 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -352,27 +370,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1225 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1225 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1225 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 10628 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 10628 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 10628 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 124769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 124769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 124769000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000571 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000571 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000571 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11739.649981 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1225 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1225 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1225 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1225 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1225 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1225 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10628 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10628 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10628 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10628 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10628 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10628 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124769000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 124769000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124769000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 124769000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124769000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 124769000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11739.649981 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11739.649981 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11739.649981 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 159 # number of replacements system.cpu.dcache.tagsinuse 1462.507461 # Cycle average of tags in use @@ -380,38 +401,59 @@ system.cpu.dcache.total_refs 30399158 # To system.cpu.dcache.sampled_refs 2246 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13534.798753 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1462.507461 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.357057 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 23906051 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6493055 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 52 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 30399106 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 30399106 # number of overall hits -system.cpu.dcache.ReadReq_misses 938 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 8048 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 8986 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 8986 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 28163500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 289889000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 38000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 318052500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 318052500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 23906989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 30408092 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 30408092 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.018868 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000296 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000296 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 30025.053305 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 36020.004970 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35394.224349 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35394.224349 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1462.507461 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.357057 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.357057 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23906051 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23906051 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493055 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493055 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 30399106 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 30399106 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 30399106 # number of overall hits +system.cpu.dcache.overall_hits::total 30399106 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 938 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 938 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8048 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8048 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 8986 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8986 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8986 # number of overall misses +system.cpu.dcache.overall_misses::total 8986 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28163500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28163500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 289889000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 289889000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 38000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 38000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 318052500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 318052500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 318052500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 318052500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23906989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23906989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 30408092 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 30408092 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 30408092 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 30408092 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000039 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001238 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018868 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000296 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000296 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30025.053305 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36020.004970 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35394.224349 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35394.224349 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -420,36 +462,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 424 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6317 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6741 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6741 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1731 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2245 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2245 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 16469500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 61655000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 78124500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 78124500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.018868 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000074 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000074 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32041.828794 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35618.139804 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 108 # number of writebacks +system.cpu.dcache.writebacks::total 108 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 424 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6317 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6317 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6741 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6741 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6741 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6741 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 514 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 514 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2245 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2245 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2245 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2245 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16469500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16469500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61655000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61655000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78124500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78124500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78124500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78124500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018868 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32041.828794 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35618.139804 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34799.331849 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34799.331849 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2400.275766 # Cycle average of tags in use @@ -457,36 +509,75 @@ system.cpu.l2cache.total_refs 7666 # To system.cpu.l2cache.sampled_refs 3556 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.155793 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2382.642182 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.633584 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.072712 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000538 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 7655 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 108 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 25 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 382.154472 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000538 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.061050 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.011662 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.073251 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7599 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 56 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7655 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 108 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 108 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 25 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 25 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7599 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 75038500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 179036500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 10628 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 515 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 11143 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 108 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 108 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1731 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1731 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 10628 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2246 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 12874 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10628 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2246 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 12874 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.285002 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.891262 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985557 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.285002 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.963936 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.285002 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.963936 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34334.103665 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34410.675381 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34726.846424 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34334.103665 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34659.815242 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34334.103665 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34659.815242 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,30 +586,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3488 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5194 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5194 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 108490000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 53828000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 162318000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 162318000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313022 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985557 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.403449 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.403449 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.784404 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31552.168816 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31251.058914 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31251.058914 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3029 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 459 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3488 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1706 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1706 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3029 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5194 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3029 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5194 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 94144500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14345500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 108490000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53828000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53828000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 94144500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68173500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 162318000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 94144500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68173500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 162318000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.891262 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985557 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31081.049851 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31253.812636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31552.168816 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31081.049851 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31488.914550 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31081.049851 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31488.914550 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index c3b5c0104..452e0175b 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -64,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout index 887ca3f4e..b6a6db444 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 06:10:21 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:46:35 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index af93195e1..defa21ce1 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4191883 # Simulator instruction rate (inst/s) -host_tick_rate 2095941744 # Simulator tick rate (ticks/s) -host_mem_usage 202544 # Number of bytes of host memory used -host_seconds 21.92 # Real time elapsed on the host +host_inst_rate 5286635 # Simulator instruction rate (inst/s) +host_op_rate 5286630 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2643314521 # Simulator tick rate (ticks/s) +host_mem_usage 204308 # Number of bytes of host memory used +host_seconds 17.38 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated +sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read 475949877 # Number of bytes read from this memory system.physmem.bytes_inst_read 367612356 # Number of instructions bytes read from this memory system.physmem.bytes_written 30920974 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 389 # Nu system.cpu.numCycles 91903136 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 91903056 # Number of instructions executed +system.cpu.committedInsts 91903056 # Number of instructions committed +system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses system.cpu.num_func_calls 2059216 # number of times a function call or return occured diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 2fe44f969..16b0989b3 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout index 84097b1db..1373e7148 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 06:10:54 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:47:03 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index ba87aad33..244f3ca51 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.118740 # Nu sim_ticks 118740049000 # Number of ticks simulated final_tick 118740049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2095418 # Simulator instruction rate (inst/s) -host_tick_rate 2707308980 # Simulator tick rate (ticks/s) -host_mem_usage 211256 # Number of bytes of host memory used -host_seconds 43.86 # Real time elapsed on the host +host_inst_rate 2598987 # Simulator instruction rate (inst/s) +host_op_rate 2598985 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3357924345 # Simulator tick rate (ticks/s) +host_mem_usage 213168 # Number of bytes of host memory used +host_seconds 35.36 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated +sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read 304960 # Number of bytes read from this memory system.physmem.bytes_inst_read 167744 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -54,7 +56,8 @@ system.cpu.workload.num_syscalls 389 # Nu system.cpu.numCycles 237480098 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 91903056 # Number of instructions executed +system.cpu.committedInsts 91903056 # Number of instructions committed +system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses system.cpu.num_func_calls 2059216 # number of times a function call or return occured @@ -78,26 +81,39 @@ system.cpu.icache.total_refs 91894580 # To system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1418.037996 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.692401 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits -system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits -system.cpu.icache.overall_hits 91894580 # number of overall hits -system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses -system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses -system.cpu.icache.overall_misses 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1418.037996 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.692401 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.692401 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 91894580 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 91894580 # number of overall hits +system.cpu.icache.overall_hits::total 91894580 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8510 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8510 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8510 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses +system.cpu.icache.overall_misses::total 8510 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 229222000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 229222000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 229222000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 229222000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 229222000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 229222000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 91903090 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 91903090 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 91903090 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26935.605170 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 26935.605170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 26935.605170 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -106,26 +122,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use @@ -133,32 +147,49 @@ system.cpu.dcache.total_refs 26495078 # To system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1442.028823 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.352058 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits -system.cpu.dcache.demand_hits 26495078 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 26495078 # number of overall hits -system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses -system.cpu.dcache.demand_misses 2223 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 96796000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 121170000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 121170000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55375.286041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54507.422402 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1442.028823 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.352058 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.352058 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits +system.cpu.dcache.overall_hits::total 26495078 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses +system.cpu.dcache.overall_misses::total 2223 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24374000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24374000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 96796000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 96796000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 121170000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 121170000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 121170000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 121170000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51313.684211 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55375.286041 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54507.422402 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -167,30 +198,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 107 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 114501000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use @@ -198,36 +231,75 @@ system.cpu.l2cache.total_refs 5951 # To system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 1.914120 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2056.253411 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.795183 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.062752 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 5968 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 4765 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 4765 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 158236000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 89544000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 247780000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 247780000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.443958 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.443958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 17.795183 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1704.999565 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.253845 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.052032 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010719 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.063295 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5889 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5968 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5889 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits +system.cpu.l2cache.overall_hits::total 5968 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2621 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3043 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2621 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4765 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses +system.cpu.l2cache.overall_misses::total 4765 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 136292000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21944000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 158236000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 89544000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 89544000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 136292000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 111488000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 247780000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 136292000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 111488000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 247780000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 8510 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 8985 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 8510 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 10733 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 8510 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 10733 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.307991 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -236,30 +308,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 4765 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 4765 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 68880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 190600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 190600000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.443958 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.443958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2621 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3043 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2621 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4765 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104840000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 121720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68880000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68880000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85760000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 190600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104840000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85760000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 190600000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index ce56be1ef..eef0e971d 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -444,20 +437,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -492,20 +478,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -529,12 +508,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index 442ecd78f..d10088405 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,14 +1,10 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 10 2012 00:18:03 -gem5 started Feb 10 2012 00:18:20 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:37:09 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 83e315e2a..98dddaff0 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.105851 # Nu sim_ticks 105850842000 # Number of ticks simulated final_tick 105850842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46914 # Simulator instruction rate (inst/s) -host_tick_rate 26320721 # Simulator tick rate (ticks/s) -host_mem_usage 259812 # Number of bytes of host memory used -host_seconds 4021.58 # Real time elapsed on the host -sim_insts 188667627 # Number of instructions simulated +host_inst_rate 122767 # Simulator instruction rate (inst/s) +host_op_rate 134419 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75414821 # Simulator tick rate (ticks/s) +host_mem_usage 227032 # Number of bytes of host memory used +host_seconds 1403.58 # Real time elapsed on the host +sim_insts 172314144 # Number of instructions simulated +sim_ops 188667627 # Number of ops (including micro ops) simulated system.physmem.bytes_read 239936 # Number of bytes read from this memory system.physmem.bytes_inst_read 128320 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -280,7 +282,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.155893 # insts written-back per cycle system.cpu.iew.wb_fanout 0.599323 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 188682015 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 172328532 # The number of committed instructions +system.cpu.commit.commitCommittedOps 188682015 # The number of committed instructions system.cpu.commit.commitSquashedInsts 146244510 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1636018 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 9791900 # The number of times a branch was mispredicted @@ -301,7 +304,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 188552607 # Number of insts commited each cycle -system.cpu.commit.count 188682015 # Number of instructions committed +system.cpu.commit.committedInsts 172328532 # Number of instructions committed +system.cpu.commit.committedOps 188682015 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 42498565 # Number of memory references committed system.cpu.commit.loads 29851708 # Number of loads committed @@ -316,12 +320,13 @@ system.cpu.rob.rob_reads 519029825 # Th system.cpu.rob.rob_writes 693007050 # The number of ROB writes system.cpu.timesIdled 1719 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 58483 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 188667627 # Number of Instructions Simulated -system.cpu.committedInsts_total 188667627 # Number of Instructions Simulated -system.cpu.cpi 1.122088 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.122088 # CPI: Total CPI of All Threads -system.cpu.ipc 0.891196 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.891196 # IPC: Total IPC of All Threads +system.cpu.committedInsts 172314144 # Number of Instructions Simulated +system.cpu.committedOps 188667627 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172314144 # Number of Instructions Simulated +system.cpu.cpi 1.228580 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.228580 # CPI: Total CPI of All Threads +system.cpu.ipc 0.813948 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.813948 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 1111988877 # number of integer regfile reads system.cpu.int_regfile_writes 407368356 # number of integer regfile writes system.cpu.fp_regfile_reads 2928539 # number of floating regfile reads @@ -334,26 +339,39 @@ system.cpu.icache.total_refs 40615441 # To system.cpu.icache.sampled_refs 3640 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 11158.088187 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1329.301324 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.649073 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 40615441 # number of ReadReq hits -system.cpu.icache.demand_hits 40615441 # number of demand (read+write) hits -system.cpu.icache.overall_hits 40615441 # number of overall hits -system.cpu.icache.ReadReq_misses 4234 # number of ReadReq misses -system.cpu.icache.demand_misses 4234 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4234 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 101275500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 101275500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 101275500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 40619675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 40619675 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 40619675 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000104 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000104 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000104 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23919.579594 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23919.579594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23919.579594 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1329.301324 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.649073 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.649073 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 40615441 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 40615441 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 40615441 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 40615441 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 40615441 # number of overall hits +system.cpu.icache.overall_hits::total 40615441 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4234 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4234 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4234 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4234 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4234 # number of overall misses +system.cpu.icache.overall_misses::total 4234 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 101275500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 101275500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 101275500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 101275500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 101275500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 101275500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 40619675 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 40619675 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 40619675 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 40619675 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 40619675 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 40619675 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000104 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000104 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000104 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23919.579594 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23919.579594 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23919.579594 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -362,27 +380,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 594 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 594 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 594 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3640 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3640 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3640 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 74572500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 74572500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 74572500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000090 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000090 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000090 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20486.950549 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20486.950549 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20486.950549 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 594 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 594 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 594 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 594 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 594 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3640 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3640 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 3640 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3640 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 3640 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3640 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74572500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 74572500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74572500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 74572500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74572500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 74572500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20486.950549 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20486.950549 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20486.950549 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 53 # number of replacements system.cpu.dcache.tagsinuse 1403.723956 # Cycle average of tags in use @@ -390,40 +411,63 @@ system.cpu.dcache.total_refs 48643693 # To system.cpu.dcache.sampled_refs 1846 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 26350.862947 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1403.723956 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.342706 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 36234545 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 12356727 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 27791 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 24630 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 48591272 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 48591272 # number of overall hits -system.cpu.dcache.ReadReq_misses 1808 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 7560 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 9368 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9368 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 59529000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 237156500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 63500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 296685500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 296685500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 36236353 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 27793 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 24630 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 48600640 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 48600640 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000050 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000611 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000072 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000193 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000193 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 32925.331858 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 31369.907407 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 31750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 31670.100342 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 31670.100342 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1403.723956 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.342706 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.342706 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 36234545 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 36234545 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356727 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356727 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 27791 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 27791 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 24630 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 24630 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 48591272 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 48591272 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 48591272 # number of overall hits +system.cpu.dcache.overall_hits::total 48591272 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1808 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1808 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7560 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7560 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9368 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9368 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9368 # number of overall misses +system.cpu.dcache.overall_misses::total 9368 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59529000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59529000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 237156500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 237156500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 63500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 63500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 296685500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 296685500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 296685500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 296685500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 36236353 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 36236353 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 27793 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 27793 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 24630 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 24630 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 48600640 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 48600640 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 48600640 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 48600640 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000050 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000611 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000072 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000193 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000193 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32925.331858 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31369.907407 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31670.100342 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31670.100342 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -432,33 +476,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1053 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6469 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 7522 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 7522 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 755 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1091 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1846 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1846 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24116500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 38344000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 62460500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 62460500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000038 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000038 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31942.384106 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35145.737855 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33835.590466 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33835.590466 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 18 # number of writebacks +system.cpu.dcache.writebacks::total 18 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1053 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1053 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6469 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6469 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7522 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7522 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7522 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7522 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 755 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 755 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1091 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1091 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1846 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1846 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1846 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1846 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24116500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24116500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38344000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 38344000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62460500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 62460500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62460500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 62460500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000038 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000038 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31942.384106 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35145.737855 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33835.590466 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33835.590466 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 1923.480613 # Cycle average of tags in use @@ -466,36 +519,75 @@ system.cpu.l2cache.total_refs 1714 # To system.cpu.l2cache.sampled_refs 2676 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.640508 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1919.476269 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 4.004344 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058578 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000122 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1714 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 18 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 9 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1723 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1723 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2681 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1082 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 3763 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 3763 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 91922000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 37184000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 129106000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 129106000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 4395 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 18 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1091 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 5486 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 5486 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.610011 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.991751 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.685928 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.685928 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34286.460276 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34365.988909 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34309.327664 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34309.327664 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 4.004344 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1392.392495 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 527.083774 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000122 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.042492 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016085 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.058700 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 1633 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 81 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1714 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1633 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 90 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1723 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1633 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 90 # number of overall hits +system.cpu.l2cache.overall_hits::total 1723 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2007 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 674 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2681 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1082 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1082 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2007 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1756 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3763 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2007 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses +system.cpu.l2cache.overall_misses::total 3763 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68771500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23150500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 91922000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 37184000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 37184000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 68771500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 60334500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 129106000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 68771500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 60334500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 129106000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 3640 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 755 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 4395 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1091 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1091 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 3640 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1846 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 5486 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3640 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1846 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 5486 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.551374 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.892715 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991751 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.551374 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.951246 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.551374 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.951246 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34265.819631 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34347.922849 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34365.988909 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34265.819631 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34359.054670 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34265.819631 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34359.054670 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -504,31 +596,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 14 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2667 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1082 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 3749 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 3749 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 82895000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 33590000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 116485000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 116485000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.606826 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991751 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.683376 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.683376 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.739783 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31044.362292 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31070.952254 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31070.952254 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2005 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 662 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2667 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1082 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1082 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2005 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1744 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3749 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2005 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1744 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3749 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 62251500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20643500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 82895000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33590000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33590000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 62251500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54233500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 116485000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 62251500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54233500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 116485000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876821 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991751 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.944745 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.944745 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31048.129676 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31183.534743 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.362292 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31048.129676 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31097.190367 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31048.129676 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31097.190367 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini index 01def30a3..8e458b793 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,32 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=ArmInterrupts [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +119,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout index f2a9f0661..36b361cbc 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 09:50:48 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:37:27 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sav -Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sv2 +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 079a70f11..5d6608220 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.103107 # Nu sim_ticks 103106771000 # Number of ticks simulated final_tick 103106771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3006793 # Simulator instruction rate (inst/s) -host_tick_rate 1643182108 # Simulator tick rate (ticks/s) -host_mem_usage 213456 # Number of bytes of host memory used -host_seconds 62.75 # Real time elapsed on the host -sim_insts 188670900 # Number of instructions simulated +host_inst_rate 3118510 # Simulator instruction rate (inst/s) +host_op_rate 3414466 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1865971013 # Simulator tick rate (ticks/s) +host_mem_usage 216012 # Number of bytes of host memory used +host_seconds 55.26 # Real time elapsed on the host +sim_insts 172317417 # Number of instructions simulated +sim_ops 188670900 # Number of ops (including micro ops) simulated system.physmem.bytes_read 869973902 # Number of bytes read from this memory system.physmem.bytes_inst_read 759440240 # Number of instructions bytes read from this memory system.physmem.bytes_written 45252940 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 400 # Nu system.cpu.numCycles 206213543 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 188670900 # Number of instructions executed +system.cpu.committedInsts 172317417 # Number of instructions committed +system.cpu.committedOps 188670900 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_func_calls 3504894 # number of times a function call or return occured diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini index 3f54c6512..f90360da8 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +106,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +120,21 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=ArmInterrupts + [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +147,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +169,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +177,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout index b21763742..322e5b2f2 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 09:52:01 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:38:33 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav -Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2 +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index d861ddab1..f86e3b057 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.232077 # Nu sim_ticks 232077154000 # Number of ticks simulated final_tick 232077154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1497030 # Simulator instruction rate (inst/s) -host_tick_rate 1846187485 # Simulator tick rate (ticks/s) -host_mem_usage 222460 # Number of bytes of host memory used -host_seconds 125.71 # Real time elapsed on the host -sim_insts 188185929 # Number of instructions simulated +host_inst_rate 1867609 # Simulator instruction rate (inst/s) +host_op_rate 2045232 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2522247357 # Simulator tick rate (ticks/s) +host_mem_usage 224952 # Number of bytes of host memory used +host_seconds 92.01 # Real time elapsed on the host +sim_insts 171842491 # Number of instructions simulated +sim_ops 188185929 # Number of ops (including micro ops) simulated system.physmem.bytes_read 220992 # Number of bytes read from this memory system.physmem.bytes_inst_read 110656 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -64,7 +66,8 @@ system.cpu.workload.num_syscalls 400 # Nu system.cpu.numCycles 464154308 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 188185929 # Number of instructions executed +system.cpu.committedInsts 171842491 # Number of instructions committed +system.cpu.committedOps 188185929 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_func_calls 3504894 # number of times a function call or return occured @@ -88,26 +91,39 @@ system.cpu.icache.total_refs 189857010 # To system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 62227.797443 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1147.981155 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.560538 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 189857010 # number of ReadReq hits -system.cpu.icache.demand_hits 189857010 # number of demand (read+write) hits -system.cpu.icache.overall_hits 189857010 # number of overall hits -system.cpu.icache.ReadReq_misses 3051 # number of ReadReq misses -system.cpu.icache.demand_misses 3051 # number of demand (read+write) misses -system.cpu.icache.overall_misses 3051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 115332000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 115332000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 115332000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 189860061 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 189860061 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 189860061 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000016 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 37801.376598 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 37801.376598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 37801.376598 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1147.981155 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.560538 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.560538 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 189857010 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 189857010 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 189857010 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 189857010 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 189857010 # number of overall hits +system.cpu.icache.overall_hits::total 189857010 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses +system.cpu.icache.overall_misses::total 3051 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 115332000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 115332000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 115332000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 115332000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 115332000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 115332000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 189860061 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 189860061 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 189860061 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 189860061 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 189860061 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 189860061 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37801.376598 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,26 +132,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3051 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3051 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3051 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 106179000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 106179000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 106179000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000016 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000016 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.376598 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106179000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 106179000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106179000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 106179000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106179000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 106179000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34801.376598 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 40 # number of replacements system.cpu.dcache.tagsinuse 1363.604315 # Cycle average of tags in use @@ -143,36 +157,57 @@ system.cpu.dcache.total_refs 42007359 # To system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 23480.916154 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1363.604315 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.332911 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 29599358 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 12363187 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 22407 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 41962545 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 41962545 # number of overall hits -system.cpu.dcache.ReadReq_misses 689 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1100 # number of WriteReq misses -system.cpu.dcache.demand_misses 1789 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 36190000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 61264000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 97454000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 97454000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 29600047 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 41964334 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 41964334 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000023 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000043 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 52525.399129 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55694.545455 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54474.007826 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54474.007826 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1363.604315 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.332911 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.332911 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 29599358 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 29599358 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41962545 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41962545 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41962545 # number of overall hits +system.cpu.dcache.overall_hits::total 41962545 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 689 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 689 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1789 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1789 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses +system.cpu.dcache.overall_misses::total 1789 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36190000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36190000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 61264000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 61264000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 97454000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 97454000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 97454000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 97454000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 29600047 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 29600047 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 41964334 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41964334 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41964334 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41964334 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52525.399129 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55694.545455 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54474.007826 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54474.007826 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -181,30 +216,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 16 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 689 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1100 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1789 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1789 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 34123000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 57964000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 92087000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 92087000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000043 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000043 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49525.399129 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52694.545455 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51474.007826 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51474.007826 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 689 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 689 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1789 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1789 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34123000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34123000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57964000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 57964000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 92087000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 1675.648030 # Cycle average of tags in use @@ -212,36 +249,75 @@ system.cpu.l2cache.total_refs 1379 # To system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.582102 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1672.609981 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3.038048 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.051044 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000093 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1379 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 16 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1387 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1387 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2361 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1092 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 3453 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 3453 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 122772000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 56784000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 179556000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 179556000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 3740 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 16 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1100 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 4840 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 4840 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.631283 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.992727 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.713430 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.713430 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 3.038048 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1169.027734 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 503.582248 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.051137 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1322 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 65 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1387 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1322 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 65 # number of overall hits +system.cpu.l2cache.overall_hits::total 1387 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1729 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2361 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1092 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1092 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1729 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1724 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3453 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses +system.cpu.l2cache.overall_misses::total 3453 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 89908000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32864000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 122772000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56784000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 56784000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 89908000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 89648000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 179556000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 89908000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 89648000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 179556000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 3051 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 689 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 3051 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1789 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 4840 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3051 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1789 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 4840 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.917271 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992727 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,30 +326,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2361 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1092 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 3453 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 3453 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 94440000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 43680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 138120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 138120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.631283 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992727 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.713430 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.713430 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1729 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 632 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2361 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94440000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43680000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43680000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 138120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68960000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 138120000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 5551fc718..bf42eae33 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=SparcTLB size=64 +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -64,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic +cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout index 5a1dc45d3..288eec929 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 06:25:10 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 14:01:49 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic -Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/smred.sav -Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index fabf573dd..acb9c3a66 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.096723 # Nu sim_ticks 96722951500 # Number of ticks simulated final_tick 96722951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3381365 # Simulator instruction rate (inst/s) -host_tick_rate 1690691780 # Simulator tick rate (ticks/s) -host_mem_usage 210080 # Number of bytes of host memory used -host_seconds 57.21 # Real time elapsed on the host -sim_insts 193444769 # Number of instructions simulated +host_inst_rate 4190258 # Simulator instruction rate (inst/s) +host_op_rate 4190262 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2095142285 # Simulator tick rate (ticks/s) +host_mem_usage 207744 # Number of bytes of host memory used +host_seconds 46.17 # Real time elapsed on the host +sim_insts 193444531 # Number of instructions simulated +sim_ops 193444769 # Number of ops (including micro ops) simulated system.physmem.bytes_read 997245606 # Number of bytes read from this memory system.physmem.bytes_inst_read 773782192 # Number of instructions bytes read from this memory system.physmem.bytes_written 72065412 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 401 # Nu system.cpu.numCycles 193445904 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 193444769 # Number of instructions executed +system.cpu.committedInsts 193444531 # Number of instructions committed +system.cpu.committedOps 193444769 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses system.cpu.num_func_calls 1957920 # number of times a function call or return occured diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini index 2d0b36d34..4355111bc 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing +cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout index e7f89f9a0..cb4fa4440 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 06:26:18 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 14:02:21 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sav -Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sv2 +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 16bfeed42..fba3d7989 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.270577 # Nu sim_ticks 270576960000 # Number of ticks simulated final_tick 270576960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1675606 # Simulator instruction rate (inst/s) -host_tick_rate 2343719954 # Simulator tick rate (ticks/s) -host_mem_usage 218792 # Number of bytes of host memory used -host_seconds 115.45 # Real time elapsed on the host -sim_insts 193444769 # Number of instructions simulated +host_inst_rate 2083715 # Simulator instruction rate (inst/s) +host_op_rate 2083717 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2914556895 # Simulator tick rate (ticks/s) +host_mem_usage 216616 # Number of bytes of host memory used +host_seconds 92.84 # Real time elapsed on the host +sim_insts 193444531 # Number of instructions simulated +sim_ops 193444769 # Number of ops (including micro ops) simulated system.physmem.bytes_read 331072 # Number of bytes read from this memory system.physmem.bytes_inst_read 230208 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -22,7 +24,8 @@ system.cpu.workload.num_syscalls 401 # Nu system.cpu.numCycles 541153920 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 193444769 # Number of instructions executed +system.cpu.committedInsts 193444531 # Number of instructions committed +system.cpu.committedOps 193444769 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses system.cpu.num_func_calls 1957920 # number of times a function call or return occured @@ -46,26 +49,39 @@ system.cpu.icache.total_refs 193433261 # To system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 15741.639079 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1591.571713 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.777135 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 193433261 # number of ReadReq hits -system.cpu.icache.demand_hits 193433261 # number of demand (read+write) hits -system.cpu.icache.overall_hits 193433261 # number of overall hits -system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses -system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses -system.cpu.icache.overall_misses 12288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 193445549 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 193445549 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1591.571713 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.777135 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.777135 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 193433261 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 193433261 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 193433261 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 193433261 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 193433261 # number of overall hits +system.cpu.icache.overall_hits::total 193433261 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses +system.cpu.icache.overall_misses::total 12288 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 323106000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 323106000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 323106000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 323106000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 323106000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 323106000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 193445549 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 193445549 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 193445549 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 193445549 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 193445549 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 193445549 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26294.433594 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -74,26 +90,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 12288 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 12288 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 286242000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 286242000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 286242000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 286242000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 286242000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 286242000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 286242000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 286242000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 286242000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23294.433594 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2 # number of replacements system.cpu.dcache.tagsinuse 1237.197455 # Cycle average of tags in use @@ -101,38 +115,59 @@ system.cpu.dcache.total_refs 76732338 # To system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1237.197455 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.302050 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 57734571 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 18975362 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits -system.cpu.dcache.demand_hits 76709933 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 76709933 # number of overall hits -system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1077 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses -system.cpu.dcache.demand_misses 1575 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1575 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 27888000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 60312000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency 56000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency 88200000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 88200000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1237.197455 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.302050 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.302050 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 57734571 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 57734571 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 76709933 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 76709933 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 76709933 # number of overall hits +system.cpu.dcache.overall_hits::total 76709933 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses +system.cpu.dcache.overall_misses::total 1575 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27888000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27888000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 60312000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 60312000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 56000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 56000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 88200000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 88200000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 88200000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 88200000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 57735069 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 57735069 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 76711508 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 76711508 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 76711508 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 76711508 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -141,34 +176,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 2 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1077 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1575 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1575 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 26394000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 57081000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency 53000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 83475000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 83475000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 2 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26394000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57081000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 57081000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 53000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83475000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 83475000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83475000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 83475000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2678.327135 # Cycle average of tags in use @@ -176,35 +215,70 @@ system.cpu.l2cache.total_refs 8691 # To system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.121308 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2678.326682 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 0.000454 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.081736 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 8691 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits -system.cpu.l2cache.demand_hits 8691 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 8691 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4095 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1078 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5173 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5173 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 212940000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 56056000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 268996000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 268996000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 12786 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1078 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 13864 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.320272 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.373125 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.373125 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 0.000454 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2275.271466 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 403.055215 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.081736 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2 # number of Writeback hits +system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits +system.cpu.l2cache.overall_hits::total 8691 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3597 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 498 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4095 # 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number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -213,30 +287,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1078 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5173 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 163800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 43120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 206920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 206920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.373125 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.373125 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3597 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4095 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63040000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 206920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63040000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 206920000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 9f72e3b54..82a282d96 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -442,20 +435,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -494,20 +480,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -531,12 +510,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing +cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 0b6a80ec2..99b3e7f21 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,14 +1,10 @@ -Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 9 2012 12:45:55 -gem5 started Feb 9 2012 12:46:40 -gem5 executing on ribera.cs.wisc.edu -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 15:02:46 +gem5 executing on zizzer +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 2a68affc2..0aeabdea4 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.096266 # Nu sim_ticks 96266258000 # Number of ticks simulated final_tick 96266258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60515 # Simulator instruction rate (inst/s) -host_tick_rate 26316743 # Simulator tick rate (ticks/s) -host_mem_usage 262352 # Number of bytes of host memory used -host_seconds 3657.99 # Real time elapsed on the host -sim_insts 221363017 # Number of instructions simulated +host_inst_rate 89516 # Simulator instruction rate (inst/s) +host_op_rate 150037 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65247901 # Simulator tick rate (ticks/s) +host_mem_usage 229524 # Number of bytes of host memory used +host_seconds 1475.39 # Real time elapsed on the host +sim_insts 132071227 # Number of instructions simulated +sim_ops 221363017 # Number of ops (including micro ops) simulated system.physmem.bytes_read 339712 # Number of bytes read from this memory system.physmem.bytes_inst_read 214912 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -235,7 +237,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.457634 # insts written-back per cycle system.cpu.iew.wb_fanout 0.601730 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions +system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions system.cpu.commit.commitSquashedInsts 174222633 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 2892920 # The number of times a branch was mispredicted @@ -256,7 +259,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 168869292 # Number of insts commited each cycle -system.cpu.commit.count 221363017 # Number of instructions committed +system.cpu.commit.committedInsts 132071227 # Number of instructions committed +system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 77165306 # Number of memory references committed system.cpu.commit.loads 56649590 # Number of loads committed @@ -271,12 +275,13 @@ system.cpu.rob.rob_reads 560089335 # Th system.cpu.rob.rob_writes 814800236 # The number of ROB writes system.cpu.timesIdled 1747 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 80351 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 221363017 # Number of Instructions Simulated -system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 0.869759 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.869759 # CPI: Total CPI of All Threads -system.cpu.ipc 1.149744 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.149744 # IPC: Total IPC of All Threads +system.cpu.committedInsts 132071227 # Number of Instructions Simulated +system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated +system.cpu.cpi 1.457793 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.457793 # CPI: Total CPI of All Threads +system.cpu.ipc 0.685968 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.685968 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 530367480 # number of integer regfile reads system.cpu.int_regfile_writes 288604591 # number of integer regfile writes system.cpu.fp_regfile_reads 3608788 # number of floating regfile reads @@ -289,26 +294,39 @@ system.cpu.icache.total_refs 28751182 # To system.cpu.icache.sampled_refs 6167 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4662.101832 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1597.649860 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.780102 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 28751182 # number of ReadReq hits -system.cpu.icache.demand_hits 28751182 # number of demand (read+write) hits -system.cpu.icache.overall_hits 28751182 # number of overall hits -system.cpu.icache.ReadReq_misses 7479 # number of ReadReq misses -system.cpu.icache.demand_misses 7479 # number of demand (read+write) misses -system.cpu.icache.overall_misses 7479 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 173725000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 173725000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 173725000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 28758661 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 28758661 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 28758661 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000260 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000260 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000260 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23228.372777 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23228.372777 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23228.372777 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1597.649860 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.780102 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.780102 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 28751182 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 28751182 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 28751182 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 28751182 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 28751182 # number of overall hits +system.cpu.icache.overall_hits::total 28751182 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 7479 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 7479 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 7479 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 7479 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 7479 # number of overall misses +system.cpu.icache.overall_misses::total 7479 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 173725000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 173725000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 173725000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 173725000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 173725000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 173725000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 28758661 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 28758661 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 28758661 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 28758661 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 28758661 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 28758661 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000260 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000260 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000260 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23228.372777 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -317,27 +335,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1119 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1119 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1119 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 6360 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 6360 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 6360 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 125233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 125233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 125233500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000221 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000221 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000221 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 19690.801887 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 19690.801887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 19690.801887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1119 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1119 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1119 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1119 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1119 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1119 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6360 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6360 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6360 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6360 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6360 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6360 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125233500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 125233500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125233500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 125233500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125233500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 125233500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19690.801887 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 56 # number of replacements system.cpu.dcache.tagsinuse 1415.486536 # Cycle average of tags in use @@ -345,32 +366,49 @@ system.cpu.dcache.total_refs 72938173 # To system.cpu.dcache.sampled_refs 1987 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 36707.686462 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1415.486536 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.345578 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 52423955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20513973 # number of WriteReq hits -system.cpu.dcache.demand_hits 72937928 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 72937928 # number of overall hits -system.cpu.dcache.ReadReq_misses 771 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1757 # number of WriteReq misses -system.cpu.dcache.demand_misses 2528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 24605500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 66582500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 91188000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 91188000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 52424726 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 72940456 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 72940456 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000086 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000035 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000035 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 31913.748379 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 37895.560615 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 36071.202532 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 36071.202532 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1415.486536 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.345578 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.345578 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 52423955 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 52423955 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513973 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513973 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 72937928 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 72937928 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 72937928 # number of overall hits +system.cpu.dcache.overall_hits::total 72937928 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 771 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 771 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1757 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1757 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2528 # number of overall misses +system.cpu.dcache.overall_misses::total 2528 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24605500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24605500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 66582500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 66582500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91188000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91188000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91188000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91188000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 52424726 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 52424726 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 72940456 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 72940456 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 72940456 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 72940456 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000015 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000086 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000035 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000035 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31913.748379 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37895.560615 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36071.202532 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36071.202532 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,32 +417,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 344 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 346 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 346 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 427 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1755 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2182 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2182 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14039500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 61244500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 75284000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 75284000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000086 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000030 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000030 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32879.391101 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34897.150997 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34502.291476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34502.291476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 13 # number of writebacks +system.cpu.dcache.writebacks::total 13 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 344 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 344 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 346 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 346 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 346 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 346 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 427 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1755 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1755 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2182 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2182 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2182 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2182 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14039500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14039500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61244500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61244500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 75284000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 75284000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 75284000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 75284000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000086 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000030 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000030 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32879.391101 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34897.150997 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34502.291476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34502.291476 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2496.824684 # Cycle average of tags in use @@ -412,39 +458,80 @@ system.cpu.l2cache.total_refs 2842 # To system.cpu.l2cache.sampled_refs 3755 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.756858 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2494.880189 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.944495 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.076138 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000059 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2840 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 13 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2848 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2848 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3753 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 193 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 1555 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5308 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5308 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 128533500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 53066500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 181600000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 181600000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 6593 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 13 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 193 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1563 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8156 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8156 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.569240 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.994882 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.650809 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.650809 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34248.201439 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34126.366559 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34212.509420 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34212.509420 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 1.944495 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2209.976363 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 284.903826 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000059 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.067443 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.008695 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.076197 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2809 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 31 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2840 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2809 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2848 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2809 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits +system.cpu.l2cache.overall_hits::total 2848 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3358 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 395 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3753 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 193 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 193 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1555 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1555 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3358 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1950 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5308 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3358 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1950 # number of overall misses +system.cpu.l2cache.overall_misses::total 5308 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 115037500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13496000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 128533500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 53066500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 53066500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 115037500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 66562500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 181600000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 115037500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 66562500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 181600000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6167 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 426 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 6593 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 193 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 193 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1563 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1563 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6167 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1989 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8156 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6167 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1989 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8156 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.544511 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.927230 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994882 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.544511 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.980392 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.544511 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.980392 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34257.742704 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34167.088608 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34126.366559 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34257.742704 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.615385 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34257.742704 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.615385 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,34 +540,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3753 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 193 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1555 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5308 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5308 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 116413500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 5983000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 48232500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 164646000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 164646000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.569240 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994882 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.650809 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.650809 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.784972 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31017.684887 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31018.462698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31018.462698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3358 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 395 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3753 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 193 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 193 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1555 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1555 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3358 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1950 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5308 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3358 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1950 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5308 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104175500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12238000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116413500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5983000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5983000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48232500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48232500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104175500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60470500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 164646000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104175500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60470500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 164646000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927230 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.079214 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30982.278481 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31017.684887 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini index 4d9868de9..1355f971a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,34 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[7] +pio=system.membus.port[6] [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +97,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic +cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +121,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout index 3217ab200..d61c2b9aa 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 08:24:02 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 15:27:33 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2 +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 39967f660..0e7ef2e19 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.131393 # Nu sim_ticks 131393100000 # Number of ticks simulated final_tick 131393100000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1953897 # Simulator instruction rate (inst/s) -host_tick_rate 1159762651 # Simulator tick rate (ticks/s) -host_mem_usage 211876 # Number of bytes of host memory used -host_seconds 113.29 # Real time elapsed on the host -sim_insts 221363018 # Number of instructions simulated +host_inst_rate 1741959 # Simulator instruction rate (inst/s) +host_op_rate 2919677 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1733014386 # Simulator tick rate (ticks/s) +host_mem_usage 217356 # Number of bytes of host memory used +host_seconds 75.82 # Real time elapsed on the host +sim_insts 132071228 # Number of instructions simulated +sim_ops 221363018 # Number of ops (including micro ops) simulated system.physmem.bytes_read 1698379042 # Number of bytes read from this memory system.physmem.bytes_inst_read 1387955288 # Number of instructions bytes read from this memory system.physmem.bytes_written 99822189 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 400 # Nu system.cpu.numCycles 262786201 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 221363018 # Number of instructions executed +system.cpu.committedInsts 132071228 # Number of instructions committed +system.cpu.committedOps 221363018 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini index d7a510398..62a1aa7b0 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +104,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +118,25 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[4] +pio=system.membus.port[3] + [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +149,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +171,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing egid=100 env= errout=cerr @@ -191,7 +203,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index a3170a407..fff65e67f 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 08:26:06 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 15:28:59 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2 +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 1c9d2c1e6..6e3725588 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.250961 # Nu sim_ticks 250960631000 # Number of ticks simulated final_tick 250960631000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1263573 # Simulator instruction rate (inst/s) -host_tick_rate 1432520595 # Simulator tick rate (ticks/s) -host_mem_usage 220856 # Number of bytes of host memory used -host_seconds 175.19 # Real time elapsed on the host -sim_insts 221363018 # Number of instructions simulated +host_inst_rate 1043901 # Simulator instruction rate (inst/s) +host_op_rate 1749670 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1983612036 # Simulator tick rate (ticks/s) +host_mem_usage 226268 # Number of bytes of host memory used +host_seconds 126.52 # Real time elapsed on the host +sim_insts 132071228 # Number of instructions simulated +sim_ops 221363018 # Number of ops (including micro ops) simulated system.physmem.bytes_read 303040 # Number of bytes read from this memory system.physmem.bytes_inst_read 181760 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -22,7 +24,8 @@ system.cpu.workload.num_syscalls 400 # Nu system.cpu.numCycles 501921262 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 221363018 # Number of instructions executed +system.cpu.committedInsts 132071228 # Number of instructions committed +system.cpu.committedOps 221363018 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured @@ -46,26 +49,39 @@ system.cpu.icache.total_refs 173489718 # To system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.710590 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 173489718 # number of ReadReq hits -system.cpu.icache.demand_hits 173489718 # number of demand (read+write) hits -system.cpu.icache.overall_hits 173489718 # number of overall hits -system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses -system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 185041500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 185041500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 173494412 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 173494412 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 39420.856412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1455.289108 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.710590 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.710590 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 173489718 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173489718 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173489718 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173489718 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173489718 # number of overall hits +system.cpu.icache.overall_hits::total 173489718 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses +system.cpu.icache.overall_misses::total 4694 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 185041500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 185041500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 185041500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 185041500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 185041500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 185041500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 173494412 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 173494412 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 173494412 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 173494412 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 173494412 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 173494412 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39420.856412 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39420.856412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39420.856412 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -74,26 +90,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 4694 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 4694 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 170928000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 170928000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 170928000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170928000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 170928000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170928000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 170928000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170928000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 170928000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.145718 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.145718 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.145718 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 41 # number of replacements system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use @@ -101,32 +115,49 @@ system.cpu.dcache.total_refs 77195833 # To system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.332874 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 56681681 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20514152 # number of WriteReq hits -system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 77195833 # number of overall hits -system.cpu.dcache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses -system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1905 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 18020000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 88242000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 106262000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 106262000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000077 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 55780.577428 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1363.451495 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.332874 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.332874 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 56681681 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 56681681 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514152 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514152 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 77195833 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 77195833 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 77195833 # number of overall hits +system.cpu.dcache.overall_hits::total 77195833 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses +system.cpu.dcache.overall_misses::total 1905 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18020000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18020000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 88242000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 88242000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106262000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106262000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106262000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106262000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 56682008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 56682008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 77197738 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77197738 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77197738 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77197738 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55107.033639 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55920.152091 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55780.577428 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55780.577428 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -135,30 +166,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 7 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 327 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 17038500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 83508000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 100546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 100546500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 7 # number of writebacks +system.cpu.dcache.writebacks::total 7 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use @@ -166,36 +199,75 @@ system.cpu.l2cache.total_refs 1861 # To system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.588180 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2058.146434 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 0.021756 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.062810 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1861 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 7 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1864 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1864 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3160 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 4735 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 4735 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 164335500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 246235500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 246235500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 7 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 6599 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.629357 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.998099 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.717533 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.717533 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52003.273495 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52003.273495 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 0.021756 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1829.968899 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 228.177535 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055846 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.062810 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 7 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 7 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits +system.cpu.l2cache.overall_hits::total 1864 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2840 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 320 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3160 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses +system.cpu.l2cache.overall_misses::total 4735 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 147694000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16641500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 164335500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 81900000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 81900000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 147694000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 98541500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 246235500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 147694000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 98541500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 246235500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5021 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 7 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 7 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.978593 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52004.929577 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52004.687500 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -204,30 +276,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3160 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 4735 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 4735 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 126400000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 189400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 189400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629357 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.998099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.717533 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.717533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2840 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 320 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3160 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 113600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 126400000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 113600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 189400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 113600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 189400000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |