diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
| commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
| tree | 63ce098bc690eb5b58b3297b747794d623cface4 /tests/long/se/70.twolf | |
| parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
| download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz | |
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/long/se/70.twolf')
24 files changed, 1727 insertions, 1738 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 0cab3c39f..4aef8f4de 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -191,7 +191,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout index c65e040d8..926d51412 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:52:53 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:37:18 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index a7912f8e0..60e11bdef 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.042005 # Nu sim_ticks 42005374000 # Number of ticks simulated final_tick 42005374000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106867 # Simulator instruction rate (inst/s) -host_op_rate 106867 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48844875 # Simulator tick rate (ticks/s) -host_mem_usage 218932 # Number of bytes of host memory used -host_seconds 859.98 # Real time elapsed on the host +host_inst_rate 160903 # Simulator instruction rate (inst/s) +host_op_rate 160903 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73542430 # Simulator tick rate (ticks/s) +host_mem_usage 222752 # Number of bytes of host memory used +host_seconds 571.17 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -322,9 +322,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 52276.878093 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2189.730470 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7264 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 7269 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.213285 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.214808 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 17.847253 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 1820.879596 # Average occupied blocks per requestor diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index f02146b21..d1830cc83 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -489,7 +489,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index 11770df5a..157ee9690 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:06:35 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:41:57 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +21,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 23638033500 because target called exit() +122 123 124 Exiting @ tick 23635060000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 5f8b8cbb4..42e01362d 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023638 # Number of seconds simulated -sim_ticks 23638033500 # Number of ticks simulated -final_tick 23638033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023635 # Number of seconds simulated +sim_ticks 23635060000 # Number of ticks simulated +final_tick 23635060000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160213 # Simulator instruction rate (inst/s) -host_op_rate 160213 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44988546 # Simulator tick rate (ticks/s) -host_mem_usage 220112 # Number of bytes of host memory used -host_seconds 525.42 # Real time elapsed on the host +host_inst_rate 242450 # Simulator instruction rate (inst/s) +host_op_rate 242450 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68072464 # Simulator tick rate (ticks/s) +host_mem_usage 223772 # Number of bytes of host memory used +host_seconds 347.20 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 197952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138112 # Number of bytes read from this memory -system.physmem.bytes_read::total 336064 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 197952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 197952 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3093 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2158 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5251 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8374301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5842787 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14217088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8374301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8374301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8374301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5842787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14217088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 197248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138496 # Number of bytes read from this memory +system.physmem.bytes_read::total 335744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 197248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 197248 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3082 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2164 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5246 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8345568 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5859769 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14205337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8345568 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8345568 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8345568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5859769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14205337 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23223377 # DTB read hits -system.cpu.dtb.read_misses 198479 # DTB read misses +system.cpu.dtb.read_hits 23228346 # DTB read hits +system.cpu.dtb.read_misses 200425 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 23421856 # DTB read accesses -system.cpu.dtb.write_hits 7079825 # DTB write hits -system.cpu.dtb.write_misses 1403 # DTB write misses +system.cpu.dtb.read_accesses 23428771 # DTB read accesses +system.cpu.dtb.write_hits 7078031 # DTB write hits +system.cpu.dtb.write_misses 1393 # DTB write misses system.cpu.dtb.write_acv 5 # DTB write access violations -system.cpu.dtb.write_accesses 7081228 # DTB write accesses -system.cpu.dtb.data_hits 30303202 # DTB hits -system.cpu.dtb.data_misses 199882 # DTB misses +system.cpu.dtb.write_accesses 7079424 # DTB write accesses +system.cpu.dtb.data_hits 30306377 # DTB hits +system.cpu.dtb.data_misses 201818 # DTB misses system.cpu.dtb.data_acv 5 # DTB access violations -system.cpu.dtb.data_accesses 30503084 # DTB accesses -system.cpu.itb.fetch_hits 14943347 # ITB hits -system.cpu.itb.fetch_misses 91 # ITB misses +system.cpu.dtb.data_accesses 30508195 # DTB accesses +system.cpu.itb.fetch_hits 14951144 # ITB hits +system.cpu.itb.fetch_misses 107 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14943438 # ITB accesses +system.cpu.itb.fetch_accesses 14951251 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,146 +60,146 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 47276068 # number of cpu cycles simulated +system.cpu.numCycles 47270121 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15033034 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10893927 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 965097 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 8612659 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7067377 # Number of BTB hits +system.cpu.BPredUnit.lookups 15030146 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10897396 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 964237 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 8689796 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7074632 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1490279 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6040 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15621230 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 128217007 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15033034 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8557656 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22378884 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4633381 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5548401 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1488592 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 3325 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15628273 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 128247685 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15030146 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8563224 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22387448 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4637135 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5522059 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1854 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14943347 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 336798 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47185446 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.717300 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.373013 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 1901 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14951144 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 336879 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47178795 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.718333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.372984 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24806562 52.57% 52.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2389979 5.07% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1207538 2.56% 60.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1775063 3.76% 63.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2802024 5.94% 69.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1169800 2.48% 72.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1228019 2.60% 74.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 790135 1.67% 76.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11016326 23.35% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24791347 52.55% 52.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2391230 5.07% 57.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1207932 2.56% 60.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1776893 3.77% 63.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2805490 5.95% 69.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1170846 2.48% 72.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1228782 2.60% 74.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 789170 1.67% 76.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11017105 23.35% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47185446 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317984 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.712091 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17463925 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4249040 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20759249 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1090184 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3623048 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2545357 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12255 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 125130253 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31826 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3623048 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18629909 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 965094 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8920 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20661182 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3297293 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 122152175 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 401388 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2422623 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89685518 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 158620062 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 148881837 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9738225 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 47178795 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317963 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.713081 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17466562 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4227162 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20770000 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1087804 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3627267 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2544055 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12184 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 125158453 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31894 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3627267 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18628524 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 960250 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8367 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20673426 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3280961 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 122187472 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 401237 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2407508 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89717314 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 158683253 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 148939266 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9743987 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 21258157 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1427 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1434 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8739521 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25557847 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8301356 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2609711 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 904973 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 106143007 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2358 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96975947 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 189226 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21491456 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16142477 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1969 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47185446 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.055209 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.876136 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 21289953 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1139 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1148 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8701053 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25559054 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8299979 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2600508 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 916071 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 106169681 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2314 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96996119 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 187372 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21529768 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16156839 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1925 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47178795 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.055926 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.875880 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12454883 26.40% 26.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9420722 19.97% 46.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8458741 17.93% 64.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6315379 13.38% 77.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4948925 10.49% 88.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2846998 6.03% 94.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1728154 3.66% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 801160 1.70% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 210484 0.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12439775 26.37% 26.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9421207 19.97% 46.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8463269 17.94% 64.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6318044 13.39% 77.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4948438 10.49% 88.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2848262 6.04% 94.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1729160 3.67% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 800900 1.70% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 209740 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47185446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47178795 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 186828 11.91% 11.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 238 0.02% 11.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7150 0.46% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5464 0.35% 12.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 842994 53.75% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 446294 28.45% 94.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 79499 5.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 186062 11.86% 11.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 228 0.01% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7118 0.45% 12.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5890 0.38% 12.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 842932 53.71% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 447788 28.53% 94.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79372 5.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58979048 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 480591 0.50% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2800978 2.89% 64.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115548 0.12% 64.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2385848 2.46% 66.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311419 0.32% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 759609 0.78% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58995521 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 480822 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2802067 2.89% 64.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115555 0.12% 64.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2385721 2.46% 66.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311403 0.32% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759596 0.78% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.89% # Type of FU issued @@ -221,86 +221,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23970757 24.72% 92.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7171823 7.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23975443 24.72% 92.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7169665 7.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96975947 # Type of FU issued -system.cpu.iq.rate 2.051269 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1568467 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016174 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 227768377 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118855856 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87353688 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15126656 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8815414 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7066282 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90552040 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7992367 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1520027 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96996119 # Type of FU issued +system.cpu.iq.rate 2.051954 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1569390 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016180 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 227797779 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 118919368 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87372371 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15130016 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8817376 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7067715 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90571077 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7994425 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1518936 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5561649 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 19937 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34563 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1800253 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5562856 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 19876 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35099 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1798876 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10514 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10509 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3623048 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 133924 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17201 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 116441723 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 394323 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25557847 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8301356 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2358 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2853 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 36 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34563 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 569788 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 508452 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1078240 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95678343 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23422851 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1297604 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3627267 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 134249 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17377 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 116472912 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 393481 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25559054 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8299979 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2314 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2868 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 32 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35099 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 569232 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 508759 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1077991 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95699624 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23429474 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1296495 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10296358 # number of nop insts executed -system.cpu.iew.exec_refs 30504278 # number of memory reference insts executed -system.cpu.iew.exec_branches 12076445 # Number of branches executed -system.cpu.iew.exec_stores 7081427 # Number of stores executed -system.cpu.iew.exec_rate 2.023822 # Inst execution rate -system.cpu.iew.wb_sent 94963988 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94419970 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64608180 # num instructions producing a value -system.cpu.iew.wb_consumers 89987821 # num instructions consuming a value +system.cpu.iew.exec_nop 10300917 # number of nop insts executed +system.cpu.iew.exec_refs 30509089 # number of memory reference insts executed +system.cpu.iew.exec_branches 12078604 # Number of branches executed +system.cpu.iew.exec_stores 7079615 # Number of stores executed +system.cpu.iew.exec_rate 2.024527 # Inst execution rate +system.cpu.iew.wb_sent 94984897 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94440086 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64627368 # num instructions producing a value +system.cpu.iew.wb_consumers 90016132 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.997204 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717966 # average fanout of values written-back +system.cpu.iew.wb_rate 1.997881 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717953 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitCommittedOps 91903055 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 24539814 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 24570867 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 953116 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43562398 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.109688 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.736301 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 952438 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43551528 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.110214 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.736227 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17041146 39.12% 39.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9957627 22.86% 61.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4507142 10.35% 72.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2283698 5.24% 77.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1617573 3.71% 81.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1122316 2.58% 83.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 722162 1.66% 85.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 820666 1.88% 87.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5490068 12.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17031202 39.11% 39.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9950887 22.85% 61.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4509538 10.35% 72.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2291714 5.26% 77.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1611645 3.70% 81.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1125442 2.58% 83.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 722499 1.66% 85.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 819642 1.88% 87.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5488959 12.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43562398 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43551528 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -311,70 +311,70 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5490068 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5488959 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 154514159 # The number of ROB reads -system.cpu.rob.rob_writes 236533126 # The number of ROB writes -system.cpu.timesIdled 2183 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 90622 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 154535451 # The number of ROB reads +system.cpu.rob.rob_writes 236599608 # The number of ROB writes +system.cpu.timesIdled 2240 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 91326 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.561609 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.561609 # CPI: Total CPI of All Threads -system.cpu.ipc 1.780599 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.780599 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129442497 # number of integer regfile reads -system.cpu.int_regfile_writes 70765525 # number of integer regfile writes -system.cpu.fp_regfile_reads 6190739 # number of floating regfile reads -system.cpu.fp_regfile_writes 6047859 # number of floating regfile writes -system.cpu.misc_regfile_reads 714278 # number of misc regfile reads +system.cpu.cpi 0.561538 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.561538 # CPI: Total CPI of All Threads +system.cpu.ipc 1.780823 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.780823 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129477590 # number of integer regfile reads +system.cpu.int_regfile_writes 70782663 # number of integer regfile writes +system.cpu.fp_regfile_reads 6191536 # number of floating regfile reads +system.cpu.fp_regfile_writes 6049328 # number of floating regfile writes +system.cpu.misc_regfile_reads 714291 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 10359 # number of replacements -system.cpu.icache.tagsinuse 1607.190165 # Cycle average of tags in use -system.cpu.icache.total_refs 14929668 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 12297 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1214.090266 # Average number of references to valid blocks. +system.cpu.icache.replacements 10215 # number of replacements +system.cpu.icache.tagsinuse 1600.385722 # Cycle average of tags in use +system.cpu.icache.total_refs 14937616 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12152 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1229.231073 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1607.190165 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.784761 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.784761 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14929668 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14929668 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14929668 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14929668 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14929668 # number of overall hits -system.cpu.icache.overall_hits::total 14929668 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13679 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13679 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13679 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13679 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13679 # number of overall misses -system.cpu.icache.overall_misses::total 13679 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 203969000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 203969000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 203969000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 203969000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 203969000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 203969000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14943347 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14943347 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14943347 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14943347 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14943347 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14943347 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000915 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000915 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000915 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000915 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000915 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000915 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14911.104613 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14911.104613 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14911.104613 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14911.104613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14911.104613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14911.104613 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1600.385722 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.781438 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.781438 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14937616 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14937616 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14937616 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14937616 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14937616 # number of overall hits +system.cpu.icache.overall_hits::total 14937616 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13528 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13528 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13528 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13528 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13528 # number of overall misses +system.cpu.icache.overall_misses::total 13528 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 201479500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 201479500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 201479500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 201479500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 201479500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 201479500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14951144 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14951144 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14951144 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14951144 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14951144 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14951144 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000905 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000905 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000905 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000905 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000905 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000905 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14893.517150 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14893.517150 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14893.517150 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14893.517150 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14893.517150 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14893.517150 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -383,300 +383,300 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1382 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1382 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1382 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1382 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1382 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1382 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12297 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12297 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12297 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12297 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12297 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12297 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130905500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 130905500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130905500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 130905500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130905500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 130905500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000823 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000823 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000823 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10645.319997 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10645.319997 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10645.319997 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10645.319997 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10645.319997 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10645.319997 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1376 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1376 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1376 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1376 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1376 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1376 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12152 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12152 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12152 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12152 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12152 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12152 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130219500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 130219500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130219500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 130219500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130219500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 130219500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000813 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000813 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000813 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000813 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000813 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000813 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10715.890388 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10715.890388 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10715.890388 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10715.890388 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10715.890388 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10715.890388 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 158 # number of replacements -system.cpu.dcache.tagsinuse 1455.343539 # Cycle average of tags in use -system.cpu.dcache.total_refs 28184934 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2238 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12593.804290 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 1459.321585 # Cycle average of tags in use +system.cpu.dcache.total_refs 28191010 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2244 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12562.838681 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1455.343539 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.355308 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.355308 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 21691339 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21691339 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493048 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493048 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 547 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 547 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28184387 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28184387 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28184387 # number of overall hits -system.cpu.dcache.overall_hits::total 28184387 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 946 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 946 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8055 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8055 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1459.321585 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.356280 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.356280 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21697441 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21697441 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493044 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493044 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 525 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 525 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28190485 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28190485 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28190485 # number of overall hits +system.cpu.dcache.overall_hits::total 28190485 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 934 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 934 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8059 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8059 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9001 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9001 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9001 # number of overall misses -system.cpu.dcache.overall_misses::total 9001 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28453500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28453500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 289283500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 289283500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 8993 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8993 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8993 # number of overall misses +system.cpu.dcache.overall_misses::total 8993 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27907000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27907000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 290105500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 290105500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 38000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 38000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 317737000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 317737000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 317737000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 317737000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21692285 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21692285 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 318012500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 318012500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 318012500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 318012500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21698375 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21698375 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 548 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 548 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28193388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28193388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28193388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28193388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001239 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001239 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001825 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001825 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 526 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 526 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28199478 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28199478 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28199478 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28199478 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000043 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001240 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001240 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001901 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001901 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000319 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000319 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000319 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000319 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30077.695560 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30077.695560 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35913.531968 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35913.531968 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 29879.014989 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 29879.014989 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35997.704430 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35997.704430 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35300.188868 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35300.188868 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35300.188868 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35300.188868 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6500 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35362.226176 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35362.226176 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35362.226176 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35362.226176 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 1000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 435 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 435 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 421 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6329 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 6329 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6764 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6764 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6764 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6764 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 511 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 511 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1726 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1726 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 6750 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6750 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6750 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6750 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1730 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1730 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2237 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2237 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2237 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2237 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16444500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16444500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61474000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 61474000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2243 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2243 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2243 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2243 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16519000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16519000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61611500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61611500 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 77918500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 77918500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 77918500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 77918500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78130500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78130500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78130500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78130500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000265 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000265 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.001825 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.001825 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32181.017613 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32181.017613 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35616.454229 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35616.454229 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.001901 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.001901 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32200.779727 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32200.779727 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35613.583815 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35613.583815 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34831.694233 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34831.694233 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34831.694233 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34831.694233 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34833.036112 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34833.036112 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34833.036112 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34833.036112 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2429.489974 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9270 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3617 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.562897 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2418.588292 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9138 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3608 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.532705 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.697251 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2033.991651 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 377.801072 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.698469 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2020.214461 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 380.675363 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.062072 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.011530 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.074142 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 9204 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.061652 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.011617 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.073809 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 9070 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 54 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 9258 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 9124 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 108 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 108 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 9204 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 9070 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 80 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 9284 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 9204 # number of overall hits +system.cpu.l2cache.demand_hits::total 9150 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 9070 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 80 # number of overall hits -system.cpu.l2cache.overall_hits::total 9284 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3093 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 458 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3551 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1700 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1700 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3093 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2158 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5251 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3093 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2158 # number of overall misses -system.cpu.l2cache.overall_misses::total 5251 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 106153500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15762000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 121915500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 59022000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 59022000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 106153500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 74784000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 180937500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 106153500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 74784000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 180937500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 12297 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 512 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 12809 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_hits::total 9150 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3082 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 460 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3542 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1704 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1704 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3082 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2164 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5246 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3082 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2164 # number of overall misses +system.cpu.l2cache.overall_misses::total 5246 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 105790500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15832500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 121623000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 59198500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 59198500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 105790500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 75031000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 180821500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 105790500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 75031000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 180821500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 12152 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 514 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 12666 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 108 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 108 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1726 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1726 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 12297 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2238 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 14535 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12297 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2238 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 14535 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.251525 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894531 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.277227 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984936 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.984936 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.251525 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.964254 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.361266 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.251525 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.964254 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.361266 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34320.562561 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34414.847162 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34332.723177 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34718.823529 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34718.823529 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.562561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34654.309546 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34457.722339 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.562561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34654.309546 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34457.722339 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1730 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1730 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 12152 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2244 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 14396 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12152 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2244 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 14396 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.253621 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894942 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.279646 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984971 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.984971 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.253621 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964349 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.364407 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.253621 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964349 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.364407 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34325.275795 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34418.478261 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34337.380011 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34740.903756 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34740.903756 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34325.275795 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34672.365989 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34468.452154 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34325.275795 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34672.365989 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34468.452154 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3093 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3551 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1700 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1700 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3093 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2158 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5251 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3093 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2158 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5251 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 96110500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14313000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 110423500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53634000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53634000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96110500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67947000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 164057500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96110500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67947000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 164057500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894531 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.277227 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984936 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984936 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964254 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.361266 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964254 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.361266 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31073.553185 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31251.091703 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31096.451704 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31549.411765 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31549.411765 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31073.553185 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31486.098239 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31243.096553 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31073.553185 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31486.098239 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31243.096553 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3082 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 460 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3542 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1704 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1704 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3082 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2164 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5246 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3082 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2164 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5246 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 95761000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14382500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 110143500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53772000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53772000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 95761000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68154500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 163915500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 95761000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68154500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 163915500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.253621 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894942 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.279646 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984971 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984971 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.253621 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.364407 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.253621 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.364407 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31071.057755 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31266.304348 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31096.414455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31556.338028 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31556.338028 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31071.057755 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31494.685767 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31245.806329 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31071.057755 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31494.685767 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31245.806329 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 39023eb08..7fbc3a2c7 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout index 3fe1e7489..0bb9be5b6 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:18:52 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:47:30 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 5d71f2054..b947ca514 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.118740 # Nu sim_ticks 118740049000 # Number of ticks simulated final_tick 118740049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1590844 # Simulator instruction rate (inst/s) -host_op_rate 1590843 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2055391195 # Simulator tick rate (ticks/s) -host_mem_usage 218628 # Number of bytes of host memory used -host_seconds 57.77 # Real time elapsed on the host +host_inst_rate 2205371 # Simulator instruction rate (inst/s) +host_op_rate 2205370 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2849367775 # Simulator tick rate (ticks/s) +host_mem_usage 222752 # Number of bytes of host memory used +host_seconds 41.67 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory @@ -262,9 +262,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5951 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 5956 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.914120 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.915729 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 17.795183 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 1704.999565 # Average occupied blocks per requestor diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 292cbefed..bf679d420 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -507,7 +507,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index f8119727b..6b424cab1 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:52:11 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:29:26 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +21,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 76322764500 because target called exit() +122 123 124 Exiting @ tick 76049800000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 15323b4b4..a9dc709bb 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.076323 # Number of seconds simulated -sim_ticks 76322764500 # Number of ticks simulated -final_tick 76322764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.076050 # Number of seconds simulated +sim_ticks 76049800000 # Number of ticks simulated +final_tick 76049800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95790 # Simulator instruction rate (inst/s) -host_op_rate 104880 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42423254 # Simulator tick rate (ticks/s) -host_mem_usage 235620 # Number of bytes of host memory used -host_seconds 1799.08 # Real time elapsed on the host -sim_insts 172333279 # Number of instructions simulated -sim_ops 188686762 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 133376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 113216 # Number of bytes read from this memory -system.physmem.bytes_read::total 246592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 133376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 133376 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2084 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1769 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3853 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1747526 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1483384 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3230910 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1747526 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1747526 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1747526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1483384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3230910 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 156056 # Simulator instruction rate (inst/s) +host_op_rate 170865 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68866655 # Simulator tick rate (ticks/s) +host_mem_usage 238096 # Number of bytes of host memory used +host_seconds 1104.31 # Real time elapsed on the host +sim_insts 172333196 # Number of instructions simulated +sim_ops 188686678 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 132416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112128 # Number of bytes read from this memory +system.physmem.bytes_read::total 244544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 132416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 132416 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2069 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1752 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3821 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1741175 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1474402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3215577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1741175 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1741175 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1741175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1474402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3215577 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,141 +70,142 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 152645530 # number of cpu cycles simulated +system.cpu.numCycles 152099601 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 97143446 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 76317615 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 6623022 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 46654244 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 44354550 # Number of BTB hits +system.cpu.BPredUnit.lookups 96837963 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 76071776 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6557528 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 46441082 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 44202196 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4440290 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 115738 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40856932 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 389909160 # Number of instructions fetch has processed -system.cpu.fetch.Branches 97143446 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48794840 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 82559996 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 28665024 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7154273 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8876 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4477911 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 89401 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 40623947 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 388565051 # Number of instructions fetch has processed +system.cpu.fetch.Branches 96837963 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48680107 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 82289244 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 28490098 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7220589 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8612 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 37841460 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1897566 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 152586857 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.799629 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.155476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37659031 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1889609 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 152039589 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.799223 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.154384 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 70197419 46.00% 46.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5514909 3.61% 49.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10699531 7.01% 56.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10457896 6.85% 63.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8809329 5.77% 69.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6861836 4.50% 73.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6316245 4.14% 77.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8382546 5.49% 83.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25347146 16.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 69920012 45.99% 45.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5487559 3.61% 49.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10685692 7.03% 56.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10438123 6.87% 63.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8795207 5.78% 69.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6832085 4.49% 73.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6301825 4.14% 77.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8365502 5.50% 83.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25213584 16.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 152586857 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.636399 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.554344 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 46935408 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5876258 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76807695 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1114753 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21852743 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14847820 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 163458 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 403001894 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 745204 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21852743 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52498514 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 705487 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 794640 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 72299255 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4436218 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 380239935 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 319922 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3547314 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 643715569 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1619843514 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1602242427 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17601087 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298092552 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 345623017 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 60567 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 60564 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12828776 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 44110344 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16988908 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5691426 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3676812 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 335623795 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 80679 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 253280777 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 910888 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 145778004 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 375851378 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 29413 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 152586857 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.659912 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.759603 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 152039589 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.636675 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.554675 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 46670430 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5932664 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76574160 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1118361 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 21743974 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14821262 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 162795 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401681988 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 736800 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 21743974 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 52193760 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 715909 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 791714 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 72108942 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4485290 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 379159906 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 316677 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3600241 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 642535255 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1615137204 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1597539210 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17597994 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298092419 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 344442836 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 52681 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 52677 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12879836 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 44010443 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16892323 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5849879 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3738879 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 334925831 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 74527 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 252866200 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 897062 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 145077714 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 374156671 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 23276 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152039589 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.663160 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.758894 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 58969897 38.65% 38.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23051369 15.11% 53.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25143684 16.48% 70.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20551680 13.47% 83.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12918795 8.47% 92.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6596322 4.32% 96.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4048422 2.65% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1113826 0.73% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 192862 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 58521655 38.49% 38.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23034636 15.15% 53.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25191735 16.57% 70.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20480082 13.47% 83.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12877411 8.47% 92.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6577788 4.33% 96.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4065173 2.67% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1110646 0.73% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 180463 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 152586857 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152039589 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 968336 37.79% 37.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5589 0.22% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 91 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 33 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1185185 46.25% 84.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 403164 15.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 967418 37.56% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5599 0.22% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 146 0.01% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 21 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1198100 46.52% 84.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 404230 15.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 197697657 78.05% 78.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 995408 0.39% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 197377765 78.06% 78.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 996285 0.39% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued @@ -223,169 +224,169 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33135 0.01% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33143 0.01% 78.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164107 0.06% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 254969 0.10% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76438 0.03% 78.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467546 0.18% 78.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206313 0.08% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71855 0.03% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 39090450 15.43% 94.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14222579 5.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164246 0.06% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 255557 0.10% 78.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76455 0.03% 78.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 467877 0.19% 78.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206463 0.08% 78.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 39025783 15.43% 94.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14190441 5.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 253280777 # Type of FU issued -system.cpu.iq.rate 1.659274 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2562398 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010117 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 658846824 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 479250938 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 240868765 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3774873 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2250330 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1852271 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 253948063 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1895112 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2034666 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 252866200 # Type of FU issued +system.cpu.iq.rate 1.662504 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2575514 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010185 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 657470724 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 477849498 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 240611060 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3773841 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2247636 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1852910 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 253547208 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1894506 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2021626 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14254809 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18806 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19550 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4338224 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14154924 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 16760 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19840 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4241654 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 46 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21852743 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13300 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 608 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 335763367 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 963800 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 44110344 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16988908 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 58117 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 150 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 281 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19550 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4170846 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3956659 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8127505 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 246138856 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 37439094 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7141921 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 21743974 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13418 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 622 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 335058586 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 832362 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 44010443 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16892323 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 51985 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 162 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 263 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19840 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4108839 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3946041 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8054880 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 245860683 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 37402341 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7005517 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 58893 # number of nop insts executed -system.cpu.iew.exec_refs 51255438 # number of memory reference insts executed -system.cpu.iew.exec_branches 54101167 # Number of branches executed -system.cpu.iew.exec_stores 13816344 # Number of stores executed -system.cpu.iew.exec_rate 1.612486 # Inst execution rate -system.cpu.iew.wb_sent 243866975 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 242721036 # cumulative count of insts written-back -system.cpu.iew.wb_producers 150184249 # num instructions producing a value -system.cpu.iew.wb_consumers 269391648 # num instructions consuming a value +system.cpu.iew.exec_nop 58228 # number of nop insts executed +system.cpu.iew.exec_refs 51211338 # number of memory reference insts executed +system.cpu.iew.exec_branches 54022808 # Number of branches executed +system.cpu.iew.exec_stores 13808997 # Number of stores executed +system.cpu.iew.exec_rate 1.616445 # Inst execution rate +system.cpu.iew.wb_sent 243598204 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 242463970 # cumulative count of insts written-back +system.cpu.iew.wb_producers 150083518 # num instructions producing a value +system.cpu.iew.wb_consumers 269173561 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.590096 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557494 # average fanout of values written-back +system.cpu.iew.wb_rate 1.594113 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557572 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 172347667 # The number of committed instructions -system.cpu.commit.commitCommittedOps 188701150 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 147062192 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 51266 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6488296 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130734115 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.443396 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.157229 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 172347584 # The number of committed instructions +system.cpu.commit.commitCommittedOps 188701066 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 146357504 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 51251 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6423604 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130295616 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.448253 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.160604 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 60440090 46.23% 46.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 32094015 24.55% 70.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14011020 10.72% 81.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7691837 5.88% 87.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4423613 3.38% 90.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1340820 1.03% 91.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1731909 1.32% 93.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1286910 0.98% 94.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7713901 5.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 60033353 46.07% 46.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 32093498 24.63% 70.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14006031 10.75% 81.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7653781 5.87% 87.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4421161 3.39% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1332201 1.02% 91.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1737103 1.33% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1282008 0.98% 94.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7736480 5.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130734115 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172347667 # Number of instructions committed -system.cpu.commit.committedOps 188701150 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 130295616 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172347584 # Number of instructions committed +system.cpu.commit.committedOps 188701066 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42506219 # Number of memory references committed -system.cpu.commit.loads 29855535 # Number of loads committed +system.cpu.commit.refs 42506188 # Number of memory references committed +system.cpu.commit.loads 29855519 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40287733 # Number of branches committed +system.cpu.commit.branches 40287717 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150130425 # Number of committed integer instructions. +system.cpu.commit.int_insts 150130357 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7713901 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7736480 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 458778355 # The number of ROB reads -system.cpu.rob.rob_writes 693498788 # The number of ROB writes -system.cpu.timesIdled 1746 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58673 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172333279 # Number of Instructions Simulated -system.cpu.committedOps 188686762 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172333279 # Number of Instructions Simulated -system.cpu.cpi 0.885758 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.885758 # CPI: Total CPI of All Threads -system.cpu.ipc 1.128977 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.128977 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1093182861 # number of integer regfile reads -system.cpu.int_regfile_writes 388952433 # number of integer regfile writes -system.cpu.fp_regfile_reads 2911975 # number of floating regfile reads -system.cpu.fp_regfile_writes 2511798 # number of floating regfile writes -system.cpu.misc_regfile_reads 476343702 # number of misc regfile reads -system.cpu.misc_regfile_writes 832136 # number of misc regfile writes -system.cpu.icache.replacements 2645 # number of replacements -system.cpu.icache.tagsinuse 1374.603363 # Cycle average of tags in use -system.cpu.icache.total_refs 37836261 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4394 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8610.892353 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 457612505 # The number of ROB reads +system.cpu.rob.rob_writes 691979598 # The number of ROB writes +system.cpu.timesIdled 1775 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 60012 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172333196 # Number of Instructions Simulated +system.cpu.committedOps 188686678 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172333196 # Number of Instructions Simulated +system.cpu.cpi 0.882590 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.882590 # CPI: Total CPI of All Threads +system.cpu.ipc 1.133029 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.133029 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1092071141 # number of integer regfile reads +system.cpu.int_regfile_writes 388656879 # number of integer regfile writes +system.cpu.fp_regfile_reads 2914235 # number of floating regfile reads +system.cpu.fp_regfile_writes 2512527 # number of floating regfile writes +system.cpu.misc_regfile_reads 474801777 # number of misc regfile reads +system.cpu.misc_regfile_writes 832106 # number of misc regfile writes +system.cpu.icache.replacements 2596 # number of replacements +system.cpu.icache.tagsinuse 1365.085421 # Cycle average of tags in use +system.cpu.icache.total_refs 37653918 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4338 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8680.017981 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1374.603363 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.671193 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.671193 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37836261 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37836261 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37836261 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37836261 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37836261 # number of overall hits -system.cpu.icache.overall_hits::total 37836261 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5199 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5199 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5199 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5199 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5199 # number of overall misses -system.cpu.icache.overall_misses::total 5199 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 112756500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 112756500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 112756500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 112756500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 112756500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 112756500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37841460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37841460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37841460 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37841460 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37841460 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37841460 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000137 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000137 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000137 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000137 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000137 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000137 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21688.113099 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21688.113099 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21688.113099 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21688.113099 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1365.085421 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.666546 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.666546 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37653921 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37653921 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37653921 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37653921 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37653921 # number of overall hits +system.cpu.icache.overall_hits::total 37653921 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5110 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5110 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5110 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5110 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5110 # number of overall misses +system.cpu.icache.overall_misses::total 5110 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 111334000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 111334000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 111334000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 111334000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 111334000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 111334000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37659031 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37659031 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37659031 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37659031 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37659031 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37659031 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000136 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000136 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000136 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000136 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000136 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000136 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21787.475538 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21787.475538 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21787.475538 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21787.475538 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21787.475538 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21787.475538 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -394,246 +395,250 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 804 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 804 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 804 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 804 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 804 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 804 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4395 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4395 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4395 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4395 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4395 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4395 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78893000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 78893000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78893000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 78893000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78893000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 78893000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000116 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000116 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000116 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17950.625711 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17950.625711 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17950.625711 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17950.625711 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 768 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 768 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 768 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 768 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 768 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 768 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4342 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4342 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4342 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4342 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4342 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4342 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78323000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 78323000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78323000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 78323000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78323000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 78323000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000115 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000115 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000115 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000115 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000115 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000115 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18038.461538 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18038.461538 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18038.461538 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18038.461538 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18038.461538 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18038.461538 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 59 # number of replacements -system.cpu.dcache.tagsinuse 1421.643782 # Cycle average of tags in use -system.cpu.dcache.total_refs 47334662 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1881 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25164.626263 # Average number of references to valid blocks. +system.cpu.dcache.replacements 58 # number of replacements +system.cpu.dcache.tagsinuse 1413.439257 # Cycle average of tags in use +system.cpu.dcache.total_refs 47316793 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1865 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25370.934584 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1421.643782 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.347081 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.347081 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34919209 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34919209 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356677 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356677 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 30319 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 30319 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 28457 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 28457 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 47275886 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 47275886 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 47275886 # number of overall hits -system.cpu.dcache.overall_hits::total 47275886 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1860 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1860 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7610 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7610 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1413.439257 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.345078 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.345078 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34901837 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34901837 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356702 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356702 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 29806 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 29806 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 28442 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 28442 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 47258539 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 47258539 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 47258539 # number of overall hits +system.cpu.dcache.overall_hits::total 47258539 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1853 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1853 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7585 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7585 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9470 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9470 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9470 # number of overall misses -system.cpu.dcache.overall_misses::total 9470 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 60591000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 60591000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 237329500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 237329500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9438 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9438 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9438 # number of overall misses +system.cpu.dcache.overall_misses::total 9438 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59897500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59897500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 237415000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 237415000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 64000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 64000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 297920500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 297920500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 297920500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 297920500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34921069 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34921069 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 297312500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 297312500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 297312500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 297312500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34903690 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34903690 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30321 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 30321 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 28457 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 28457 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 47285356 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 47285356 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 47285356 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 47285356 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29808 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 29808 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 28442 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 28442 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 47267977 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 47267977 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 47267977 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 47267977 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000615 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000615 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000613 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000613 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000200 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000200 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000200 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000200 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32575.806452 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32575.806452 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31186.530880 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31186.530880 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32324.608743 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32324.608743 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31300.593276 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31300.593276 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31459.398099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31459.398099 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31501.642297 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31501.642297 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31501.642297 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31501.642297 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 19500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9750 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1056 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1056 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6533 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6533 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1071 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1071 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6498 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6498 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7589 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7589 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7589 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7589 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 804 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 804 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1881 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1881 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1881 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1881 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25610500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 25610500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 37862500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 37862500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63473000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63473000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63473000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63473000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7569 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7569 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7569 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7569 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 782 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1087 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1087 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1869 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1869 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1869 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1869 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24727500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24727500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38087000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 38087000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62814500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 62814500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62814500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 62814500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31853.855721 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31853.855721 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35155.524605 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35155.524605 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31620.843990 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31620.843990 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35038.638454 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35038.638454 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33608.614232 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33608.614232 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33608.614232 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33608.614232 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2017.739485 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2396 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2793 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.857859 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1980.325503 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2358 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2751 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.857143 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 4.002094 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1457.512395 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 556.224996 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000122 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.044480 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016975 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.061577 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2308 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2396 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 3.028951 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1438.887241 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 538.409312 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.043911 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016431 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.060435 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2267 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 92 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2359 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2308 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2405 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2308 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits -system.cpu.l2cache.overall_hits::total 2405 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2087 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 716 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2803 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1068 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1068 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2087 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1784 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3871 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2087 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1784 # number of overall misses -system.cpu.l2cache.overall_misses::total 3871 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71492500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24574000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 96066500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 36706000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 36706000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 71492500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 61280000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 132772500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 71492500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 61280000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 132772500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4395 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 804 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5199 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_hits::cpu.inst 2267 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 101 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2368 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2267 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 101 # number of overall hits +system.cpu.l2cache.overall_hits::total 2368 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2073 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 689 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2762 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1075 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1075 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2073 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1764 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3837 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2073 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1764 # number of overall misses +system.cpu.l2cache.overall_misses::total 3837 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71046500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23679500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 94726000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 36948500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 36948500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 71046500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 60628000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 131674500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 71046500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 60628000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 131674500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4340 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 781 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5121 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1077 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1077 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4395 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1881 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6276 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4395 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1881 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6276 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.474858 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.890547 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.539142 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991643 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.991643 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.474858 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.948432 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.616794 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.474858 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.948432 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.616794 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.109248 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34321.229050 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34272.743489 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34368.913858 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34368.913858 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34299.276673 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34299.276673 # average overall miss latency +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1084 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1084 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4340 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1865 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6205 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4340 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1865 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6205 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.477650 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.882202 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.539348 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991697 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.991697 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.477650 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.945845 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.618372 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.477650 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.945845 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.618372 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34272.310661 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34367.924528 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34296.162201 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34370.697674 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34370.697674 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34272.310661 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34369.614512 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34317.044566 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34272.310661 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34369.614512 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34317.044566 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -642,59 +647,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 18 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2084 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 701 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2785 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1068 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1068 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2084 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1769 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3853 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2084 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1769 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3853 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64692000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21857000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 86549000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33156000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33156000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64692000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 55013000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 119705000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64692000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 55013000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 119705000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871891 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.535680 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991643 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991643 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.613926 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.613926 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31042.226488 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31179.743224 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31076.840215 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.943820 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31044.943820 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2069 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 677 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2746 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2069 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1752 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3821 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2069 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1752 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3821 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64256500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21124000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 85380500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33377000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33377000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64256500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54501000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 118757500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64256500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54501000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 118757500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.476728 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866837 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.536223 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991697 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991697 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.476728 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.939410 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.615794 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.476728 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.939410 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.615794 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31056.790720 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31202.363368 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31092.680262 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31048.372093 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31048.372093 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31056.790720 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31107.876712 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31080.214604 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31056.790720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31107.876712 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31080.214604 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini index b72ac514a..337b40f6d 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -95,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout index 18d32cd6b..887de4fb8 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:53:41 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:29:40 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2 +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +21,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 103106771000 because target called exit() +122 123 124 Exiting @ tick 103106766000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index bbd6c00f1..0e78b9612 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.103107 # Number of seconds simulated -sim_ticks 103106771000 # Number of ticks simulated -final_tick 103106771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 103106766000 # Number of ticks simulated +final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2060024 # Simulator instruction rate (inst/s) -host_op_rate 2255526 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1232622542 # Simulator tick rate (ticks/s) -host_mem_usage 224496 # Number of bytes of host memory used -host_seconds 83.65 # Real time elapsed on the host -sim_insts 172317417 # Number of instructions simulated -sim_ops 188670900 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 759440240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 110533662 # Number of bytes read from this memory -system.physmem.bytes_read::total 869973902 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 759440240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 759440240 # Number of instructions bytes read from this memory +host_inst_rate 3148564 # Simulator instruction rate (inst/s) +host_op_rate 3447371 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1883953687 # Simulator tick rate (ticks/s) +host_mem_usage 227464 # Number of bytes of host memory used +host_seconds 54.73 # Real time elapsed on the host +sim_insts 172317409 # Number of instructions simulated +sim_ops 188670891 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory +system.physmem.bytes_read::total 869973865 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 759440204 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 759440204 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 189860060 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29622454 # Number of read requests responded to by this memory -system.physmem.num_reads::total 219482514 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 189860051 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29622453 # Number of read requests responded to by this memory +system.physmem.num_reads::total 219482504 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7365570977 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1072031070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8437602047 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7365570977 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7365570977 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 438893969 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 438893969 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7365570977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1510925039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8876496016 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 7365570985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1072031112 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8437602097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7365570985 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7365570985 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 438893991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 438893991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7365570985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1510925103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8876496088 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 206213543 # number of cpu cycles simulated +system.cpu.numCycles 206213533 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 172317417 # Number of instructions committed -system.cpu.committedOps 188670900 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses +system.cpu.committedInsts 172317409 # Number of instructions committed +system.cpu.committedOps 188670891 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses -system.cpu.num_func_calls 3504894 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32493891 # number of instructions that are conditional controls -system.cpu.num_int_insts 150106226 # number of integer instructions +system.cpu.num_func_calls 3545028 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 32493890 # number of instructions that are conditional controls +system.cpu.num_int_insts 150106218 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 809396650 # number of times the integer registers were read -system.cpu.num_int_register_writes 294073530 # number of times the integer registers were written +system.cpu.num_int_register_reads 809396612 # number of times the integer registers were read +system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_mem_refs 42494120 # number of memory refs -system.cpu.num_load_insts 29849485 # Number of load instructions +system.cpu.num_mem_refs 42494119 # number of memory refs +system.cpu.num_load_insts 29849484 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 206213543 # Number of busy cycles +system.cpu.num_busy_cycles 206213533 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini index 3e3d3dcbe..7a871da2f 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -176,7 +176,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout index 08e4c719e..0e8fdda90 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:54:15 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:30:46 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2 +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +21,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 232077154000 because target called exit() +122 123 124 Exiting @ tick 232077144000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 1e695b431..4c3bb52b8 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.232077 # Number of seconds simulated -sim_ticks 232077154000 # Number of ticks simulated -final_tick 232077154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 232077144000 # Number of ticks simulated +final_tick 232077144000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 665536 # Simulator instruction rate (inst/s) -host_op_rate 728833 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 898821179 # Simulator tick rate (ticks/s) -host_mem_usage 233632 # Number of bytes of host memory used -host_seconds 258.20 # Real time elapsed on the host -sim_insts 171842491 # Number of instructions simulated -sim_ops 188185929 # Number of ops (including micro ops) simulated +host_inst_rate 1482014 # Simulator instruction rate (inst/s) +host_op_rate 1622964 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2001492603 # Simulator tick rate (ticks/s) +host_mem_usage 236052 # Number of bytes of host memory used +host_seconds 115.95 # Real time elapsed on the host +sim_insts 171842483 # Number of instructions simulated +sim_ops 188185920 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory system.physmem.bytes_read::total 220992 # Number of bytes read from this memory @@ -70,43 +70,43 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 464154308 # number of cpu cycles simulated +system.cpu.numCycles 464154288 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 171842491 # Number of instructions committed -system.cpu.committedOps 188185929 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses +system.cpu.committedInsts 171842483 # Number of instructions committed +system.cpu.committedOps 188185920 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses -system.cpu.num_func_calls 3504894 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32493891 # number of instructions that are conditional controls -system.cpu.num_int_insts 150106226 # number of integer instructions +system.cpu.num_func_calls 3545028 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 32493890 # number of instructions that are conditional controls +system.cpu.num_int_insts 150106218 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 898652287 # number of times the integer registers were read -system.cpu.num_int_register_writes 294073530 # number of times the integer registers were written +system.cpu.num_int_register_reads 898652246 # number of times the integer registers were read +system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_mem_refs 42494120 # number of memory refs -system.cpu.num_load_insts 29849485 # Number of load instructions +system.cpu.num_mem_refs 42494119 # number of memory refs +system.cpu.num_load_insts 29849484 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 464154308 # Number of busy cycles +system.cpu.num_busy_cycles 464154288 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1506 # number of replacements -system.cpu.icache.tagsinuse 1147.981155 # Cycle average of tags in use -system.cpu.icache.total_refs 189857010 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1147.981203 # Cycle average of tags in use +system.cpu.icache.total_refs 189857001 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 62227.797443 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 62227.794494 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1147.981155 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1147.981203 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.560538 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.560538 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 189857010 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 189857010 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 189857010 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 189857010 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 189857010 # number of overall hits -system.cpu.icache.overall_hits::total 189857010 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 189857001 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 189857001 # number of overall hits +system.cpu.icache.overall_hits::total 189857001 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses @@ -119,12 +119,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 115332000 system.cpu.icache.demand_miss_latency::total 115332000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 115332000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 115332000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 189860061 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 189860061 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 189860061 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 189860061 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 189860061 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 189860061 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 189860052 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 189860052 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 189860052 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses @@ -171,26 +171,26 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 40 # number of replacements -system.cpu.dcache.tagsinuse 1363.604315 # Cycle average of tags in use -system.cpu.dcache.total_refs 42007359 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1363.604373 # Cycle average of tags in use +system.cpu.dcache.total_refs 42007358 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 23480.916154 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 23480.915595 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.604315 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 1363.604373 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.332911 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.332911 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 29599358 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 29599358 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41962545 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41962545 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41962545 # number of overall hits -system.cpu.dcache.overall_hits::total 41962545 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 41962544 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41962544 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41962544 # number of overall hits +system.cpu.dcache.overall_hits::total 41962544 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 689 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 689 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses @@ -207,18 +207,18 @@ system.cpu.dcache.demand_miss_latency::cpu.data 97454000 system.cpu.dcache.demand_miss_latency::total 97454000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 97454000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 97454000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 29600047 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 29600047 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 29600046 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 29600046 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41964334 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41964334 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41964334 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41964334 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 41964333 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41964333 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41964333 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41964333 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses @@ -279,14 +279,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1675.648030 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1379 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1675.648101 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1380 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.582102 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.582524 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 3.038048 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1169.027734 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 503.582248 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1169.027783 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 503.582269 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 1b6b8f01a..24899e6d1 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -510,7 +510,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing +cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index e9982c78d..34329ed9e 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 16:25:20 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 29 2012 00:01:11 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +22,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 87751730000 because target called exit() +122 123 124 Exiting @ tick 87734048000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 9505812e4..963d9307c 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,272 +1,272 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.087752 # Number of seconds simulated -sim_ticks 87751730000 # Number of ticks simulated -final_tick 87751730000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.087734 # Number of seconds simulated +sim_ticks 87734048000 # Number of ticks simulated +final_tick 87734048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66952 # Simulator instruction rate (inst/s) -host_op_rate 112217 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44484510 # Simulator tick rate (ticks/s) -host_mem_usage 236376 # Number of bytes of host memory used -host_seconds 1972.64 # Real time elapsed on the host +host_inst_rate 104988 # Simulator instruction rate (inst/s) +host_op_rate 175969 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69742772 # Simulator tick rate (ticks/s) +host_mem_usage 239080 # Number of bytes of host memory used +host_seconds 1257.97 # Real time elapsed on the host sim_insts 132071227 # Number of instructions simulated sim_ops 221363017 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 219584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 219520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125504 # Number of bytes read from this memory system.physmem.bytes_read::total 345024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219584 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3431 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 219520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219520 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3430 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1961 # Number of read requests responded to by this memory system.physmem.num_reads::total 5391 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2502332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1429487 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3931820 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2502332 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2502332 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2502332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1429487 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3931820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2502107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1430505 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3932612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2502107 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2502107 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2502107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1430505 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3932612 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 175503461 # number of cpu cycles simulated +system.cpu.numCycles 175468097 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 20929970 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 20929970 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2208761 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15515509 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 13857635 # Number of BTB hits +system.cpu.BPredUnit.lookups 20936810 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20936810 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2209025 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15519452 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13863485 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27320294 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 226942709 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20929970 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13857635 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59854483 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 19459786 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 71271521 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 647 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5211 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25822554 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 471165 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 175426420 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.136612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.300359 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27317448 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 226954156 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20936810 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13863485 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59860939 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 19465594 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 71226359 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 837 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7164 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25821692 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 473022 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 175391237 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.137569 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.300907 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 117249103 66.84% 66.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3234615 1.84% 68.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2477718 1.41% 70.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3147881 1.79% 71.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3542128 2.02% 73.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3766355 2.15% 76.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4530628 2.58% 78.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2823565 1.61% 80.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34654427 19.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 117206877 66.83% 66.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3231358 1.84% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2482815 1.42% 70.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3136542 1.79% 71.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3542923 2.02% 73.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3767949 2.15% 76.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4531829 2.58% 78.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2825666 1.61% 80.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34665278 19.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 175426420 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119257 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.293095 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40654970 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 61059749 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46547974 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10189463 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16974264 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 365977737 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16974264 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 48548849 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 16319097 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23046 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 48140036 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 45421128 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 356799059 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 33 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20636040 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22537767 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 2198 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 506554560 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1130537584 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1120266837 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10270747 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 175391237 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119320 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.293421 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40660130 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 61009372 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46541390 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10201855 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16978490 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 366073396 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16978490 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 48547252 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 16251189 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23056 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48155491 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 45435759 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 356858942 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 31 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20674050 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22523448 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 2249 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 506627728 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1130775437 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1120479419 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10296018 # Number of floating rename lookups system.cpu.rename.CommittedMaps 320143989 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 186410571 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1911 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1906 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 95097015 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89808446 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 33130186 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59201466 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19519303 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 344515408 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7842 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 270869041 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 254270 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 122674827 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 297005948 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6596 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 175426420 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.544061 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.467197 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 186483739 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1903 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1897 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 95061023 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89836107 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 33126554 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59108509 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19466725 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 344545895 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7937 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 270906839 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 256776 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 122697293 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 297019638 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6691 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 175391237 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.544586 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.467556 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 49131919 28.01% 28.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 52597597 29.98% 57.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34344440 19.58% 77.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18981960 10.82% 88.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12711399 7.25% 95.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4926918 2.81% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2079867 1.19% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 541264 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 111056 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 49119269 28.01% 28.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 52565616 29.97% 57.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34331484 19.57% 77.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18982131 10.82% 88.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12721464 7.25% 95.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4942775 2.82% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2076613 1.18% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 542627 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 109258 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 175426420 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 175391237 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91065 3.49% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2241508 85.86% 89.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 277930 10.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 90563 3.50% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2225289 85.92% 89.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 273998 10.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212815 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 176257528 65.07% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1592327 0.59% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68300084 25.22% 91.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23506287 8.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212985 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 176266302 65.07% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1595268 0.59% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68329319 25.22% 91.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23502965 8.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 270869041 # Type of FU issued -system.cpu.iq.rate 1.543383 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2610503 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009638 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 714724682 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 462639790 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 263265519 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5304593 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4857798 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2549095 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 269608691 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2658038 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18925158 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 270906839 # Type of FU issued +system.cpu.iq.rate 1.543909 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2589850 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009560 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 714739567 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 462675137 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 263287653 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5311974 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4876750 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2553148 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 269622080 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2661624 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18915593 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 33158856 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 30567 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 304625 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12614470 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 33186517 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 30708 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 305892 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12610838 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 47486 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 47515 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16974264 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 523635 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 253200 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 344523250 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 297274 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89808446 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 33130186 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1859 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 168556 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 31575 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 304625 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1298513 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1028751 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2327264 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 267763849 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 67223329 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3105192 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16978490 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 517280 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 233874 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 344553832 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 297077 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89836107 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 33126554 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1857 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 147591 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 33364 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 305892 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1298592 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1028927 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2327519 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 267790575 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 67240366 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3116264 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90337843 # number of memory reference insts executed -system.cpu.iew.exec_branches 14773998 # Number of branches executed -system.cpu.iew.exec_stores 23114514 # Number of stores executed -system.cpu.iew.exec_rate 1.525690 # Inst execution rate -system.cpu.iew.wb_sent 266689649 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 265814614 # cumulative count of insts written-back -system.cpu.iew.wb_producers 214459238 # num instructions producing a value -system.cpu.iew.wb_consumers 504388652 # num instructions consuming a value +system.cpu.iew.exec_refs 90351837 # number of memory reference insts executed +system.cpu.iew.exec_branches 14775060 # Number of branches executed +system.cpu.iew.exec_stores 23111471 # Number of stores executed +system.cpu.iew.exec_rate 1.526150 # Inst execution rate +system.cpu.iew.wb_sent 266714598 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 265840801 # cumulative count of insts written-back +system.cpu.iew.wb_producers 214478617 # num instructions producing a value +system.cpu.iew.wb_consumers 504376698 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.514583 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.425186 # average fanout of values written-back +system.cpu.iew.wb_rate 1.515038 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.425235 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 123271968 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 123301880 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2209353 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158452156 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.397034 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.794480 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2209791 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158412747 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.397381 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.795092 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 54225216 34.22% 34.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 60443910 38.15% 72.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15544008 9.81% 82.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12710691 8.02% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4546278 2.87% 93.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2974927 1.88% 94.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2086566 1.32% 96.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1244605 0.79% 97.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4675955 2.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 54206628 34.22% 34.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 60400758 38.13% 72.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15586261 9.84% 82.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12707072 8.02% 90.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4534557 2.86% 93.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2957745 1.87% 94.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2082808 1.31% 96.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1250624 0.79% 97.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4686294 2.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158452156 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158412747 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071227 # Number of instructions committed system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -277,70 +277,70 @@ system.cpu.commit.branches 12326943 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4675955 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4686294 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 498411186 # The number of ROB reads -system.cpu.rob.rob_writes 706281673 # The number of ROB writes -system.cpu.timesIdled 1684 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 77041 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 498391350 # The number of ROB reads +system.cpu.rob.rob_writes 706346628 # The number of ROB writes +system.cpu.timesIdled 1678 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76860 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071227 # Number of Instructions Simulated system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated -system.cpu.cpi 1.328855 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.328855 # CPI: Total CPI of All Threads -system.cpu.ipc 0.752528 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.752528 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 657510098 # number of integer regfile reads -system.cpu.int_regfile_writes 365370199 # number of integer regfile writes -system.cpu.fp_regfile_reads 3509073 # number of floating regfile reads -system.cpu.fp_regfile_writes 2221147 # number of floating regfile writes -system.cpu.misc_regfile_reads 139423581 # number of misc regfile reads +system.cpu.cpi 1.328587 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.328587 # CPI: Total CPI of All Threads +system.cpu.ipc 0.752679 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.752679 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 657568441 # number of integer regfile reads +system.cpu.int_regfile_writes 365395599 # number of integer regfile writes +system.cpu.fp_regfile_reads 3514318 # number of floating regfile reads +system.cpu.fp_regfile_writes 2225520 # number of floating regfile writes +system.cpu.misc_regfile_reads 139440665 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 5601 # number of replacements -system.cpu.icache.tagsinuse 1627.936468 # Cycle average of tags in use -system.cpu.icache.total_refs 25813461 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7571 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3409.518029 # Average number of references to valid blocks. +system.cpu.icache.replacements 5526 # number of replacements +system.cpu.icache.tagsinuse 1631.257386 # Cycle average of tags in use +system.cpu.icache.total_refs 25812694 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7496 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3443.529082 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1627.936468 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.794891 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.794891 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25813461 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25813461 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25813461 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25813461 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25813461 # number of overall hits -system.cpu.icache.overall_hits::total 25813461 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9093 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9093 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9093 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9093 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9093 # number of overall misses -system.cpu.icache.overall_misses::total 9093 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 187306000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 187306000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 187306000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 187306000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 187306000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 187306000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25822554 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25822554 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25822554 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25822554 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25822554 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25822554 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000352 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000352 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000352 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000352 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000352 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20598.922248 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20598.922248 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20598.922248 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20598.922248 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1631.257386 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.796512 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.796512 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25812694 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25812694 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25812694 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25812694 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25812694 # number of overall hits +system.cpu.icache.overall_hits::total 25812694 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8998 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8998 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8998 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8998 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8998 # number of overall misses +system.cpu.icache.overall_misses::total 8998 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 186818500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 186818500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 186818500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 186818500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 186818500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 186818500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25821692 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25821692 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25821692 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25821692 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25821692 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25821692 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000348 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000348 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000348 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000348 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000348 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000348 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20762.224939 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20762.224939 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20762.224939 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20762.224939 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20762.224939 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20762.224939 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -349,94 +349,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1367 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1367 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1367 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1367 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1367 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1367 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7726 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7726 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7726 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7726 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7726 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7726 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130634500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 130634500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130634500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 130634500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130634500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 130634500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16908.426094 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16908.426094 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16908.426094 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16908.426094 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1359 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1359 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1359 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1359 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1359 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1359 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7639 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7639 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7639 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7639 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7639 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7639 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130438500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 130438500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130438500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 130438500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130438500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 130438500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000296 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000296 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000296 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000296 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000296 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000296 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17075.337086 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17075.337086 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17075.337086 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17075.337086 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17075.337086 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17075.337086 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 56 # number of replacements -system.cpu.dcache.tagsinuse 1426.584624 # Cycle average of tags in use -system.cpu.dcache.total_refs 68642098 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1997 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34372.607912 # Average number of references to valid blocks. +system.cpu.dcache.replacements 57 # number of replacements +system.cpu.dcache.tagsinuse 1425.887115 # Cycle average of tags in use +system.cpu.dcache.total_refs 68669194 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1998 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34368.965966 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1426.584624 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.348287 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.348287 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 48127880 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 48127880 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514014 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514014 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68641894 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68641894 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68641894 # number of overall hits -system.cpu.dcache.overall_hits::total 68641894 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 772 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 772 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1716 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1716 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2488 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2488 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2488 # number of overall misses -system.cpu.dcache.overall_misses::total 2488 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24823500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24823500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 65115000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 65115000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 89938500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 89938500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 89938500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 89938500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 48128652 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 48128652 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1425.887115 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.348117 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.348117 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 48154983 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 48154983 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514026 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514026 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68669009 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68669009 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68669009 # number of overall hits +system.cpu.dcache.overall_hits::total 68669009 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 768 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 768 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1704 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1704 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2472 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2472 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2472 # number of overall misses +system.cpu.dcache.overall_misses::total 2472 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24800000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24800000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64672500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64672500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 89472500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 89472500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89472500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89472500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 48155751 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 48155751 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 68644382 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 68644382 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 68644382 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 68644382 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 68671481 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 68671481 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 68671481 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 68671481 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000016 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000083 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000036 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000036 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000036 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32154.792746 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32154.792746 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37945.804196 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37945.804196 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36148.914791 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36148.914791 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32291.666667 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32291.666667 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37953.345070 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37953.345070 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36194.377023 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36194.377023 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36194.377023 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36194.377023 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -445,32 +445,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 13 # number of writebacks -system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 331 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 331 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 14 # number of writebacks +system.cpu.dcache.writebacks::total 14 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 326 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 326 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 334 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 334 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 334 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 441 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 441 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1713 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1713 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2154 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2154 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2154 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2154 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14546500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 14546500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59868000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 59868000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 74414500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 74414500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 74414500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 74414500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 442 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 442 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1701 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1701 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2143 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2143 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2143 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2143 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14580500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14580500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59464500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 59464500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 74045000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 74045000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 74045000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 74045000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses @@ -479,104 +479,104 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32985.260771 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32985.260771 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34949.211909 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34949.211909 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34547.121634 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34547.121634 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32987.556561 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32987.556561 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34958.553792 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34958.553792 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34552.029865 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34552.029865 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34552.029865 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34552.029865 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2579.336511 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4173 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3841 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.086436 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2578.525319 # Cycle average of tags in use +system.cpu.l2cache.total_refs 4100 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3842 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 1.067153 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1.713269 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2279.819240 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 297.804001 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000052 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.069575 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.009088 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.078715 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 4140 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 1.139953 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2280.306781 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 297.078586 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000035 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.069589 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.009066 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.078690 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 4066 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 31 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 4171 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::total 4097 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 14 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 14 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4140 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 4066 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 4179 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4140 # number of overall hits +system.cpu.l2cache.demand_hits::total 4105 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 4066 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits -system.cpu.l2cache.overall_hits::total 4179 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3431 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 409 # number of ReadReq misses +system.cpu.l2cache.overall_hits::total 4105 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3430 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 410 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 3840 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 155 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 155 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 143 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 143 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 1551 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1551 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3431 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1960 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 3430 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1961 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 5391 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3431 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1960 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 3430 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1961 # number of overall misses system.cpu.l2cache.overall_misses::total 5391 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117518500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13976500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 131495000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 52996000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 52996000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 117518500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 66972500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 184491000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 117518500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 66972500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 184491000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7571 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 440 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 8011 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 155 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 155 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117492500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14011500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 131504000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 52997000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 52997000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 117492500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 67008500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 184501000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 117492500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 67008500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 184501000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7496 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 441 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7937 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 14 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 14 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 143 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 143 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1559 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1559 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 7571 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1999 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9570 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 7571 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1999 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9570 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.453177 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.929545 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.479341 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 7496 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2000 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9496 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 7496 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2000 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9496 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.457577 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.929705 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.483810 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994869 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.994869 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.453177 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.980490 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.563323 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.453177 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.980490 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.563323 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34251.967356 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34172.371638 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34243.489583 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34168.923275 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34168.923275 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34222.036728 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34222.036728 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.457577 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.980500 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.567713 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.457577 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.980500 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.567713 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34254.373178 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34174.390244 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34245.833333 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34169.568021 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34169.568021 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34254.373178 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34170.576237 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34223.891671 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34254.373178 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34170.576237 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34223.891671 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -585,58 +585,58 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3431 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 409 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3430 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 410 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 3840 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 155 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 155 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 143 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 143 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1551 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1551 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3431 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1960 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3430 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1961 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 5391 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3431 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1960 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3430 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1961 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5391 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106440500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12676500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 119117000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4805000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4805000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106414500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12709500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 119124000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4433000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4433000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48110500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48110500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106440500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60787000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 167227500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106440500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60787000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 167227500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929545 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.479341 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106414500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60820000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 167234500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106414500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60820000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 167234500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.457577 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929705 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.483810 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994869 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994869 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.563323 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.563323 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.171087 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30993.887531 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31020.052083 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.457577 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.567713 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.457577 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.567713 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31024.635569 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30998.780488 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31021.875000 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.019987 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31019.019987 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31019.755147 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31019.755147 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31024.635569 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.788373 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31021.053608 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31024.635569 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.788373 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31021.053608 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini index 3d56f1a99..168d19d0f 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -179,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index 3bc28071d..c17116a39 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 17:00:16 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 29 2012 00:23:42 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2 +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 8ebc5f697..8e544f41c 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250961 # Nu sim_ticks 250960631000 # Number of ticks simulated final_tick 250960631000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 653434 # Simulator instruction rate (inst/s) -host_op_rate 1095213 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1241649233 # Simulator tick rate (ticks/s) -host_mem_usage 232776 # Number of bytes of host memory used -host_seconds 202.12 # Real time elapsed on the host +host_inst_rate 1047161 # Simulator instruction rate (inst/s) +host_op_rate 1755134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1989805633 # Simulator tick rate (ticks/s) +host_mem_usage 234988 # Number of bytes of host memory used +host_seconds 126.12 # Real time elapsed on the host sim_insts 132071228 # Number of instructions simulated sim_ops 221363018 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory @@ -230,9 +230,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.588180 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.588496 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 0.021756 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 1829.968899 # Average occupied blocks per requestor |