diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
| commit | 10b70d54529f0a44dc088c9271d9ecf3a8ffe68a (patch) | |
| tree | 482dff6407c0b1c8cf1711f33d8ecad6acbf6c7f /tests/long/se/70.twolf | |
| parent | 9cbe1cb653428a2298644579ddf82c46272683d4 (diff) | |
| download | gem5-10b70d54529f0a44dc088c9271d9ecf3a8ffe68a.tar.xz | |
stats: Update stats for unified cache configuration
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
Diffstat (limited to 'tests/long/se/70.twolf')
4 files changed, 2032 insertions, 2016 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index a6fa2a523..ba13ea976 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041975 # Number of seconds simulated -sim_ticks 41974805000 # Number of ticks simulated -final_tick 41974805000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041949 # Number of seconds simulated +sim_ticks 41948719000 # Number of ticks simulated +final_tick 41948719000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82989 # Simulator instruction rate (inst/s) -host_op_rate 82989 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37903288 # Simulator tick rate (ticks/s) -host_mem_usage 220440 # Number of bytes of host memory used -host_seconds 1107.42 # Real time elapsed on the host +host_inst_rate 82495 # Simulator instruction rate (inst/s) +host_op_rate 82495 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37654494 # Simulator tick rate (ticks/s) +host_mem_usage 221732 # Number of bytes of host memory used +host_seconds 1114.04 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4260079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3269009 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7529088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4260079 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4260079 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4260079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3269009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7529088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4262728 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3271041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7533770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4262728 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4262728 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4262728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3271041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7533770 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 4938 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 41974753000 # Total gap between requests +system.physmem.totGap 41948681000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,13 +98,13 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 789 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3467 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 15273921 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 109715921 # Sum of mem lat for all requests +system.physmem.totQLat 18563928 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 107349928 # Sum of mem lat for all requests system.physmem.totBusLat 19752000 # Total cycles spent in databus access -system.physmem.totBankLat 74690000 # Total cycles spent in bank access -system.physmem.avgQLat 3093.14 # Average queueing delay per request -system.physmem.avgBankLat 15125.56 # Average bank access latency per request +system.physmem.totBankLat 69034000 # Total cycles spent in bank access +system.physmem.avgQLat 3759.40 # Average queueing delay per request +system.physmem.avgBankLat 13980.15 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22218.70 # Average memory access latency +system.physmem.avgMemAccLat 21739.56 # Average memory access latency system.physmem.avgRdBW 7.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 7.53 # Average consumed read bandwidth in MB/s @@ -184,27 +184,27 @@ system.physmem.readRowHits 4458 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8500355.00 # Average gap between requests +system.physmem.avgGap 8495075.13 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996215 # DTB read hits +system.cpu.dtb.read_hits 19996251 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996225 # DTB read accesses -system.cpu.dtb.write_hits 6501907 # DTB write hits +system.cpu.dtb.read_accesses 19996261 # DTB read accesses +system.cpu.dtb.write_hits 6501863 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501930 # DTB write accesses -system.cpu.dtb.data_hits 26498122 # DTB hits +system.cpu.dtb.write_accesses 6501886 # DTB write accesses +system.cpu.dtb.data_hits 26498114 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498155 # DTB accesses -system.cpu.itb.fetch_hits 10035744 # ITB hits +system.cpu.dtb.data_accesses 26498147 # DTB accesses +system.cpu.itb.fetch_hits 10035746 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 10035793 # ITB accesses +system.cpu.itb.fetch_accesses 10035795 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,26 +218,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83949611 # number of cpu cycles simulated +system.cpu.numCycles 83897439 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 13564912 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 9782242 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 13564910 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 9782241 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 4497823 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 7992579 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 3850502 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 7992573 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 3850501 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 122 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 48.175964 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 5999728 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.BTBHitPct 48.175988 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 5999726 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 7565184 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73745301 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 73745307 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136320773 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206799 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136320779 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206802 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8058687 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38528717 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.floatRegFileAccesses 8058690 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 38528710 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 26769089 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 3520477 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 976488 # Number of Branches Incorrectly Predicted As Not Taken). @@ -248,12 +248,12 @@ system.cpu.execution_unit.executions 57470360 # Nu system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83639616 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 83635742 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 11375 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7667023 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 76282588 # Number of cycles cpu stages are processed. -system.cpu.activity 90.867113 # Percentage of cycles cpu is active +system.cpu.timesIdled 10897 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7614848 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 76282591 # Number of cycles cpu stages are processed. +system.cpu.activity 90.923623 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -265,144 +265,144 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.913458 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.912891 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.913458 # CPI: Total CPI of All Threads -system.cpu.ipc 1.094741 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.912891 # CPI: Total CPI of All Threads +system.cpu.ipc 1.095421 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.094741 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27728071 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 56221540 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.970578 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34502106 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49447505 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.901411 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33971546 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49978065 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.533409 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65920043 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18029568 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.476655 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 30005535 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53944076 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.257684 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.095421 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27675918 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 56221521 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 67.012202 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34449958 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49447481 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.938010 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33919397 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49978042 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.570402 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65867839 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18029600 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.490048 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29953374 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53944065 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.297630 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 8127 # number of replacements -system.cpu.icache.tagsinuse 1492.468291 # Cycle average of tags in use -system.cpu.icache.total_refs 10023999 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1492.667941 # Cycle average of tags in use +system.cpu.icache.total_refs 10023995 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 10012 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1001.198462 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1001.198062 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.468291 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728744 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728744 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10023999 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10023999 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10023999 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10023999 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10023999 # number of overall hits -system.cpu.icache.overall_hits::total 10023999 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11743 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11743 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11743 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11743 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11743 # number of overall misses -system.cpu.icache.overall_misses::total 11743 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 259067500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 259067500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 259067500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 259067500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 259067500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 259067500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 10035742 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 10035742 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 10035742 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 10035742 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 10035742 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 10035742 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001170 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001170 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001170 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001170 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001170 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001170 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22061.440858 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22061.440858 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22061.440858 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22061.440858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22061.440858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22061.440858 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 67 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 16.750000 # average number of cycles each access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1492.667941 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728842 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728842 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10023995 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10023995 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10023995 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10023995 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10023995 # number of overall hits +system.cpu.icache.overall_hits::total 10023995 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11751 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11751 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11751 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11751 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11751 # number of overall misses +system.cpu.icache.overall_misses::total 11751 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 259062500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 259062500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 259062500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 259062500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 259062500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 259062500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 10035746 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 10035746 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 10035746 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 10035746 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 10035746 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 10035746 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001171 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001171 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001171 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001171 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001171 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001171 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22045.996085 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22045.996085 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22045.996085 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22045.996085 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22045.996085 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22045.996085 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1731 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1731 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1731 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1731 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1731 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1731 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1739 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1739 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1739 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1739 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1739 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1739 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10012 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 10012 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 10012 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 10012 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10012 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10012 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210374500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 210374500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210374500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 210374500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210374500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 210374500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209799500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 209799500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209799500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 209799500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209799500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 209799500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000998 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000998 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21012.235318 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21012.235318 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21012.235318 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21012.235318 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21012.235318 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21012.235318 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20954.804235 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20954.804235 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20954.804235 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20954.804235 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20954.804235 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20954.804235 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.629591 # Cycle average of tags in use -system.cpu.dcache.total_refs 26491183 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.862848 # Cycle average of tags in use +system.cpu.dcache.total_refs 26488630 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11916.861448 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11915.713000 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.629591 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.351960 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.351960 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995637 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995637 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6495546 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6495546 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26491183 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26491183 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26491183 # number of overall hits -system.cpu.dcache.overall_hits::total 26491183 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 561 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 561 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5557 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5557 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6118 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6118 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6118 # number of overall misses -system.cpu.dcache.overall_misses::total 6118 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28389500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28389500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 249397000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 249397000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 277786500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 277786500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 277786500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 277786500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 1441.862848 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.352017 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.352017 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995623 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493007 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493007 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488630 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488630 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488630 # number of overall hits +system.cpu.dcache.overall_hits::total 26488630 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 575 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 575 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8096 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8096 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8671 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8671 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8671 # number of overall misses +system.cpu.dcache.overall_misses::total 8671 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28479000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28479000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 330607000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 330607000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 359086000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 359086000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 359086000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 359086000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -411,40 +411,40 @@ system.cpu.dcache.demand_accesses::cpu.data 26497301 # system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000855 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000855 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000231 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000231 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000231 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000231 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50605.169340 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50605.169340 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44879.791254 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44879.791254 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45404.789147 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45404.789147 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45404.789147 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45404.789147 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 63919 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 77.290206 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001245 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001245 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49528.695652 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49528.695652 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40835.844862 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40835.844862 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41412.293853 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41412.293853 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41412.293853 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41412.293853 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11966 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 828 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.451691 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 86 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3809 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3809 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3895 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3895 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3895 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3895 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 100 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6348 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6348 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6448 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6448 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6448 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6448 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -453,14 +453,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23282500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23282500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80468500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 80468500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 103751000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 103751000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 103751000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 103751000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22783000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22783000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82274500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 82274500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 105057500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 105057500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 105057500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 105057500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -469,28 +469,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49015.789474 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49015.789474 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46034.610984 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46034.610984 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46671.614935 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 46671.614935 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46671.614935 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 46671.614935 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47964.210526 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47964.210526 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47067.791762 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47067.791762 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47259.334233 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 47259.334233 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47259.334233 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 47259.334233 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2189.948520 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2190.279989 # Cycle average of tags in use system.cpu.l2cache.total_refs 7285 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.219683 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.843388 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1821.063413 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.041719 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.844336 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1821.341583 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.094069 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055574 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010713 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066832 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055583 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010715 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066842 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 7218 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7271 # number of ReadReq hits @@ -515,17 +515,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 127870000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22259000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 150129000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78446500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 78446500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 127870000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 100705500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 228575500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 127870000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 100705500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 228575500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 127295000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21759500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 149054500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 80257000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 80257000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 127295000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 102016500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 229311500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 127295000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102016500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 229311500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 10012 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 10487 # number of ReadReq accesses(hits+misses) @@ -550,17 +550,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.403596 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.403596 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45765.926986 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52746.445498 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 46681.902985 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45555.458769 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45555.458769 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45765.926986 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46970.848881 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46289.084650 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45765.926986 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46970.848881 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46289.084650 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45560.128848 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51562.796209 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 46347.792289 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46606.852497 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46606.852497 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45560.128848 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47582.322761 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46438.132847 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45560.128848 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47582.322761 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46438.132847 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -580,17 +580,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 92500808 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16940683 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 109441491 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 57047489 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 57047489 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 92500808 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 73988172 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 166488980 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92500808 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 73988172 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 166488980 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 91926812 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16443678 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 108370490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59040867 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59040867 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91926812 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75484545 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 167411357 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91926812 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75484545 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 167411357 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306665 # mshr miss rate for ReadReq accesses @@ -602,17 +602,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.403596 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.403596 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33106.946314 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40143.798578 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34030.314366 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33128.623113 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33128.623113 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33106.946314 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34509.408582 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33715.872823 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33106.946314 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34509.408582 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33715.872823 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32901.507516 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38966.061611 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33697.291667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34286.217770 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34286.217770 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32901.507516 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35207.343750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33902.664439 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32901.507516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35207.343750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33902.664439 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index ca5f0ff42..ef2eb2fe7 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023631 # Number of seconds simulated -sim_ticks 23630830000 # Number of ticks simulated -final_tick 23630830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023714 # Number of seconds simulated +sim_ticks 23713623000 # Number of ticks simulated +final_tick 23713623000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120910 # Simulator instruction rate (inst/s) -host_op_rate 120910 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33941778 # Simulator tick rate (ticks/s) -host_mem_usage 221472 # Number of bytes of host memory used -host_seconds 696.22 # Real time elapsed on the host +host_inst_rate 202255 # Simulator instruction rate (inst/s) +host_op_rate 202255 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56975613 # Simulator tick rate (ticks/s) +host_mem_usage 222752 # Number of bytes of host memory used +host_seconds 416.21 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 197248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138368 # Number of bytes read from this memory -system.physmem.bytes_read::total 335616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 197248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 197248 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3082 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5244 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8347062 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5855402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14202463 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8347062 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8347062 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8347062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5855402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14202463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5244 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 196928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory +system.physmem.bytes_read::total 335488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 196928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 196928 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5242 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8304425 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5843055 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14147480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8304425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8304425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8304425 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5843055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14147480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5242 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5244 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 335616 # Total number of bytes read from memory +system.physmem.cpureqs 5242 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 335488 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 335616 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 335488 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 369 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 342 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 252 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 255 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 370 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 340 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 254 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 319 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 254 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 377 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 403 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 324 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 404 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 323 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 298 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 279 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 287 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 325 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 386 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 288 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 326 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 385 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 380 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 354 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 353 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23630742000 # Total gap between requests +system.physmem.totGap 23713517000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5244 # Categorize read packet sizes +system.physmem.readPktSize::6 5242 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,16 +98,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 23669737 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 116101737 # Sum of mem lat for all requests -system.physmem.totBusLat 20976000 # Total cycles spent in databus access -system.physmem.totBankLat 71456000 # Total cycles spent in bank access -system.physmem.avgQLat 4513.68 # Average queueing delay per request -system.physmem.avgBankLat 13626.24 # Average bank access latency per request +system.physmem.totQLat 21552231 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 116524231 # Sum of mem lat for all requests +system.physmem.totBusLat 20968000 # Total cycles spent in databus access +system.physmem.totBankLat 74004000 # Total cycles spent in bank access +system.physmem.avgQLat 4111.45 # Average queueing delay per request +system.physmem.avgBankLat 14117.51 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22139.92 # Average memory access latency -system.physmem.avgRdBW 14.20 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22228.96 # Average memory access latency +system.physmem.avgRdBW 14.15 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.20 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.15 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.09 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4702 # Number of row buffer hits during reads +system.physmem.readRowHits 4692 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.66 # Row buffer hit rate for reads +system.physmem.readRowHitRate 89.51 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4506243.71 # Average gap between requests +system.physmem.avgGap 4523753.72 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23223355 # DTB read hits -system.cpu.dtb.read_misses 199967 # DTB read misses -system.cpu.dtb.read_acv 4 # DTB read access violations -system.cpu.dtb.read_accesses 23423322 # DTB read accesses -system.cpu.dtb.write_hits 7080030 # DTB write hits -system.cpu.dtb.write_misses 1356 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 7081386 # DTB write accesses -system.cpu.dtb.data_hits 30303385 # DTB hits -system.cpu.dtb.data_misses 201323 # DTB misses -system.cpu.dtb.data_acv 6 # DTB access violations -system.cpu.dtb.data_accesses 30504708 # DTB accesses -system.cpu.itb.fetch_hits 14954333 # ITB hits -system.cpu.itb.fetch_misses 120 # ITB misses +system.cpu.dtb.read_hits 23220961 # DTB read hits +system.cpu.dtb.read_misses 199829 # DTB read misses +system.cpu.dtb.read_acv 2 # DTB read access violations +system.cpu.dtb.read_accesses 23420790 # DTB read accesses +system.cpu.dtb.write_hits 7077526 # DTB write hits +system.cpu.dtb.write_misses 1364 # DTB write misses +system.cpu.dtb.write_acv 6 # DTB write access violations +system.cpu.dtb.write_accesses 7078890 # DTB write accesses +system.cpu.dtb.data_hits 30298487 # DTB hits +system.cpu.dtb.data_misses 201193 # DTB misses +system.cpu.dtb.data_acv 8 # DTB access violations +system.cpu.dtb.data_accesses 30499680 # DTB accesses +system.cpu.itb.fetch_hits 14949647 # ITB hits +system.cpu.itb.fetch_misses 105 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14954453 # ITB accesses +system.cpu.itb.fetch_accesses 14949752 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,112 +218,113 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 47261661 # number of cpu cycles simulated +system.cpu.numCycles 47427247 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15031497 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10899201 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 964727 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 8732701 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7076597 # Number of BTB hits +system.cpu.BPredUnit.lookups 15025642 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10894363 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 964786 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 8694430 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7072700 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1487345 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 3368 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15614500 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 128263242 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15031497 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8563942 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22389896 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4636452 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5551739 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2133 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14954333 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 338853 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47196510 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.717643 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.372831 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1485982 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 3318 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15702309 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 128217574 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15025642 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8558682 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22383156 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4634796 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5563262 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 84 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2124 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 19 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14949647 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 339712 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47286808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.711487 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.371391 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24806614 52.56% 52.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2389980 5.06% 57.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1210958 2.57% 60.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1776777 3.76% 63.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2802179 5.94% 69.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1172690 2.48% 72.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1230204 2.61% 74.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 789239 1.67% 76.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11017869 23.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24903652 52.67% 52.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2390695 5.06% 57.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1208579 2.56% 60.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1776118 3.76% 64.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2803213 5.93% 69.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1173314 2.48% 72.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1230561 2.60% 75.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 786829 1.66% 76.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11013847 23.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47196510 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.318048 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.713896 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17460604 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4250656 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20766421 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1092488 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3626341 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2544445 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12397 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 125174951 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32088 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3626341 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18627234 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 962190 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8129 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20670858 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3301758 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 122185352 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 402329 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2427096 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89707747 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 158670699 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 148931458 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9739241 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 47286808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316815 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.703458 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17546675 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4261865 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20763738 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1090514 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3624016 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2545492 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12249 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 125138336 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32050 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3624016 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18714540 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 973231 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8290 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20663986 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3302745 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 122153228 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 68 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 400521 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2428440 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89689212 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 158636809 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 148888433 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9748376 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 21280386 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1002 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1014 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8742077 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25560713 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8304198 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2649829 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 949216 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 106168633 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2274 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96984807 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 186233 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21527282 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16158700 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1885 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47196510 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.054915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875207 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 21261851 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 999 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1008 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8748966 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25553670 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8298282 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2624329 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 917691 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 106148372 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2425 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96973982 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 186832 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21507239 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16151719 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2036 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47286808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.050762 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.875057 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12446961 26.37% 26.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9431395 19.98% 46.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8468096 17.94% 64.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6320682 13.39% 77.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4944837 10.48% 88.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2848295 6.03% 94.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1728522 3.66% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 798557 1.69% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 209165 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12523872 26.48% 26.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9450826 19.99% 46.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8468072 17.91% 64.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6321623 13.37% 77.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4941695 10.45% 88.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2845109 6.02% 94.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1728871 3.66% 97.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 797328 1.69% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 209412 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47196510 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47286808 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 189157 12.05% 12.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 237 0.02% 12.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7151 0.46% 12.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5547 0.35% 12.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843237 53.72% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 189731 12.08% 12.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 196 0.01% 12.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7230 0.46% 12.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5874 0.37% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 843349 53.68% 66.60% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.60% # attempts to use FU when none available @@ -345,19 +346,19 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.60% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 445222 28.36% 94.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 79100 5.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 445490 28.35% 94.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79325 5.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58989351 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 480619 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58981330 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 480636 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2802202 2.89% 64.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115471 0.12% 64.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2386536 2.46% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311369 0.32% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 759928 0.78% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2802326 2.89% 64.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115452 0.12% 64.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2386635 2.46% 66.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311394 0.32% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759833 0.78% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.89% # Type of FU issued @@ -379,84 +380,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23967188 24.71% 92.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7171817 7.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23966232 24.71% 92.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7169818 7.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96984807 # Type of FU issued -system.cpu.iq.rate 2.052082 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1569651 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016185 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 227791870 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118912637 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87370988 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15130138 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8820177 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7068200 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90559677 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7994774 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1518774 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96973982 # Type of FU issued +system.cpu.iq.rate 2.044689 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1571195 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016202 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 227861218 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 118862045 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87356059 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15131581 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8830751 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7068549 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90549768 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7995402 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1518620 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5564515 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 19809 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34734 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1803095 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5557472 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 19450 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34891 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1797179 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10505 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10488 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1489 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3626341 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 131070 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17619 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 116470742 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 396615 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25560713 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8304198 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2274 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3005 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34734 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 570082 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 507540 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1077622 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95693120 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23424012 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1291687 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3624016 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 135468 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17609 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 116444859 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 396288 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25553670 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8298282 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2425 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3185 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 28 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34891 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 568741 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 508698 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1077439 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95679677 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23421457 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1294305 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10299835 # number of nop insts executed -system.cpu.iew.exec_refs 30505591 # number of memory reference insts executed -system.cpu.iew.exec_branches 12076727 # Number of branches executed -system.cpu.iew.exec_stores 7081579 # Number of stores executed -system.cpu.iew.exec_rate 2.024752 # Inst execution rate -system.cpu.iew.wb_sent 94981894 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94439188 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64622529 # num instructions producing a value -system.cpu.iew.wb_consumers 90009959 # num instructions consuming a value +system.cpu.iew.exec_nop 10294062 # number of nop insts executed +system.cpu.iew.exec_refs 30500537 # number of memory reference insts executed +system.cpu.iew.exec_branches 12076025 # Number of branches executed +system.cpu.iew.exec_stores 7079080 # Number of stores executed +system.cpu.iew.exec_rate 2.017399 # Inst execution rate +system.cpu.iew.wb_sent 94965900 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94424608 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64613443 # num instructions producing a value +system.cpu.iew.wb_consumers 89987902 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.998220 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717949 # average fanout of values written-back +system.cpu.iew.wb_rate 1.990936 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.718024 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24568706 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 24543105 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 952874 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43570169 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.109311 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.735421 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 952948 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43662792 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.104837 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.733240 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17034200 39.10% 39.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9970297 22.88% 61.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4508116 10.35% 72.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2285317 5.25% 77.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1618875 3.72% 81.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1127711 2.59% 83.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 720325 1.65% 85.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 818054 1.88% 87.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5487274 12.59% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17112386 39.19% 39.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9977533 22.85% 62.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4511330 10.33% 72.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2294197 5.25% 77.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1617378 3.70% 81.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1129034 2.59% 83.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 721116 1.65% 85.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 819651 1.88% 87.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5480167 12.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43570169 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43662792 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -467,372 +468,372 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5487274 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5480167 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 154553616 # The number of ROB reads -system.cpu.rob.rob_writes 236594431 # The number of ROB writes -system.cpu.timesIdled 1889 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 65151 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 154627745 # The number of ROB reads +system.cpu.rob.rob_writes 236540658 # The number of ROB writes +system.cpu.timesIdled 5097 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 140439 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.561438 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.561438 # CPI: Total CPI of All Threads -system.cpu.ipc 1.781142 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.781142 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129470706 # number of integer regfile reads -system.cpu.int_regfile_writes 70779763 # number of integer regfile writes -system.cpu.fp_regfile_reads 6192026 # number of floating regfile reads -system.cpu.fp_regfile_writes 6049557 # number of floating regfile writes -system.cpu.misc_regfile_reads 714457 # number of misc regfile reads +system.cpu.cpi 0.563405 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.563405 # CPI: Total CPI of All Threads +system.cpu.ipc 1.774923 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.774923 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129451321 # number of integer regfile reads +system.cpu.int_regfile_writes 70766811 # number of integer regfile writes +system.cpu.fp_regfile_reads 6191777 # number of floating regfile reads +system.cpu.fp_regfile_writes 6050030 # number of floating regfile writes +system.cpu.misc_regfile_reads 714415 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 10301 # number of replacements -system.cpu.icache.tagsinuse 1602.585562 # Cycle average of tags in use -system.cpu.icache.total_refs 14940827 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 12238 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1220.855287 # Average number of references to valid blocks. +system.cpu.icache.replacements 10208 # number of replacements +system.cpu.icache.tagsinuse 1605.593166 # Cycle average of tags in use +system.cpu.icache.total_refs 14934718 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12146 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1229.599704 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1602.585562 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.782512 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.782512 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14940827 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14940827 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14940827 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14940827 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14940827 # number of overall hits -system.cpu.icache.overall_hits::total 14940827 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13506 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13506 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13506 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13506 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13506 # number of overall misses -system.cpu.icache.overall_misses::total 13506 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 154262500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 154262500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 154262500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 154262500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 154262500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 154262500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14954333 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14954333 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14954333 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14954333 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14954333 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14954333 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000903 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000903 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000903 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000903 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000903 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000903 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11421.775507 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 11421.775507 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11421.775507 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 11421.775507 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11421.775507 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 11421.775507 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1605.593166 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.783981 # 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number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 320401000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 320401000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 320401000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 320401000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 320401000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 320401000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14949646 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14949646 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14949646 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14949646 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14949646 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21463.089496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21463.089496 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 41.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106604500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 106604500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106604500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 106604500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106604500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 106604500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000818 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000818 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000818 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000818 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 242268500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242268500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 242268500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000812 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000812 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000812 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000812 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000812 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000812 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19946.360942 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19946.360942 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19946.360942 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19946.360942 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19946.360942 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19946.360942 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1457.159640 # Cycle average of tags in use -system.cpu.dcache.total_refs 28186155 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2241 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12577.489960 # Average number of references to valid blocks. +system.cpu.dcache.replacements 158 # number of replacements +system.cpu.dcache.tagsinuse 1458.435251 # Cycle average of tags in use +system.cpu.dcache.total_refs 28182735 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2245 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12553.556793 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1457.159640 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.355752 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.355752 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 21692653 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21692653 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493028 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493028 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 474 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 347386146 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 347386146 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 72000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 391882646 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 391882646 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 391882646 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 391882646 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21690346 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21690346 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 475 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 475 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28194692 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28194692 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28194692 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28194692 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000043 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001242 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001242 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002105 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002105 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000320 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000320 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000320 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000320 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31123.397436 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31123.397436 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28724.148607 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28724.148607 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 54000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 54000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28973.365886 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28973.365886 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28973.365886 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28973.365886 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 59 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 410 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 410 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28191449 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28191449 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28191449 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28191449 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001247 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001247 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002439 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002439 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000324 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000324 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000324 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000324 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43666.830226 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 43666.830226 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42866.010118 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42866.010118 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 42955.458292 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 42955.458292 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 42955.458292 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 42955.458292 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11029 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 474 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 23.267932 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107 # number of writebacks -system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 428 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 428 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6343 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6343 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6771 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6771 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6771 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6771 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 508 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 508 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 108 # number of writebacks +system.cpu.dcache.writebacks::total 108 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 508 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 508 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6371 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6371 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6879 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6879 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6879 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6879 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 511 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 511 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1733 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1733 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # 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number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 73724500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 73724500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 73724500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 73724500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002105 # 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average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48121.751298 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 70000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 70000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48862.074421 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48862.074421 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48862.074421 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48862.074421 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2409.771273 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9224 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3603 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.560089 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2419.268456 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9138 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3601 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.537628 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.696686 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2016.662499 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 375.412087 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.697198 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2024.332365 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 139425500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 106510500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 245936000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 12146 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 512 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 12658 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 108 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 108 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1733 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1733 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 12146 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 14391 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12146 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 14391 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.253334 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894531 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.279270 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984997 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.984997 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.253334 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964365 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.364255 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.253334 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964365 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.364255 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45312.154696 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55136.462882 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 46585.007072 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47602.811951 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47602.811951 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45312.154696 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49196.535797 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46916.444105 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45312.154696 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49196.535797 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46916.444105 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 21.500000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3082 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 455 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3537 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3077 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3535 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1707 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1707 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3082 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2162 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5244 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3082 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2162 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5244 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 74145562 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15695119 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 89840681 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48589265 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48589265 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74145562 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 64284384 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 138429946 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74145562 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 64284384 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 138429946 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.251839 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893910 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.277477 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985566 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985566 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.251839 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964748 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.362180 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.251839 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964748 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.362180 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 24057.612589 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34494.767033 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 25400.249081 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28464.712947 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28464.712947 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 24057.612589 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29733.757632 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 26397.777651 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 24057.612589 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29733.757632 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 26397.777651 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3077 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5242 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3077 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5242 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 100633163 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19510628 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 120143791 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60209566 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60209566 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 100633163 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79720194 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 180353357 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 100633163 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79720194 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 180353357 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.253334 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894531 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.279270 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984997 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984997 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.253334 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.364255 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.253334 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.364255 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32704.960351 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42599.624454 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33986.928147 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35272.153486 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35272.153486 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32704.960351 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36822.260508 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34405.447730 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32704.960351 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36822.260508 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34405.447730 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 49d6eef8e..3d59bfc93 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.075917 # Number of seconds simulated -sim_ticks 75916922000 # Number of ticks simulated -final_tick 75916922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.075963 # Number of seconds simulated +sim_ticks 75962996000 # Number of ticks simulated +final_tick 75962996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139176 # Simulator instruction rate (inst/s) -host_op_rate 152383 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61310301 # Simulator tick rate (ticks/s) -host_mem_usage 236468 # Number of bytes of host memory used -host_seconds 1238.24 # Real time elapsed on the host -sim_insts 172333316 # Number of instructions simulated -sim_ops 188686798 # Number of ops (including micro ops) simulated +host_inst_rate 82470 # Simulator instruction rate (inst/s) +host_op_rate 90296 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36352186 # Simulator tick rate (ticks/s) +host_mem_usage 236740 # Number of bytes of host memory used +host_seconds 2089.64 # Real time elapsed on the host +sim_insts 172333241 # Number of instructions simulated +sim_ops 188686723 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 132736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112320 # Number of bytes read from this memory -system.physmem.bytes_read::total 245056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory +system.physmem.bytes_read::total 244928 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 132736 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 132736 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 2074 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1755 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3829 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1748438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1479512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3227950 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1748438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1748438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1748438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1479512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3227950 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3829 # Total number of read requests seen +system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3827 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1747377 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1476930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3224307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1747377 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1747377 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1747377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1476930 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3224307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3828 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 3829 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 245056 # Total number of bytes read from memory +system.physmem.bytesRead 244928 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 245056 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 244928 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed system.physmem.perBankRdReqs::0 320 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 234 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 239 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 240 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 228 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 195 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 194 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 224 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 283 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 245 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 284 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 247 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 265 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 250 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 263 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 249 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 181 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 182 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 238 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 75916775000 # Total gap between requests +system.physmem.totGap 75962976500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3829 # Categorize read packet sizes +system.physmem.readPktSize::6 3828 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -95,16 +95,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 1 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 2774 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 838 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 44 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2829 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 12309321 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 87055321 # Sum of mem lat for all requests -system.physmem.totBusLat 15316000 # Total cycles spent in databus access -system.physmem.totBankLat 59430000 # Total cycles spent in bank access -system.physmem.avgQLat 3214.76 # Average queueing delay per request -system.physmem.avgBankLat 15521.02 # Average bank access latency per request +system.physmem.totQLat 15909310 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 90413310 # Sum of mem lat for all requests +system.physmem.totBusLat 15312000 # Total cycles spent in databus access +system.physmem.totBankLat 59192000 # Total cycles spent in bank access +system.physmem.avgQLat 4156.04 # Average queueing delay per request +system.physmem.avgBankLat 15462.90 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22735.79 # Average memory access latency -system.physmem.avgRdBW 3.23 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 23618.94 # Average memory access latency +system.physmem.avgRdBW 3.22 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.23 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.22 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3315 # Number of row buffer hits during reads +system.physmem.readRowHits 3324 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.58 # Row buffer hit rate for reads +system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19826788.98 # Average gap between requests +system.physmem.avgGap 19844037.75 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,141 +228,143 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 151833845 # number of cpu cycles simulated +system.cpu.numCycles 151925993 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 96840599 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 76060531 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 6557597 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 46497854 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 44230275 # Number of BTB hits +system.cpu.BPredUnit.lookups 96812188 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 76032236 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6553809 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 46446152 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 44209779 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4471070 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 89483 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40605581 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 388281645 # Number of instructions fetch has processed -system.cpu.fetch.Branches 96840599 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48701345 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 82243787 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 28438511 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7066827 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8646 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4476893 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 89558 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 40612935 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 388214882 # Number of instructions fetch has processed +system.cpu.fetch.Branches 96812188 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48686672 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 82228989 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 28431080 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7111966 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9226 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 37664937 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1885880 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 151789722 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.799994 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.153176 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37654254 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1887415 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 151824267 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.799061 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.153208 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 69716020 45.93% 45.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5494868 3.62% 49.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10713361 7.06% 56.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10448438 6.88% 63.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8787039 5.79% 69.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6829673 4.50% 73.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6296859 4.15% 77.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8361926 5.51% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25141538 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 69765849 45.95% 45.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5500538 3.62% 49.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10700560 7.05% 56.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10437997 6.88% 63.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8786758 5.79% 69.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6834684 4.50% 73.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6296298 4.15% 77.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8361211 5.51% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25140372 16.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151789722 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.637806 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.557280 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 46630303 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5777884 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76557243 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1112705 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21711587 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14823931 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 162890 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401294311 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 730539 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21711587 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52135013 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 698137 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 692737 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 72105161 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4447087 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 379004822 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 318070 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3558685 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 642471315 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1614529203 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1596934770 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17594433 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298092611 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 344378704 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33379 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 33376 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12572106 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43979277 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16887724 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5767479 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3738298 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 334855562 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 55454 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 252836764 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 889769 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 145001031 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 373941866 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4179 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151789722 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.665704 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.759623 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151824267 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.637233 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.555289 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 46639472 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5819765 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76543741 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1113557 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 21707732 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14816289 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 162918 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401266810 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 729123 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 21707732 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 52145776 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 716376 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 699385 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 72090483 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4464515 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 378976726 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 316631 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3575950 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 15 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 642441440 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1614452334 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1596874036 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17578298 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298092491 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 344348949 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 33473 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 33471 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12628265 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43987484 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16888261 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5791013 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3746055 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 334831031 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 55567 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 252811108 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 890392 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 144974552 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 373956822 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4307 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151824267 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.665156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.759693 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 58337035 38.43% 38.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22987248 15.14% 53.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25139726 16.56% 70.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20501728 13.51% 83.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12883464 8.49% 92.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6586273 4.34% 96.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4061259 2.68% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1111807 0.73% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181182 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 58367016 38.44% 38.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23007793 15.15% 53.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25146514 16.56% 70.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20482198 13.49% 83.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12879503 8.48% 92.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6581643 4.34% 96.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4062886 2.68% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1113562 0.73% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 183152 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151789722 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151824267 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 964155 37.62% 37.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5594 0.22% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 94 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 1 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 24 0.00% 37.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1191140 46.48% 84.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 401719 15.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 966665 37.55% 37.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5596 0.22% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 94 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 27 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1198357 46.55% 84.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 403391 15.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 197361954 78.06% 78.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 995375 0.39% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 197328873 78.05% 78.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 995382 0.39% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued @@ -381,419 +383,423 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33153 0.01% 78.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164117 0.06% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 255226 0.10% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76451 0.03% 78.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467799 0.19% 78.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206454 0.08% 78.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71861 0.03% 78.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 78.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 39017631 15.43% 94.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14186422 5.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33194 0.01% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 163810 0.06% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 255234 0.10% 78.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76440 0.03% 78.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 467356 0.18% 78.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206283 0.08% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71857 0.03% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 39021114 15.43% 94.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14191245 5.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 252836764 # Type of FU issued -system.cpu.iq.rate 1.665220 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2562727 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010136 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 657141484 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 477682512 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 240592268 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3774262 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2248392 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1852132 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 253504217 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1895274 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2034571 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 252811108 # Type of FU issued +system.cpu.iq.rate 1.664041 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2574130 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010182 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 657138452 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 477635375 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 240576408 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3772553 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2244745 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1851453 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 253490963 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1894275 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2028433 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14123734 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 16793 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19636 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4237031 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14131956 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 16953 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19730 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4237583 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 84 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21711587 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4884 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 553 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 334928786 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 838607 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43979277 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16887724 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 32914 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 218 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19636 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4106046 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3927041 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8033087 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 245835770 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 37393574 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7000994 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 21707732 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16237 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 835 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 334904365 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 834808 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43987484 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16888261 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 33011 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 269 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19730 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4101344 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3925912 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8027256 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 245818022 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 37400003 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6993086 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17770 # number of nop insts executed -system.cpu.iew.exec_refs 51200144 # number of memory reference insts executed -system.cpu.iew.exec_branches 54041718 # Number of branches executed -system.cpu.iew.exec_stores 13806570 # Number of stores executed -system.cpu.iew.exec_rate 1.619110 # Inst execution rate -system.cpu.iew.wb_sent 243578722 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 242444400 # cumulative count of insts written-back -system.cpu.iew.wb_producers 150079170 # num instructions producing a value -system.cpu.iew.wb_consumers 269183647 # num instructions consuming a value +system.cpu.iew.exec_nop 17767 # number of nop insts executed +system.cpu.iew.exec_refs 51208402 # number of memory reference insts executed +system.cpu.iew.exec_branches 54033495 # Number of branches executed +system.cpu.iew.exec_stores 13808399 # Number of stores executed +system.cpu.iew.exec_rate 1.618012 # Inst execution rate +system.cpu.iew.wb_sent 243559168 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 242427861 # cumulative count of insts written-back +system.cpu.iew.wb_producers 150062323 # num instructions producing a value +system.cpu.iew.wb_consumers 269174598 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.596774 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557534 # average fanout of values written-back +system.cpu.iew.wb_rate 1.595697 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557491 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 146227575 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 51275 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6404316 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130078136 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.450676 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.162324 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 146203238 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 51260 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6400494 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130116536 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.450247 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.162155 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59851320 46.01% 46.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 32072665 24.66% 70.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13982527 10.75% 81.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7658050 5.89% 87.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4412794 3.39% 90.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1335206 1.03% 91.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1737015 1.34% 93.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1288451 0.99% 94.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7740108 5.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59888298 46.03% 46.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 32076129 24.65% 70.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13982572 10.75% 81.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7654340 5.88% 87.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4412681 3.39% 90.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1335897 1.03% 91.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1741211 1.34% 93.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1283921 0.99% 94.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7741487 5.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130078136 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172347704 # Number of instructions committed -system.cpu.commit.committedOps 188701186 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 130116536 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172347629 # Number of instructions committed +system.cpu.commit.committedOps 188701111 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42506236 # Number of memory references committed -system.cpu.commit.loads 29855543 # Number of loads committed +system.cpu.commit.refs 42506206 # Number of memory references committed +system.cpu.commit.loads 29855528 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40306370 # Number of branches committed +system.cpu.commit.branches 40306355 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150130453 # Number of committed integer instructions. +system.cpu.commit.int_insts 150130393 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7740108 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7741487 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 457261588 # The number of ROB reads -system.cpu.rob.rob_writes 691688263 # The number of ROB writes -system.cpu.timesIdled 1182 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 44123 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172333316 # Number of Instructions Simulated -system.cpu.committedOps 188686798 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172333316 # Number of Instructions Simulated -system.cpu.cpi 0.881048 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.881048 # CPI: Total CPI of All Threads -system.cpu.ipc 1.135013 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.135013 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1091959933 # number of integer regfile reads -system.cpu.int_regfile_writes 388658885 # number of integer regfile writes -system.cpu.fp_regfile_reads 2913610 # number of floating regfile reads -system.cpu.fp_regfile_writes 2511674 # number of floating regfile writes -system.cpu.misc_regfile_reads 474503072 # number of misc regfile reads -system.cpu.misc_regfile_writes 832154 # number of misc regfile writes -system.cpu.icache.replacements 2619 # number of replacements -system.cpu.icache.tagsinuse 1372.300046 # Cycle average of tags in use -system.cpu.icache.total_refs 37659845 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4361 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8635.598487 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 457274197 # The number of ROB reads +system.cpu.rob.rob_writes 691635591 # The number of ROB writes +system.cpu.timesIdled 2582 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 101726 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172333241 # Number of Instructions Simulated +system.cpu.committedOps 188686723 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172333241 # Number of Instructions Simulated +system.cpu.cpi 0.881583 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.881583 # CPI: Total CPI of All Threads +system.cpu.ipc 1.134324 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.134324 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1091906245 # number of integer regfile reads +system.cpu.int_regfile_writes 388600616 # number of integer regfile writes +system.cpu.fp_regfile_reads 2911397 # number of floating regfile reads +system.cpu.fp_regfile_writes 2511024 # number of floating regfile writes +system.cpu.misc_regfile_reads 474438629 # number of misc regfile reads +system.cpu.misc_regfile_writes 832124 # number of misc regfile writes +system.cpu.icache.replacements 2644 # number of replacements +system.cpu.icache.tagsinuse 1367.286315 # Cycle average of tags in use +system.cpu.icache.total_refs 37648759 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4386 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8583.848381 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1372.300046 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.670068 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.670068 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37659851 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37659851 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37659851 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37659851 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37659851 # number of overall hits -system.cpu.icache.overall_hits::total 37659851 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5086 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5086 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5086 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5086 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5086 # number of overall misses -system.cpu.icache.overall_misses::total 5086 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 90441000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 90441000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 90441000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 90441000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 90441000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 90441000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37664937 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37664937 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37664937 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37664937 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37664937 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37664937 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000135 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000135 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000135 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000135 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000135 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000135 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17782.343689 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17782.343689 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17782.343689 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17782.343689 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17782.343689 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17782.343689 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29847.133758 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29847.133758 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29847.133758 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 669 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 37.166667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # 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Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25318.497859 # Average number of references to valid blocks. +system.cpu.dcache.replacements 57 # number of replacements +system.cpu.dcache.tagsinuse 1416.459985 # Cycle average of tags in use +system.cpu.dcache.total_refs 47307506 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1862 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25406.823845 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1419.994069 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.346678 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.346678 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34879202 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34879202 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356978 # 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number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 47258495 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 47258495 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 47258495 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 47258495 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000057 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000057 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000196 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000196 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000196 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000196 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27894.790603 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27894.790603 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21625.324942 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21625.324942 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22949.983814 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22949.983814 # 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miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45479.462475 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 45479.462475 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38644.436869 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38644.436869 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40033.704082 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40033.704082 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40033.704082 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40033.704082 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 45 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.363636 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1172 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1172 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6221 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6221 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1197 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1197 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6641 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6641 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7393 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7393 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7393 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7393 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 786 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 786 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 51545500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51545500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 51545500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7838 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7838 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7838 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7838 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 775 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 775 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1448.115408 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 540.474425 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.044193 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016494 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.060839 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2281 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 92 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2373 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 3.999610 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1449.117125 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 535.607885 # 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number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1083 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4363 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1868 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6231 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4363 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1868 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6231 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.477195 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.882803 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.539044 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992613 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.992613 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.477195 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.946467 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.617878 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.477195 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.946467 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.617878 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 29285.302594 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 32427.128427 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 30069.909910 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 25166.046512 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 25166.046512 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 29285.302594 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 28012.160633 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 28700.649351 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 29285.302594 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 28012.160633 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 28700.649351 # average overall miss latency +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1089 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1089 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4387 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1862 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6249 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4387 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1862 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6249 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.473900 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.886158 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.535659 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991736 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.991736 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.473900 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.947905 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.615138 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.473900 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.947905 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.615138 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47495.189995 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53024.817518 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48865.593343 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43983.796296 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43983.796296 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47495.189995 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47492.634561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 47494.016649 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47495.189995 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47492.634561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 47494.016649 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -802,59 +808,67 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 13 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 21 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2074 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 680 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2754 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2074 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1755 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3829 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2074 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1755 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3829 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53338835 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19774493 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 73113328 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 23276655 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 23276655 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53338835 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 43051148 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 96389983 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53338835 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 43051148 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 96389983 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.475361 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866242 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.534965 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.475361 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.939507 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.614508 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.475361 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.939507 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.614508 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 25717.856798 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 29080.136765 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 26548.049383 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 21652.702326 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 21652.702326 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 25717.856798 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 24530.568661 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 25173.670149 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 25717.856798 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 24530.568661 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 25173.670149 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2075 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 673 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2748 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1080 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1080 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2075 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3828 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2075 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3828 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 72306456 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27405972 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 99712428 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33965187 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33965187 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 72306456 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61371159 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 133677615 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 72306456 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61371159 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 133677615 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870634 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.532558 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991736 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991736 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941461 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.612578 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941461 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.612578 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34846.484819 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40722.098068 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36285.454148 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31449.247222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31449.247222 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34846.484819 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35009.217912 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34921.007053 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34846.484819 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35009.217912 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34921.007053 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 17b1f3559..e84462d08 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.084594 # Number of seconds simulated -sim_ticks 84594088000 # Number of ticks simulated -final_tick 84594088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.084675 # Number of seconds simulated +sim_ticks 84674525000 # Number of ticks simulated +final_tick 84674525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94248 # Simulator instruction rate (inst/s) -host_op_rate 157968 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60367706 # Simulator tick rate (ticks/s) -host_mem_usage 238096 # Number of bytes of host memory used -host_seconds 1401.31 # Real time elapsed on the host +host_inst_rate 95140 # Simulator instruction rate (inst/s) +host_op_rate 159463 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60996786 # Simulator tick rate (ticks/s) +host_mem_usage 238356 # Number of bytes of host memory used +host_seconds 1388.18 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362960 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 220544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124864 # Number of bytes read from this memory -system.physmem.bytes_read::total 345408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220544 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3446 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1951 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5397 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2607085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1476037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4083122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2607085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2607085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2607085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1476037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4083122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5399 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 219904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124736 # Number of bytes read from this memory +system.physmem.bytes_read::total 344640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219904 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3436 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1949 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5385 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2597050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1473123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4070173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2597050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2597050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2597050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1473123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4070173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5387 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5664 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 345408 # Total number of bytes read from memory +system.physmem.cpureqs 5559 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 344640 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 345408 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 344640 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 265 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 309 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 318 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 172 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 307 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 316 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 319 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 319 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 372 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 333 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 261 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 280 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 363 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 438 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 373 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 330 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 309 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 260 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 279 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 362 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 435 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 441 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 357 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 367 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 298 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 355 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 370 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 299 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 84594067000 # Total gap between requests +system.physmem.totGap 84674494000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5399 # Categorize read packet sizes +system.physmem.readPktSize::6 5387 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -95,16 +95,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 265 # categorize neither packet sizes +system.physmem.neitherpktsize::6 172 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 943 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,265 +164,266 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 16379877 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 123109877 # Sum of mem lat for all requests -system.physmem.totBusLat 21596000 # Total cycles spent in databus access +system.physmem.totQLat 14711866 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 121393866 # Sum of mem lat for all requests +system.physmem.totBusLat 21548000 # Total cycles spent in databus access system.physmem.totBankLat 85134000 # Total cycles spent in bank access -system.physmem.avgQLat 3033.87 # Average queueing delay per request -system.physmem.avgBankLat 15768.48 # Average bank access latency per request +system.physmem.avgQLat 2730.99 # Average queueing delay per request +system.physmem.avgBankLat 15803.60 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22802.35 # Average memory access latency -system.physmem.avgRdBW 4.08 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22534.60 # Average memory access latency +system.physmem.avgRdBW 4.07 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 4.08 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 4.07 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4777 # Number of row buffer hits during reads +system.physmem.readRowHits 4765 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.48 # Row buffer hit rate for reads +system.physmem.readRowHitRate 88.45 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15668469.53 # Average gap between requests +system.physmem.avgGap 15718302.21 # Average gap between requests system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 169188177 # number of cpu cycles simulated +system.cpu.numCycles 169349051 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 20680258 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 20680258 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2246160 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15085015 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 13721428 # Number of BTB hits +system.cpu.BPredUnit.lookups 20696936 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20696936 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2256292 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15133236 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13734962 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27164568 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227213982 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20680258 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13721428 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59660749 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 19257155 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 65568957 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 236 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1768 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25653013 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 474244 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169131808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.211225 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.333765 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27265023 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227328092 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20696936 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13734962 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59711428 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 19294366 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 65485440 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 310 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1823 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 77 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 25705537 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 473097 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169231475 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.210885 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.333405 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 111136116 65.71% 65.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3216747 1.90% 67.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2468197 1.46% 69.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3082745 1.82% 70.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3525528 2.08% 72.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3731818 2.21% 75.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4565922 2.70% 77.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2807540 1.66% 79.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34597195 20.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 111185486 65.70% 65.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3235568 1.91% 67.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2477028 1.46% 69.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3104255 1.83% 70.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3512943 2.08% 72.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3722385 2.20% 75.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4581451 2.71% 77.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2802404 1.66% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34609955 20.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169131808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122232 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.342966 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40083092 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 55790408 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46646195 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9876583 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16735530 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 364948187 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16735530 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47642140 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14699446 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23267 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 48304644 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41726781 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355757826 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 35 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17417112 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22198638 # Number of times rename has blocked due to LSQ full +system.cpu.fetch.rateDist::total 169231475 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122215 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.342364 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40175646 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 55730709 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46717910 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9839836 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16767374 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 365014393 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16767374 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 47729605 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14672331 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23050 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48352284 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41686831 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355859336 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17343697 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22236120 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 51 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 410011414 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 986948203 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 977030227 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9917976 # Number of floating rename lookups +system.cpu.rename.RenamedOperands 410085130 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 987094969 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 977133981 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9960988 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259428603 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 150582811 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1844 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1841 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 90083407 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89641616 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 32814586 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59002795 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19228439 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 342836678 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4827 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 271794183 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 309279 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 120959244 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 246380396 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3581 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169131808 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.606996 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.512238 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 150656527 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1756 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1746 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 90004350 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89661097 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 32850020 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59013027 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19193820 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 342911318 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4601 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 271901324 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 302838 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 121030414 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 246288577 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3355 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169231475 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.606683 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.513723 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 47364329 28.00% 28.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46969212 27.77% 55.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33133132 19.59% 75.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20170100 11.93% 87.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13409099 7.93% 95.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4965437 2.94% 98.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2407480 1.42% 99.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 564206 0.33% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 148813 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 47472289 28.05% 28.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 47010231 27.78% 55.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33048937 19.53% 75.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20116720 11.89% 87.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13476087 7.96% 95.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4976431 2.94% 98.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2409834 1.42% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 570016 0.34% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 150930 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169131808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169231475 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 133221 5.02% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2254463 85.01% 90.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 264273 9.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 133953 5.05% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2250624 84.89% 89.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 266784 10.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212759 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 177009113 65.13% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212972 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 177077896 65.13% 65.57% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.57% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1584136 0.58% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68507132 25.21% 91.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23481043 8.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1583975 0.58% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68517375 25.20% 91.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23509106 8.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 271794183 # Type of FU issued -system.cpu.iq.rate 1.606461 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2651957 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009757 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 710390564 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 459507075 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 264054683 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5290846 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4594594 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2539782 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 270581714 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2651667 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19012084 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 271901324 # Type of FU issued +system.cpu.iq.rate 1.605567 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2651361 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009751 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 710689981 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 459620232 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 264156330 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5298341 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4622160 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2541189 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 270684077 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2655636 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19034495 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 32992030 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 32876 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 306652 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12298870 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 33011511 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33645 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 301635 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12334304 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49471 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49870 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 57 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16735530 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 583808 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 272322 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 342841505 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 257255 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89641616 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 32814586 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1824 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 184475 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 30365 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 306652 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1330858 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1021453 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2352311 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 268621044 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 67379328 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3173139 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16767374 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 579251 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 261764 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 342915919 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 264352 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89661097 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 32850020 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1726 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 174105 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29972 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 301635 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1337300 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1023491 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2360791 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 268724619 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 67385634 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3176705 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90456785 # number of memory reference insts executed -system.cpu.iew.exec_branches 14766526 # Number of branches executed -system.cpu.iew.exec_stores 23077457 # Number of stores executed -system.cpu.iew.exec_rate 1.587706 # Inst execution rate -system.cpu.iew.wb_sent 267534302 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 266594465 # cumulative count of insts written-back -system.cpu.iew.wb_producers 215217179 # num instructions producing a value -system.cpu.iew.wb_consumers 378376353 # num instructions consuming a value +system.cpu.iew.exec_refs 90490308 # number of memory reference insts executed +system.cpu.iew.exec_branches 14777839 # Number of branches executed +system.cpu.iew.exec_stores 23104674 # Number of stores executed +system.cpu.iew.exec_rate 1.586809 # Inst execution rate +system.cpu.iew.wb_sent 267641874 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 266697519 # cumulative count of insts written-back +system.cpu.iew.wb_producers 215269478 # num instructions producing a value +system.cpu.iew.wb_consumers 378445061 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.575728 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.568791 # average fanout of values written-back +system.cpu.iew.wb_rate 1.574839 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.568826 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 121559121 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 121635359 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2246323 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 152396278 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.452548 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.926116 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2256476 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 152464101 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.451902 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.927405 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52678390 34.57% 34.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57577424 37.78% 72.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14059718 9.23% 81.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11956991 7.85% 89.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4305123 2.82% 92.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2949818 1.94% 94.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1066386 0.70% 94.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 992195 0.65% 95.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6810233 4.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52775060 34.61% 34.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57579919 37.77% 72.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14057130 9.22% 81.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11929298 7.82% 89.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4294184 2.82% 92.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2937870 1.93% 94.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1056484 0.69% 94.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 997351 0.65% 95.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6836805 4.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 152396278 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 152464101 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -433,306 +434,306 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339549 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6810233 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6836805 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 488508126 # The number of ROB reads -system.cpu.rob.rob_writes 702620216 # The number of ROB writes -system.cpu.timesIdled 1506 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 56369 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 488625615 # The number of ROB reads +system.cpu.rob.rob_writes 702805180 # The number of ROB writes +system.cpu.timesIdled 3014 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 117576 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362960 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 1.281038 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.281038 # CPI: Total CPI of All Threads -system.cpu.ipc 0.780617 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.780617 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 567639196 # number of integer regfile reads -system.cpu.int_regfile_writes 302703765 # number of integer regfile writes -system.cpu.fp_regfile_reads 3495797 # number of floating regfile reads -system.cpu.fp_regfile_writes 2211250 # number of floating regfile writes -system.cpu.misc_regfile_reads 139399302 # number of misc regfile reads +system.cpu.cpi 1.282256 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.282256 # CPI: Total CPI of All Threads +system.cpu.ipc 0.779876 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.779876 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 567778401 # number of integer regfile reads +system.cpu.int_regfile_writes 302773713 # number of integer regfile writes +system.cpu.fp_regfile_reads 3495333 # number of floating regfile reads +system.cpu.fp_regfile_writes 2213146 # number of floating regfile writes +system.cpu.misc_regfile_reads 139456752 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 5641 # number of replacements -system.cpu.icache.tagsinuse 1641.401127 # Cycle average of tags in use -system.cpu.icache.total_refs 25643925 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7612 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3368.881372 # Average number of references to valid blocks. +system.cpu.icache.replacements 5349 # number of replacements +system.cpu.icache.tagsinuse 1642.940012 # Cycle average of tags in use +system.cpu.icache.total_refs 25695767 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7318 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3511.310057 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1641.401127 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.801465 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.801465 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25643925 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25643925 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25643925 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25643925 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25643925 # number of overall hits -system.cpu.icache.overall_hits::total 25643925 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9088 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9088 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9088 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9088 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9088 # number of overall misses -system.cpu.icache.overall_misses::total 9088 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 147639500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 147639500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 147639500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 147639500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 147639500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 147639500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25653013 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25653013 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25653013 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25653013 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25653013 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25653013 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000354 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000354 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000354 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000354 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000354 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000354 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16245.543574 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16245.543574 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16245.543574 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16245.543574 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16245.543574 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16245.543574 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1642.940012 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.802217 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.802217 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25695767 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25695767 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25695767 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25695767 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25695767 # number of overall hits +system.cpu.icache.overall_hits::total 25695767 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9770 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9770 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9770 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9770 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9770 # number of overall misses +system.cpu.icache.overall_misses::total 9770 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 270457998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 270457998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 270457998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 270457998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 270457998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 270457998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25705537 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25705537 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25705537 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25705537 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25705537 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25705537 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000380 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000380 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000380 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000380 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000380 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000380 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27682.497236 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27682.497236 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27682.497236 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27682.497236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27682.497236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27682.497236 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 937 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # 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number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7877 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7877 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7877 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7877 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7877 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 110101000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 110101000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 110101000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 110101000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 110101000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 110101000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000307 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000307 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000307 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13977.529516 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13977.529516 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13977.529516 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13977.529516 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13977.529516 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13977.529516 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2279 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2279 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2279 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2279 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2279 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2279 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7491 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7491 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7491 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7491 # 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mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000291 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000291 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000291 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27374.515819 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27374.515819 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27374.515819 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27374.515819 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27374.515819 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27374.515819 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # 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miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000085 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000085 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37048.979592 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37048.979592 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24669.857768 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24669.857768 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28219.859540 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28219.859540 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28219.859540 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28219.859540 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46282.129743 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 46282.129743 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44225.806452 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44225.806452 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 44883.862123 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 44883.862123 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 44883.862123 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 44883.862123 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 262 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 15 # 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number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 58607500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 13 # number of writebacks +system.cpu.dcache.writebacks::total 13 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 388 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 388 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 390 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 390 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 390 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 390 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 429 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 429 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 28319.252432 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 28354.880533 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994882 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994882 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.469463 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.979910 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.578625 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.469463 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.979910 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.578625 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46150.320140 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55232.323232 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 47088.856994 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43543.729904 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43543.729904 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46150.320140 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 45916.196822 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46065.528123 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46150.320140 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 45916.196822 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46065.528123 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -741,58 +742,58 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3446 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 401 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3847 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 265 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 265 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1552 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115214557 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 64882583 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 180097140 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115214557 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 64882583 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 180097140 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.469463 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.925234 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.494643 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994872 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994872 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.452706 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980422 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.562162 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.452706 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980422 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.562162 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 24764.514510 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38259.628429 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 26171.205615 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 1001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 1001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 21214.230670 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 21214.230670 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 24764.514510 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 24714.079365 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 24746.270420 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 24764.514510 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 24714.079365 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 24746.270420 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.469463 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.979910 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.578625 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.469463 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979910 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.578625 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33531.594005 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42723.724747 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34481.511482 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30845.008360 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30845.008360 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33531.594005 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33256.065095 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33431.806200 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33531.594005 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33256.065095 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33431.806200 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |