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authorAli Saidi <Ali.Saidi@ARM.com>2012-09-25 11:49:41 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2012-09-25 11:49:41 -0500
commit91e74beee60b2085d18dfbfd51018dce2c779d8d (patch)
tree96a71f2f316d24e9378bc3a68df207880e0eccca /tests/long/se/70.twolf
parent80a26a3e39874dab7c0b51cd5ce0258039494e30 (diff)
downloadgem5-91e74beee60b2085d18dfbfd51018dce2c779d8d.tar.xz
ARM: update stats for bp and squash fixes.
Diffstat (limited to 'tests/long/se/70.twolf')
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini31
-rwxr-xr-xtests/long/se/70.twolf/ref/arm/linux/o3-timing/simout14
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt1091
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini21
-rwxr-xr-xtests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout10
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt12
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini31
-rwxr-xr-xtests/long/se/70.twolf/ref/arm/linux/simple-timing/simout12
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt12
9 files changed, 625 insertions, 609 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index 3f37afa6e..6abd7ca4a 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -95,7 +96,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-phase=0
predType=tournament
profile=0
progress_interval=0
@@ -129,16 +129,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=1
forward_snoops=true
hash_delay=1
+hit_latency=1000
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=1000
size=262144
subblock_size=0
system=system
@@ -157,8 +159,8 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
+clock=1
+num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -430,16 +432,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=1
forward_snoops=true
hash_delay=1
+hit_latency=1000
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=1000
size=131072
subblock_size=0
system=system
@@ -461,8 +465,8 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
+clock=1
+num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -471,16 +475,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=1
forward_snoops=true
hash_delay=1
+hit_latency=1000
is_top_level=false
-latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=1000
size=2097152
subblock_size=0
system=system
@@ -507,12 +513,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing
+cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
@@ -530,13 +536,14 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
index e4047fa1c..b01ca9643 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
@@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 09:08:16
-gem5 started Jul 2 2012 16:47:08
-gem5 executing on zizzer
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing
-Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sav
-Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
+gem5 compiled Sep 21 2012 11:19:00
+gem5 started Sep 21 2012 13:57:03
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
+Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
+Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -23,4 +23,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 76017712000 because target called exit()
+122 123 124 Exiting @ tick 76020082000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index abf6c428d..e95f937b3 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -1,32 +1,32 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.076018 # Number of seconds simulated
-sim_ticks 76017712000 # Number of ticks simulated
-final_tick 76017712000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.076020 # Number of seconds simulated
+sim_ticks 76020082000 # Number of ticks simulated
+final_tick 76020082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 156722 # Simulator instruction rate (inst/s)
-host_op_rate 171594 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 69131199 # Simulator tick rate (ticks/s)
-host_mem_usage 238024 # Number of bytes of host memory used
-host_seconds 1099.62 # Real time elapsed on the host
-sim_insts 172333351 # Number of instructions simulated
-sim_ops 188686833 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 131968 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory
-system.physmem.bytes_read::total 244160 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 131968 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 131968 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 2062 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 3815 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1736016 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1475867 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3211883 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1736016 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1736016 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1736016 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1475867 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3211883 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 108434 # Simulator instruction rate (inst/s)
+host_op_rate 118724 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 47832871 # Simulator tick rate (ticks/s)
+host_mem_usage 232824 # Number of bytes of host memory used
+host_seconds 1589.29 # Real time elapsed on the host
+sim_insts 172333166 # Number of instructions simulated
+sim_ops 188686648 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 132416 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 112256 # Number of bytes read from this memory
+system.physmem.bytes_read::total 244672 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 132416 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 132416 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 2069 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1754 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 3823 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1741856 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1476662 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3218518 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1741856 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1741856 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1741856 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1476662 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3218518 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -70,321 +70,320 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 152035425 # number of cpu cycles simulated
+system.cpu.numCycles 152040165 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 96736502 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 76001405 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 6554044 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 46407824 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 44181263 # Number of BTB hits
+system.cpu.BPredUnit.lookups 96858484 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 76060964 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 6563923 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 46433794 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 44260375 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 4475583 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 89477 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 40615724 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 388321121 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 96736502 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 48656846 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 82257766 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 28468285 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 7213696 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 8844 # Number of stall cycles due to pending traps
+system.cpu.BPredUnit.usedRAS 4475068 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 89115 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 40665802 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 388394971 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 96858484 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 48735443 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 82285186 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 28468460 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 7130109 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 7 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 9134 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.CacheLines 37645633 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1886253 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 151974828 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.798620 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.154172 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 37715921 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1893970 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 151978869 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.797548 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.152738 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 69887899 45.99% 45.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 5501348 3.62% 49.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 10684945 7.03% 56.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 10435662 6.87% 63.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 8784636 5.78% 69.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 6836908 4.50% 73.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 6295744 4.14% 77.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 8337493 5.49% 83.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 25210193 16.59% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 69866943 45.97% 45.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 5495765 3.62% 49.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 10729414 7.06% 56.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 10452168 6.88% 63.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 8790327 5.78% 69.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 6826108 4.49% 73.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 6308927 4.15% 77.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 8362057 5.50% 83.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 25147160 16.55% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 151974828 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.636276 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.554149 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 46658969 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 5920762 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 76552571 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1116980 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 21725546 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 14796577 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 162492 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 401466473 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 736417 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 21725546 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 52184597 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 714677 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 792157 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 72083528 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4474323 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 378974639 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 320673 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 3580560 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 14 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 642268895 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1614410837 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1596806412 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 17604425 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 298092667 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 344176228 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 52668 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 52665 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12854506 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 43974668 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 16894662 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 5833133 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 3767851 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 334792286 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 74530 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 252791404 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 896561 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 144952187 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 373840168 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 23248 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 151974828 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.663377 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.758905 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 151978869 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.637059 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.554555 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 46697521 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 5834788 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 76594287 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1116884 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 21735389 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 14843189 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 162820 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 401520259 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 676254 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 21735389 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 52210117 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 723485 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 695226 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 72137663 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4476989 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 379210260 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 320036 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 3584710 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 642738695 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1615361151 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1597815620 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 17545531 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 298092371 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 344646324 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 33437 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 33435 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12677945 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 44005038 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 16906133 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 5806665 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 3723076 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 335023972 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 55533 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 252928025 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 900898 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 145168889 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 374298631 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 4288 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 151978869 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.664232 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.759052 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 58489364 38.49% 38.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 23011540 15.14% 53.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 25193746 16.58% 70.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 20486028 13.48% 83.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12864515 8.46% 92.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 6577319 4.33% 96.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 4059001 2.67% 99.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1110893 0.73% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 182422 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 58441388 38.45% 38.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 23049169 15.17% 53.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 25167243 16.56% 70.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 20506081 13.49% 83.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12879623 8.47% 92.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 6582625 4.33% 96.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 4058401 2.67% 99.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1110608 0.73% 99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 183731 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 151974828 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 151978869 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 966666 37.58% 37.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 5596 0.22% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 136 0.01% 37.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 25 0.00% 37.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1199658 46.64% 84.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 400010 15.55% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 958151 37.34% 37.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 5590 0.22% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 95 0.00% 37.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 28 0.00% 37.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1196632 46.64% 84.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 405192 15.79% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 197331718 78.06% 78.06% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 995910 0.39% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 33152 0.01% 78.47% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.47% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 164284 0.06% 78.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 255235 0.10% 78.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 76457 0.03% 78.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 467994 0.19% 78.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 206483 0.08% 78.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 71867 0.03% 78.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 38997717 15.43% 94.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 14190267 5.61% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 197423347 78.06% 78.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 995576 0.39% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 33202 0.01% 78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 163925 0.06% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 254716 0.10% 78.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 76426 0.03% 78.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 467079 0.18% 78.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 206343 0.08% 78.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 71849 0.03% 78.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.95% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 39030082 15.43% 94.38% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 14205161 5.62% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 252791404 # Type of FU issued
-system.cpu.iq.rate 1.662714 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2572091 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010175 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 657257029 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 477588320 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 240562315 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 3769259 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 2249868 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 1852626 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 253473620 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1889875 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 2022881 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 252928025 # Type of FU issued
+system.cpu.iq.rate 1.663561 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2565688 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010144 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 657530631 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 478025695 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 240682393 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 3770874 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 2241416 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 1850793 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 253600335 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 1893378 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 2031332 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 14119118 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 17181 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 19942 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 4243962 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 14149525 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 17193 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 19478 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 4255470 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 21725546 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 15871 # Number of cycles IEW is blocking
+system.cpu.iew.iewSquashCycles 21735389 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 15851 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 654 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 334925114 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 838955 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 43974668 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 16894662 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 51980 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 159 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewDispatchedInsts 335097391 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 841360 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 44005038 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 16906133 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 32986 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 165 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 19942 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 4105078 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 3945464 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 8050542 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 245797206 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 37379001 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 6994198 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 19478 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4108816 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 3932770 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 8041586 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 245927260 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 37410682 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 7000765 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 58298 # number of nop insts executed
-system.cpu.iew.exec_refs 51189045 # number of memory reference insts executed
-system.cpu.iew.exec_branches 54004994 # Number of branches executed
-system.cpu.iew.exec_stores 13810044 # Number of stores executed
-system.cpu.iew.exec_rate 1.616710 # Inst execution rate
-system.cpu.iew.wb_sent 243546363 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 242414941 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 150055684 # num instructions producing a value
-system.cpu.iew.wb_consumers 269132262 # num instructions consuming a value
+system.cpu.iew.exec_nop 17886 # number of nop insts executed
+system.cpu.iew.exec_refs 51227779 # number of memory reference insts executed
+system.cpu.iew.exec_branches 54055496 # Number of branches executed
+system.cpu.iew.exec_stores 13817097 # Number of stores executed
+system.cpu.iew.exec_rate 1.617515 # Inst execution rate
+system.cpu.iew.wb_sent 243665877 # cumulative count of insts sent to commit
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-system.cpu.committedInsts_total 172333351 # Number of Instructions Simulated
-system.cpu.cpi 0.882217 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.882217 # CPI: Total CPI of All Threads
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-system.cpu.ipc_total 1.133508 # IPC: Total IPC of All Threads
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+system.cpu.cpi 0.882246 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.882246 # CPI: Total CPI of All Threads
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -393,246 +392,246 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.l2cache.ReadReq_accesses::total 5183 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 1081 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 1081 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 4400 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1864 # number of demand (read+write) accesses
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-system.cpu.l2cache.overall_accesses::cpu.data 1864 # number of overall (read+write) accesses
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.470000 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.885057 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.532703 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993525 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.993525 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.470000 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.947961 # miss rate for demand accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.470000 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.947961 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.612229 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35215.667311 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36657.287157 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 35577.508149 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34803.072626 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34803.072626 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35215.667311 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35530.277306 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 35360.625815 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35215.667311 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35530.277306 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 35360.625815 # average overall miss latency
+system.cpu.l2cache.overall_misses::total 3841 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 73125000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25174500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 98299500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 37623500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 37623500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 73125000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 62798000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 135923000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 73125000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 62798000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 135923000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 4406 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 775 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 5181 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1091 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1091 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 4406 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1866 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 6272 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 4406 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1866 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 6272 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.470722 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.883871 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.532523 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991751 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.991751 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.470722 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.946945 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.612404 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.470722 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.946945 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.612404 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35257.955641 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36751.094891 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 35628.669808 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34772.181146 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34772.181146 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35257.955641 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35539.332201 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 35387.399115 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35257.955641 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35539.332201 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 35387.399115 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -641,59 +640,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 14 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 20 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2062 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 679 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 13 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 18 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2069 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 672 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 2741 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1074 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 1074 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 2062 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 3815 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 2062 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 3815 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66124000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22800500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 88924500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33930000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33930000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66124000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 56730500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 122854500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66124000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 56730500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 122854500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.468636 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867178 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.528844 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993525 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993525 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.468636 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940451 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.609036 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.468636 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940451 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.609036 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32067.895247 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33579.528719 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32442.356804 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31592.178771 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31592.178771 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32067.895247 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32361.950941 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32203.014417 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32067.895247 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32361.950941 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32203.014417 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1082 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 1082 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2069 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1754 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 3823 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2069 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1754 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 3823 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66421500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22618000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 89039500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 34148500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 34148500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66421500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 56766500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 123188000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66421500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 56766500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 123188000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.469587 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867097 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.529048 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991751 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991751 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.469587 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.939979 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.609534 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.469587 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.939979 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.609534 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32103.189947 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33657.738095 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32484.312295 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31560.536044 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31560.536044 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32103.189947 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32364.025086 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32222.861627 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32103.189947 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32364.025086 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32222.861627 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
index 337b40f6d..0be27d977 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -48,7 +49,6 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
@@ -68,8 +68,8 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
+clock=1
+num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
@@ -84,8 +84,8 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
+clock=1
+num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
@@ -95,12 +95,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic
+cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
@@ -117,14 +117,15 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
index 887de4fb8..9558000b2 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
@@ -1,10 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 01:29:40
-gem5 executing on zizzer
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic
+gem5 compiled Sep 21 2012 11:19:00
+gem5 started Sep 21 2012 12:39:32
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic
+Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav
+Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index 0e78b9612..15db555ed 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.103107 # Nu
sim_ticks 103106766000 # Number of ticks simulated
final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3148564 # Simulator instruction rate (inst/s)
-host_op_rate 3447371 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1883953687 # Simulator tick rate (ticks/s)
-host_mem_usage 227464 # Number of bytes of host memory used
-host_seconds 54.73 # Real time elapsed on the host
+host_inst_rate 2085648 # Simulator instruction rate (inst/s)
+host_op_rate 2283582 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1247954818 # Simulator tick rate (ticks/s)
+host_mem_usage 222132 # Number of bytes of host memory used
+host_seconds 82.62 # Real time elapsed on the host
sim_insts 172317409 # Number of instructions simulated
sim_ops 188670891 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory
@@ -84,7 +84,7 @@ system.cpu.committedOps 188670891 # Nu
system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
system.cpu.num_func_calls 3545028 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 32493890 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls
system.cpu.num_int_insts 150106218 # number of integer instructions
system.cpu.num_fp_insts 1752310 # number of float instructions
system.cpu.num_int_register_reads 809396612 # number of times the integer registers were read
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
index e101e797a..a0628b862 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -47,7 +48,6 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
system=system
@@ -61,16 +61,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=1
forward_snoops=true
hash_delay=1
+hit_latency=1000
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=1000
size=262144
subblock_size=0
system=system
@@ -89,8 +91,8 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
+clock=1
+num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -99,16 +101,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=1
forward_snoops=true
hash_delay=1
+hit_latency=1000
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=1000
size=131072
subblock_size=0
system=system
@@ -130,8 +134,8 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
+clock=1
+num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -140,16 +144,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=1
forward_snoops=true
hash_delay=1
+hit_latency=10000
is_top_level=false
-latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=10000
size=2097152
subblock_size=0
system=system
@@ -176,12 +182,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing
+cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
@@ -199,13 +205,14 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
index fe3f7fc4c..6bb4ad05f 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
@@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 09:08:16
-gem5 started Jul 2 2012 17:03:03
-gem5 executing on zizzer
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing
-Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing/smred.sav
-Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing/smred.sv2
+gem5 compiled Sep 21 2012 11:19:00
+gem5 started Sep 21 2012 12:07:48
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
+Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav
+Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index 709a3b23f..ee5d7fbdb 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.232090 # Nu
sim_ticks 232089948000 # Number of ticks simulated
final_tick 232089948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1678684 # Simulator instruction rate (inst/s)
-host_op_rate 1838338 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2267224735 # Simulator tick rate (ticks/s)
-host_mem_usage 235976 # Number of bytes of host memory used
-host_seconds 102.37 # Real time elapsed on the host
+host_inst_rate 1108463 # Simulator instruction rate (inst/s)
+host_op_rate 1213886 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1497086914 # Simulator tick rate (ticks/s)
+host_mem_usage 230968 # Number of bytes of host memory used
+host_seconds 155.03 # Real time elapsed on the host
sim_insts 171842483 # Number of instructions simulated
sim_ops 188185920 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
@@ -78,7 +78,7 @@ system.cpu.committedOps 188185920 # Nu
system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
system.cpu.num_func_calls 3545028 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 32493890 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls
system.cpu.num_int_insts 150106218 # number of integer instructions
system.cpu.num_fp_insts 1752310 # number of float instructions
system.cpu.num_int_register_reads 898652246 # number of times the integer registers were read