diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
| commit | 8b4b1dcb86b0799a8c32056427581a8b6249a3bf (patch) | |
| tree | 96016b415513dc6c2c29877e1a76220e0edae629 /tests/long/se/70.twolf | |
| parent | a00383a40aeb8347af7e05f3966ab141484921a5 (diff) | |
| download | gem5-8b4b1dcb86b0799a8c32056427581a8b6249a3bf.tar.xz | |
stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM
controller.
Diffstat (limited to 'tests/long/se/70.twolf')
4 files changed, 2154 insertions, 2172 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 3f6e9d455..17c346b69 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041680 # Number of seconds simulated -sim_ticks 41680207000 # Number of ticks simulated -final_tick 41680207000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041684 # Number of seconds simulated +sim_ticks 41683573000 # Number of ticks simulated +final_tick 41683573000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131207 # Simulator instruction rate (inst/s) -host_op_rate 131207 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59505524 # Simulator tick rate (ticks/s) -host_mem_usage 234284 # Number of bytes of host memory used -host_seconds 700.44 # Real time elapsed on the host +host_inst_rate 119929 # Simulator instruction rate (inst/s) +host_op_rate 119929 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54395175 # Simulator tick rate (ticks/s) +host_mem_usage 269084 # Number of bytes of host memory used +host_seconds 766.31 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4290190 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3292114 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7582304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4290190 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4290190 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4290190 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3292114 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7582304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4289843 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3291848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7581692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4289843 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4289843 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4289843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3291848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7581692 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 4938 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 4938 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 41680133000 # Total gap between requests +system.physmem.totGap 41683192000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1090 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -154,65 +154,60 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 743 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 421.641992 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 209.527903 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 761.351186 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 254 34.19% 34.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 96 12.92% 47.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 62 8.34% 55.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 50 6.73% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 29 3.90% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 32 4.31% 70.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 22 2.96% 73.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 25 3.36% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 15 2.02% 78.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 12 1.62% 80.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 14 1.88% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 16 2.15% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 32 4.31% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 17 2.29% 90.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.67% 91.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 5 0.67% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 8 1.08% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 5 0.67% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 6 0.81% 94.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 6 0.81% 95.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.27% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 1 0.13% 96.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 1 0.13% 96.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 3 0.40% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 2 0.27% 96.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.13% 97.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.27% 97.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.27% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.13% 97.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 1 0.13% 97.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.13% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 1 0.13% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.13% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.13% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.13% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.13% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.13% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.13% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 1 0.13% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.13% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.13% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 1 0.13% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.13% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 1 0.13% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.13% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 743 # Bytes accessed per row activation -system.physmem.totQLat 34070750 # Total ticks spent queuing -system.physmem.totMemAccLat 126424500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 284 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 541.521127 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 335.427822 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.351632 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 58 20.42% 20.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 54 19.01% 39.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 24 8.45% 47.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12 4.23% 52.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 10 3.52% 55.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9 3.17% 58.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 1.76% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 1.76% 62.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 107 37.68% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 284 # Bytes accessed per row activation +system.physmem.totQLat 37971250 # Total ticks spent queuing +system.physmem.totMemAccLat 131493750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers -system.physmem.totBankLat 67663750 # Total ticks spent accessing banks -system.physmem.avgQLat 6899.71 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13702.66 # Average bank access latency per DRAM burst +system.physmem.totBankLat 68832500 # Total ticks spent accessing banks +system.physmem.avgQLat 7689.60 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13939.35 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25602.37 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26628.95 # Average memory access latency per DRAM burst system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s @@ -221,16 +216,16 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4195 # Number of row buffer hits during reads +system.physmem.readRowHits 4086 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.95 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.75 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8440691.17 # Average gap between requests -system.physmem.pageHitRate 84.95 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.90 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 7582304 # Throughput (bytes/s) +system.physmem.avgGap 8441310.65 # Average gap between requests +system.physmem.pageHitRate 82.75 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.04 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 7581692 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3216 # Transaction distribution system.membus.trans_dist::ReadResp 3216 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution @@ -241,9 +236,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 316032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 5775000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 5776500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 45973500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 45941000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 13412627 # Number of BP lookups @@ -259,18 +254,18 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996265 # DTB read hits +system.cpu.dtb.read_hits 19996264 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996275 # DTB read accesses -system.cpu.dtb.write_hits 6501862 # DTB write hits +system.cpu.dtb.read_accesses 19996274 # DTB read accesses +system.cpu.dtb.write_hits 6501866 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501885 # DTB write accesses -system.cpu.dtb.data_hits 26498127 # DTB hits +system.cpu.dtb.write_accesses 6501889 # DTB write accesses +system.cpu.dtb.data_hits 26498130 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498160 # DTB accesses +system.cpu.dtb.data_accesses 26498163 # DTB accesses system.cpu.itb.fetch_hits 9956950 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -288,18 +283,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83360415 # number of cpu cycles simulated +system.cpu.numCycles 83367147 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 5905662 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73570552 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 73570553 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136146024 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 136146025 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38521866 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 38521865 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 26722393 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken). @@ -310,12 +305,12 @@ system.cpu.execution_unit.executions 57404027 # Nu system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 82971123 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 82970332 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7752655 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75607760 # Number of cycles cpu stages are processed. -system.cpu.activity 90.699836 # Percentage of cycles cpu is active +system.cpu.timesIdled 10410 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7759392 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607755 # Number of cycles cpu stages are processed. +system.cpu.activity 90.692506 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -327,36 +322,36 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.907047 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.907121 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.907047 # CPI: Total CPI of All Threads -system.cpu.ipc 1.102478 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.907121 # CPI: Total CPI of All Threads +system.cpu.ipc 1.102389 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.102478 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27680069 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 55680346 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.794708 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34108732 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49251683 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 59.082819 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33509067 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49851348 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.802183 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65333914 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.624774 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29500658 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53859757 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.610711 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.102389 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27686803 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 55680344 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.789312 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34115467 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49251680 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 59.078044 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33515800 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49851347 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.797353 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65340657 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18026490 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.623014 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29507392 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53859755 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.605491 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 7635 # number of replacements -system.cpu.icache.tags.tagsinuse 1492.182806 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1492.188372 # Cycle average of tags in use system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1492.182806 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.728605 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.728605 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1492.188372 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.728608 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.728608 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1885 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id @@ -378,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst 11399 # n system.cpu.icache.demand_misses::total 11399 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11399 # number of overall misses system.cpu.icache.overall_misses::total 11399 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 325866750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 325866750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 325866750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 325866750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 325866750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 325866750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 329283500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 329283500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 329283500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 329283500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 329283500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 329283500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 9956950 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 9956950 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 9956950 # number of demand (read+write) accesses @@ -396,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28587.310290 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28587.310290 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28587.310290 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28587.310290 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28587.310290 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28587.310290 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28887.051496 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28887.051496 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28887.051496 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28887.051496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28887.051496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28887.051496 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -422,26 +417,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 9520 system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 266339500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 266339500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 266339500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 266339500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 266339500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 266339500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268822750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 268822750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268822750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 268822750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268822750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 268822750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27976.838235 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27976.838235 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27976.838235 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27976.838235 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27976.838235 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27976.838235 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28237.683824 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28237.683824 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28237.683824 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28237.683824 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28237.683824 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28237.683824 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 18195687 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 18194218 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution @@ -457,19 +452,19 @@ system.cpu.toL2Bus.data_through_bus 758400 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 14812000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 14800250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3559500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3515750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2189.577948 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2189.597840 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.842967 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.748644 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 350.986337 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.844631 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.766792 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 350.986416 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055565 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy @@ -507,17 +502,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189282000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32395250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 221677250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122425750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 122425750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 189282000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 154821000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 344103000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 189282000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 154821000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 344103000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191765250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32319750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 224085000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 125611500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 125611500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 191765250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 157931250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 349696500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 191765250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 157931250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 349696500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) @@ -542,17 +537,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67745.884037 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76765.995261 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68929.493159 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71095.092915 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71095.092915 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67745.884037 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.287313 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69684.690158 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67745.884037 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.287313 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69684.690158 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68634.663565 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76587.085308 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69678.171642 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72945.121951 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72945.121951 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68634.663565 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73661.963619 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70817.436209 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68634.663565 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73661.963619 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70817.436209 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -572,17 +567,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154136500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27132250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 181268750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101289750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101289750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 154136500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128422000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 282558500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 154136500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128422000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 282558500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156642750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27057250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 183700000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 104540000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 104540000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 156642750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131597250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 288240000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 156642750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131597250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 288240000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses @@ -594,31 +589,31 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55166.964925 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64294.431280 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56364.661070 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58820.993031 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58820.993031 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59898.320896 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57221.243418 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59898.320896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57221.243418 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56063.976378 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64116.706161 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57120.646766 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60708.478513 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60708.478513 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.976378 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61379.314366 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58371.810450 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.976378 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61379.314366 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58371.810450 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1441.367780 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26488450 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1441.382253 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26488456 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11915.632029 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11915.634728 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1441.367780 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.351896 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.351896 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.382253 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.351900 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.351900 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 403 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id @@ -626,28 +621,28 @@ system.cpu.dcache.tags.tag_accesses 52996825 # Nu system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 19995621 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995621 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492829 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492829 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26488450 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26488450 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26488450 # number of overall hits -system.cpu.dcache.overall_hits::total 26488450 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492835 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492835 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488456 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488456 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488456 # number of overall hits +system.cpu.dcache.overall_hits::total 26488456 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 577 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 577 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8274 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8274 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 8851 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8851 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8851 # number of overall misses -system.cpu.dcache.overall_misses::total 8851 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 41023250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 41023250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 492650500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 492650500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 533673750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 533673750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 533673750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 533673750 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 8268 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8268 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8845 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8845 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8845 # number of overall misses +system.cpu.dcache.overall_misses::total 8845 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40979500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40979500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 507652000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 507652000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 548631500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 548631500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 548631500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 548631500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -658,25 +653,25 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301 system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001273 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001273 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001272 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001272 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71097.487002 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71097.487002 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59541.999033 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59541.999033 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60295.305615 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60295.305615 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60295.305615 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60295.305615 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23884 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71021.663778 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71021.663778 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61399.612966 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61399.612966 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62027.303561 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62027.303561 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62027.303561 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62027.303561 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 25755 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 841 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 844 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.399524 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.515403 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -684,12 +679,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 102 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6526 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6526 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6628 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6628 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6628 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6628 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6520 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6520 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6622 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6622 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6622 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6622 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -698,14 +693,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33418750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33418750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124443250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 124443250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 157862000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 157862000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157862000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 157862000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33343250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33343250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127629000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 127629000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160972250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 160972250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 160972250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 160972250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -714,14 +709,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70355.263158 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70355.263158 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71191.790618 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71191.790618 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71013.045434 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71013.045434 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71013.045434 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71013.045434 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70196.315789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70196.315789 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73014.302059 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73014.302059 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72412.168241 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72412.168241 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72412.168241 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72412.168241 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index b0acaf58e..c3a9e9ab9 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023462 # Number of seconds simulated -sim_ticks 23461709500 # Number of ticks simulated -final_tick 23461709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023455 # Number of seconds simulated +sim_ticks 23455364500 # Number of ticks simulated +final_tick 23455364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186682 # Simulator instruction rate (inst/s) -host_op_rate 186682 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52030153 # Simulator tick rate (ticks/s) -host_mem_usage 235304 # Number of bytes of host memory used -host_seconds 450.93 # Real time elapsed on the host +host_inst_rate 164985 # Simulator instruction rate (inst/s) +host_op_rate 164985 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45970553 # Simulator tick rate (ticks/s) +host_mem_usage 272156 # Number of bytes of host memory used +host_seconds 510.23 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 195968 # Nu system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8352674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5908521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14261194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8352674 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8352674 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8352674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5908521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14261194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 8354933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5910119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14265052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8354933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8354933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8354933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5910119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14265052 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5228 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5228 # Number of DRAM read bursts, including those serviced by the write queue @@ -41,20 +41,20 @@ system.physmem.bytesWrittenSys 0 # To system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 466 # Per bank write bursts +system.physmem.perBankRdBursts::0 469 # Per bank write bursts system.physmem.perBankRdBursts::1 290 # Per bank write bursts -system.physmem.perBankRdBursts::2 300 # Per bank write bursts -system.physmem.perBankRdBursts::3 524 # Per bank write bursts +system.physmem.perBankRdBursts::2 301 # Per bank write bursts +system.physmem.perBankRdBursts::3 519 # Per bank write bursts system.physmem.perBankRdBursts::4 220 # Per bank write bursts -system.physmem.perBankRdBursts::5 226 # Per bank write bursts -system.physmem.perBankRdBursts::6 219 # Per bank write bursts +system.physmem.perBankRdBursts::5 227 # Per bank write bursts +system.physmem.perBankRdBursts::6 220 # Per bank write bursts system.physmem.perBankRdBursts::7 288 # Per bank write bursts -system.physmem.perBankRdBursts::8 240 # Per bank write bursts -system.physmem.perBankRdBursts::9 279 # Per bank write bursts +system.physmem.perBankRdBursts::8 236 # Per bank write bursts +system.physmem.perBankRdBursts::9 278 # Per bank write bursts system.physmem.perBankRdBursts::10 248 # Per bank write bursts -system.physmem.perBankRdBursts::11 254 # Per bank write bursts -system.physmem.perBankRdBursts::12 400 # Per bank write bursts -system.physmem.perBankRdBursts::13 336 # Per bank write bursts +system.physmem.perBankRdBursts::11 255 # Per bank write bursts +system.physmem.perBankRdBursts::12 401 # Per bank write bursts +system.physmem.perBankRdBursts::13 338 # Per bank write bursts system.physmem.perBankRdBursts::14 491 # Per bank write bursts system.physmem.perBankRdBursts::15 447 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 23461582500 # Total gap between requests +system.physmem.totGap 23455237500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 84 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -154,84 +154,78 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 750 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 442.026667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 206.409345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 807.667918 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 266 35.47% 35.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 111 14.80% 50.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 59 7.87% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 40 5.33% 63.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 26 3.47% 66.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 30 4.00% 70.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 24 3.20% 74.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 16 2.13% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 9 1.20% 77.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 13 1.73% 79.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 15 2.00% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 13 1.73% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 37 4.93% 87.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 11 1.47% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 6 0.80% 90.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 3 0.40% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 7 0.93% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 7 0.93% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 3 0.40% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.40% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 8 1.07% 94.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 1 0.13% 94.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3 0.40% 94.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 2 0.27% 95.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 4 0.53% 95.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 2 0.27% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.13% 96.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.13% 96.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.40% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.40% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.13% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 3 0.40% 97.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.13% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.13% 97.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 3 0.40% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.13% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.13% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 2 0.27% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 1 0.13% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.13% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.13% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.13% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.13% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.13% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.13% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.27% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 750 # Bytes accessed per row activation -system.physmem.totQLat 37518750 # Total ticks spent queuing -system.physmem.totMemAccLat 134402500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 339 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.348083 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 311.933424 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 425.197716 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 81 23.89% 23.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 64 18.88% 42.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 21 6.19% 48.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 17 5.01% 53.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 9 2.65% 56.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8 2.36% 59.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 2.06% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 0.88% 61.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 129 38.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 339 # Bytes accessed per row activation +system.physmem.totQLat 42838250 # Total ticks spent queuing +system.physmem.totMemAccLat 141220750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers -system.physmem.totBankLat 70743750 # Total ticks spent accessing banks -system.physmem.avgQLat 7176.50 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13531.70 # Average bank access latency per DRAM burst +system.physmem.totBankLat 72242500 # Total ticks spent accessing banks +system.physmem.avgQLat 8194.00 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13818.38 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25708.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27012.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.26 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.27 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.11 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4478 # Number of row buffer hits during reads +system.physmem.readRowHits 4346 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.65 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.13 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4487678.37 # Average gap between requests -system.physmem.pageHitRate 85.65 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.19 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 14261194 # Throughput (bytes/s) +system.physmem.avgGap 4486464.71 # Average gap between requests +system.physmem.pageHitRate 83.13 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.10 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 14265052 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3523 # Transaction distribution system.membus.trans_dist::ReadResp 3523 # Transaction distribution system.membus.trans_dist::ReadExReq 1705 # Transaction distribution @@ -242,40 +236,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 334592 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6831000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6760500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 49012250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 48963750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14847721 # Number of BP lookups -system.cpu.branchPred.condPredicted 10774921 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 922205 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8301784 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6957680 # Number of BTB hits +system.cpu.branchPred.lookups 14848335 # Number of BP lookups +system.cpu.branchPred.condPredicted 10770516 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 922016 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8296689 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6955595 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.809456 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1467978 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3097 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 83.835793 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1468520 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3112 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23117785 # DTB read hits -system.cpu.dtb.read_misses 192281 # DTB read misses +system.cpu.dtb.read_hits 23116922 # DTB read hits +system.cpu.dtb.read_misses 193562 # DTB read misses system.cpu.dtb.read_acv 4 # DTB read access violations -system.cpu.dtb.read_accesses 23310066 # DTB read accesses -system.cpu.dtb.write_hits 7068175 # DTB write hits -system.cpu.dtb.write_misses 1137 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 7069312 # DTB write accesses -system.cpu.dtb.data_hits 30185960 # DTB hits -system.cpu.dtb.data_misses 193418 # DTB misses -system.cpu.dtb.data_acv 8 # DTB access violations -system.cpu.dtb.data_accesses 30379378 # DTB accesses -system.cpu.itb.fetch_hits 14734161 # ITB hits -system.cpu.itb.fetch_misses 103 # ITB misses +system.cpu.dtb.read_accesses 23310484 # DTB read accesses +system.cpu.dtb.write_hits 7068693 # DTB write hits +system.cpu.dtb.write_misses 1118 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 7069811 # DTB write accesses +system.cpu.dtb.data_hits 30185615 # DTB hits +system.cpu.dtb.data_misses 194680 # DTB misses +system.cpu.dtb.data_acv 6 # DTB access violations +system.cpu.dtb.data_accesses 30380295 # DTB accesses +system.cpu.itb.fetch_hits 14732180 # ITB hits +system.cpu.itb.fetch_misses 100 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14734264 # ITB accesses +system.cpu.itb.fetch_accesses 14732280 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -289,139 +283,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46923420 # number of cpu cycles simulated +system.cpu.numCycles 46910730 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15463381 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 126961894 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14847721 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8425658 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22130056 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4473003 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5559398 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2205 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14734161 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 324644 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46671603 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.720324 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.376096 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15458006 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 126949517 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14848335 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8424115 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22129467 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4471319 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5547804 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2176 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14732180 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 325492 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46652781 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.721156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.376288 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24541547 52.58% 52.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2361252 5.06% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1192515 2.56% 60.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1742111 3.73% 63.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2755701 5.90% 69.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1149393 2.46% 72.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1220691 2.62% 74.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 771780 1.65% 76.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10936613 23.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24523314 52.57% 52.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2362460 5.06% 57.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1191709 2.55% 60.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1744531 3.74% 63.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2756035 5.91% 69.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1149513 2.46% 72.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1216156 2.61% 74.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 771099 1.65% 76.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10937964 23.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46671603 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316425 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.705725 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17289395 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4257221 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20524693 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1095542 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3504752 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2511898 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12167 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 123979126 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31595 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3504752 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18431780 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 963421 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7928 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20455398 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3308324 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121154570 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 87 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 400162 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2430153 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 88974225 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157440425 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 150394655 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7045769 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46652781 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316523 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.706194 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17279755 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4249359 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20525557 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1094653 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3503457 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2516236 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12079 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 123971467 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32460 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3503457 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18421615 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 960025 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8092 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20456033 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3303559 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 121144333 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 76 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 398869 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2427038 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 88958437 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157404324 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 150359413 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7044910 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20546864 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 749 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 744 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8783261 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25363133 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8241349 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2569635 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 893782 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105438334 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 961 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96565072 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178504 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20784578 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15622466 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 572 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46671603 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.069033 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.876517 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 20531076 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 753 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 746 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8762869 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25364686 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8245053 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2579677 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 916866 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105436349 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1901 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96572685 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 177506 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20788885 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15603704 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1512 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46652781 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.070031 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.877189 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12133902 26.00% 26.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9340972 20.01% 46.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8404137 18.01% 64.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6285068 13.47% 77.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4921137 10.54% 88.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2853571 6.11% 94.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1727806 3.70% 97.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 798697 1.71% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 206313 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12130850 26.00% 26.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9330795 20.00% 46.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8389374 17.98% 63.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6281972 13.47% 77.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4924466 10.56% 88.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2864469 6.14% 94.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1724344 3.70% 97.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 801135 1.72% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 205376 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46671603 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46652781 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 187905 11.99% 11.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 187827 11.99% 11.99% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 11.99% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 11.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 198 0.01% 12.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7114 0.45% 12.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5683 0.36% 12.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843073 53.81% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 444038 28.34% 94.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78699 5.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 195 0.01% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7087 0.45% 12.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5615 0.36% 12.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 842803 53.78% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 445934 28.46% 95.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77665 4.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58732393 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479878 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58739096 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 479860 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2798409 2.90% 64.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115272 0.12% 64.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2387143 2.47% 66.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 310920 0.32% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 760028 0.79% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2798014 2.90% 64.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115391 0.12% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2386555 2.47% 66.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 310970 0.32% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759904 0.79% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued @@ -443,84 +437,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23829441 24.68% 92.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7151262 7.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23830824 24.68% 92.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7151745 7.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96565072 # Type of FU issued -system.cpu.iq.rate 2.057929 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1566710 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016224 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226434513 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117518300 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87069210 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15112448 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8740080 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7062492 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90145382 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7986393 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1518186 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96572685 # Type of FU issued +system.cpu.iq.rate 2.058648 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1567126 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016227 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 226432918 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117523015 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87074868 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15109865 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8738386 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7061397 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90154911 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7984893 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1517468 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5366935 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18425 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34629 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1740246 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5368488 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18513 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34393 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1743950 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10551 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2023 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10556 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2089 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3504752 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 133474 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18356 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115674265 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 366324 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25363133 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8241349 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 961 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2994 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3503457 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 134155 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17977 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115673905 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 371989 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25364686 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8245053 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1901 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2671 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 35 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34629 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 535207 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 494157 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1029364 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95337689 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23310553 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1227383 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 34393 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 533358 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 495038 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1028396 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95341973 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23310954 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1230712 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10234970 # number of nop insts executed -system.cpu.iew.exec_refs 30380075 # number of memory reference insts executed -system.cpu.iew.exec_branches 12022158 # Number of branches executed -system.cpu.iew.exec_stores 7069522 # Number of stores executed -system.cpu.iew.exec_rate 2.031772 # Inst execution rate -system.cpu.iew.wb_sent 94652012 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94131702 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64474346 # num instructions producing a value -system.cpu.iew.wb_consumers 89850691 # num instructions consuming a value +system.cpu.iew.exec_nop 10235655 # number of nop insts executed +system.cpu.iew.exec_refs 30380968 # number of memory reference insts executed +system.cpu.iew.exec_branches 12023807 # Number of branches executed +system.cpu.iew.exec_stores 7070014 # Number of stores executed +system.cpu.iew.exec_rate 2.032413 # Inst execution rate +system.cpu.iew.wb_sent 94656410 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94136265 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64475750 # num instructions producing a value +system.cpu.iew.wb_consumers 89852391 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.006071 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717572 # average fanout of values written-back +system.cpu.iew.wb_rate 2.006711 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717574 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23772316 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23771863 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 910471 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43166851 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.129019 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.746086 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 910264 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43149324 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.129884 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.746526 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16723468 38.74% 38.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9908468 22.95% 61.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4486822 10.39% 72.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2263317 5.24% 77.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1605459 3.72% 81.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1122723 2.60% 83.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 719573 1.67% 85.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 818065 1.90% 87.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5518956 12.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16704227 38.71% 38.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9920088 22.99% 61.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4481212 10.39% 72.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2253745 5.22% 77.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1606057 3.72% 81.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1123881 2.60% 83.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 722151 1.67% 85.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 820935 1.90% 87.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5517028 12.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43166851 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43149324 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -531,173 +525,173 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5518956 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5517028 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153322226 # The number of ROB reads -system.cpu.rob.rob_writes 234879469 # The number of ROB writes -system.cpu.timesIdled 5401 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 251817 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 153306174 # The number of ROB reads +system.cpu.rob.rob_writes 234877097 # The number of ROB writes +system.cpu.timesIdled 5272 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 257949 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.557420 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.557420 # CPI: Total CPI of All Threads -system.cpu.ipc 1.793981 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.793981 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129048096 # number of integer regfile reads -system.cpu.int_regfile_writes 70519803 # number of integer regfile writes -system.cpu.fp_regfile_reads 6188545 # number of floating regfile reads -system.cpu.fp_regfile_writes 6044303 # number of floating regfile writes -system.cpu.misc_regfile_reads 714547 # number of misc regfile reads +system.cpu.cpi 0.557269 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.557269 # CPI: Total CPI of All Threads +system.cpu.ipc 1.794466 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.794466 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129050731 # number of integer regfile reads +system.cpu.int_regfile_writes 70522819 # number of integer regfile writes +system.cpu.fp_regfile_reads 6187407 # number of floating regfile reads +system.cpu.fp_regfile_writes 6043154 # number of floating regfile writes +system.cpu.misc_regfile_reads 714454 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 37824354 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 12026 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 12026 # Transaction distribution +system.cpu.toL2Bus.throughput 37351626 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 11849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 11849 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22666 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27623 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 736640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27269 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 725312 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 876096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 876096 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 7042000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 6953500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17847250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17562000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3547000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3539750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 9576 # number of replacements -system.cpu.icache.tags.tagsinuse 1596.482984 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14719872 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11510 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1278.876803 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9398 # number of replacements +system.cpu.icache.tags.tagsinuse 1599.250917 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14718111 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11333 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1298.695050 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1596.482984 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.779533 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.779533 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1934 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 766 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1599.250917 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.780884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.780884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1935 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 761 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 924 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.944336 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 29479830 # Number of tag accesses -system.cpu.icache.tags.data_accesses 29479830 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 14719872 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14719872 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14719872 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14719872 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14719872 # number of overall hits -system.cpu.icache.overall_hits::total 14719872 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14288 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14288 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14288 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14288 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14288 # number of overall misses -system.cpu.icache.overall_misses::total 14288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 413271500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 413271500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 413271500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 413271500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 413271500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 413271500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14734160 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14734160 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14734160 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14734160 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14734160 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14734160 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000970 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000970 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000970 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000970 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000970 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000970 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28924.377100 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28924.377100 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28924.377100 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28924.377100 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28924.377100 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28924.377100 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::4 929 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.944824 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 29475691 # Number of tag accesses +system.cpu.icache.tags.data_accesses 29475691 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 14718111 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14718111 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14718111 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14718111 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14718111 # number of overall hits +system.cpu.icache.overall_hits::total 14718111 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14068 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14068 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14068 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14068 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14068 # number of overall misses +system.cpu.icache.overall_misses::total 14068 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 413989500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 413989500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 413989500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 413989500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 413989500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 413989500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14732179 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14732179 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14732179 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14732179 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14732179 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14732179 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000955 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000955 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000955 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000955 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000955 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000955 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29427.743816 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29427.743816 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29427.743816 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29427.743816 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29427.743816 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29427.743816 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 165 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 68.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 41.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2778 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2778 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2778 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2778 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2778 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2778 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11510 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11510 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11510 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11510 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11510 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303668250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 303668250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303668250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 303668250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303668250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 303668250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000781 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000781 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000781 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26382.993050 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26382.993050 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26382.993050 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26382.993050 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26382.993050 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26382.993050 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2735 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2735 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2735 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2735 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2735 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2735 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11333 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11333 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11333 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11333 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11333 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11333 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305304500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 305304500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305304500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 305304500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305304500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 305304500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000769 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000769 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000769 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000769 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000769 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000769 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26939.424689 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26939.424689 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26939.424689 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26939.424689 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26939.424689 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26939.424689 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2409.583505 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8517 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2413.657208 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8341 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3590 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.372423 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.323398 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.678720 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2010.447963 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 381.456822 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061354 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011641 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.073535 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 17.675331 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2012.279201 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 383.702676 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061410 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011710 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.073659 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3590 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 910 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 904 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2435 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109558 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 116249 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 116249 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 8448 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 114833 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 114833 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 8271 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 8503 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 8326 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 109 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 109 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8448 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 8271 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 81 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 8529 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8448 # number of overall hits +system.cpu.l2cache.demand_hits::total 8352 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8271 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 81 # number of overall hits -system.cpu.l2cache.overall_hits::total 8529 # number of overall hits +system.cpu.l2cache.overall_hits::total 8352 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3062 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 461 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 3523 # number of ReadReq misses @@ -709,52 +703,52 @@ system.cpu.l2cache.demand_misses::total 5228 # nu system.cpu.l2cache.overall_misses::cpu.inst 3062 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2166 # number of overall misses system.cpu.l2cache.overall_misses::total 5228 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207668250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34560750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 242229000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 124310250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 124310250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 207668250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 158871000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 366539250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 207668250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 158871000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 366539250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 11510 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 211253500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 36622500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 247876000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 125606750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 125606750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 211253500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 162229250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 373482750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 211253500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 162229250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 373482750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 11333 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 516 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 12026 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 11849 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 109 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 109 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1731 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1731 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 11510 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 11333 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2247 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 13757 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 11510 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 13580 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 11333 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2247 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 13757 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.266030 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 13580 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.270184 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.893411 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.292949 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.297325 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984980 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.984980 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.266030 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.270184 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.963952 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.380025 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266030 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.384978 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.270184 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963952 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.380025 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67821.113651 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74969.088937 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68756.457565 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72909.237537 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72909.237537 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67821.113651 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73347.645429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70110.797628 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67821.113651 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73347.645429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70110.797628 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.384978 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68991.998694 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79441.431670 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70359.352824 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73669.648094 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73669.648094 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68991.998694 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74898.084026 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71438.934583 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68991.998694 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74898.084026 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71438.934583 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -774,135 +768,136 @@ system.cpu.l2cache.demand_mshr_misses::total 5228 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2166 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168834750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 28858250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197693000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 103390750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 103390750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168834750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132249000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 301083750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168834750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132249000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 301083750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 172480500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30915000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 203395500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 104707750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 104707750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 172480500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 135622750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 308103250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 172480500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 135622750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 308103250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270184 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893411 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.292949 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.297325 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984980 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984980 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.270184 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.380025 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.384978 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.270184 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.380025 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55138.716525 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62599.240781 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56114.958842 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60639.736070 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60639.736070 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55138.716525 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61056.786704 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57590.617827 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55138.716525 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61056.786704 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57590.617827 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.384978 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56329.359895 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67060.737527 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57733.607721 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61412.170088 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61412.170088 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56329.359895 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62614.381348 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58933.291890 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56329.359895 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62614.381348 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58933.291890 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 159 # number of replacements -system.cpu.dcache.tags.tagsinuse 1459.152638 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28079168 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1460.308394 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28078942 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2247 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12496.291945 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12496.191366 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1459.152638 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.356238 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.356238 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1460.308394 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.356521 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.356521 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1391 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 56179001 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 56179001 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21586035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21586035 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492869 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492869 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 264 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 264 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28078904 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28078904 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28078904 # number of overall hits -system.cpu.dcache.overall_hits::total 28078904 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 974 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 974 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8234 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8234 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 56178581 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 56178581 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21585827 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21585827 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492868 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492868 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 247 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 247 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28078695 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28078695 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28078695 # number of overall hits +system.cpu.dcache.overall_hits::total 28078695 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 989 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 989 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8235 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8235 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9208 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9208 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9208 # number of overall misses -system.cpu.dcache.overall_misses::total 9208 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58289250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58289250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 505816795 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 505816795 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9224 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9224 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9224 # number of overall misses +system.cpu.dcache.overall_misses::total 9224 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64012750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64012750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 517866286 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 517866286 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 564106045 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 564106045 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 564106045 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 564106045 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21587009 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21587009 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 581879036 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 581879036 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 581879036 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 581879036 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21586816 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21586816 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 265 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 265 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28088112 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28088112 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28088112 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28088112 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28087919 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28087919 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28087919 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28087919 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001267 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001267 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003774 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003774 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004032 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004032 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59845.225873 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59845.225873 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61430.264149 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61430.264149 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64724.721941 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64724.721941 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62886.009229 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62886.009229 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61262.602628 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61262.602628 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61262.602628 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61262.602628 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24052 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63083.156548 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63083.156548 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63083.156548 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63083.156548 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24818 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 336 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 346 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 71.583333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 71.728324 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 109 # number of writebacks system.cpu.dcache.writebacks::total 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 459 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6503 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6503 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6962 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6962 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6962 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6962 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 474 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 474 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6504 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6504 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6978 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6978 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6978 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6978 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses @@ -913,36 +908,36 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2246 system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35552000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 35552000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126441497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 126441497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37612750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37612750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127737997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 127737997 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161993497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161993497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161993497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161993497 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165350747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 165350747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 165350747 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 165350747 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003774 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003774 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004032 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004032 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69033.009709 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69033.009709 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73045.347776 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73045.347776 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73034.466019 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73034.466019 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73794.336800 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73794.336800 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72125.332591 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72125.332591 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72125.332591 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72125.332591 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73620.101069 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73620.101069 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73620.101069 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73620.101069 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index a1592fc7b..975655111 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074220 # Number of seconds simulated -sim_ticks 74219931000 # Number of ticks simulated -final_tick 74219931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074212 # Number of seconds simulated +sim_ticks 74211770500 # Number of ticks simulated +final_tick 74211770500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128899 # Simulator instruction rate (inst/s) -host_op_rate 141133 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55523526 # Simulator tick rate (ticks/s) -host_mem_usage 273064 # Number of bytes of host memory used -host_seconds 1336.73 # Real time elapsed on the host +host_inst_rate 109728 # Simulator instruction rate (inst/s) +host_op_rate 120142 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47260193 # Simulator tick rate (ticks/s) +host_mem_usage 316324 # Number of bytes of host memory used +host_seconds 1570.28 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory -system.physmem.bytes_read::total 242752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112000 # Number of bytes read from this memory +system.physmem.bytes_read::total 243072 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 131072 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 131072 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 2048 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1745 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3793 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1765995 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1504717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3270712 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1765995 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1765995 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1765995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1504717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3270712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3794 # Number of read requests accepted +system.physmem.num_reads::cpu.data 1750 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3798 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1766189 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1509195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3275383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1766189 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1766189 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1766189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1509195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3275383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3799 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3794 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3799 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 242816 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 243136 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 242816 # Total read bytes from the system interface side +system.physmem.bytesReadSys 243136 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 306 # Per bank write bursts system.physmem.perBankRdBursts::1 215 # Per bank write bursts -system.physmem.perBankRdBursts::2 133 # Per bank write bursts +system.physmem.perBankRdBursts::2 132 # Per bank write bursts system.physmem.perBankRdBursts::3 308 # Per bank write bursts system.physmem.perBankRdBursts::4 298 # Per bank write bursts system.physmem.perBankRdBursts::5 299 # Per bank write bursts -system.physmem.perBankRdBursts::6 264 # Per bank write bursts -system.physmem.perBankRdBursts::7 216 # Per bank write bursts +system.physmem.perBankRdBursts::6 265 # Per bank write bursts +system.physmem.perBankRdBursts::7 218 # Per bank write bursts system.physmem.perBankRdBursts::8 246 # Per bank write bursts -system.physmem.perBankRdBursts::9 215 # Per bank write bursts +system.physmem.perBankRdBursts::9 214 # Per bank write bursts system.physmem.perBankRdBursts::10 289 # Per bank write bursts -system.physmem.perBankRdBursts::11 193 # Per bank write bursts -system.physmem.perBankRdBursts::12 189 # Per bank write bursts -system.physmem.perBankRdBursts::13 206 # Per bank write bursts -system.physmem.perBankRdBursts::14 217 # Per bank write bursts +system.physmem.perBankRdBursts::11 192 # Per bank write bursts +system.physmem.perBankRdBursts::12 190 # Per bank write bursts +system.physmem.perBankRdBursts::13 208 # Per bank write bursts +system.physmem.perBankRdBursts::14 219 # Per bank write bursts system.physmem.perBankRdBursts::15 200 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 74219912500 # Total gap between requests +system.physmem.totGap 74211752000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3794 # Read request sizes (log2) +system.physmem.readPktSize::6 3799 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2838 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 780 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 138 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -154,101 +154,102 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 334.192469 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.652659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 576.534776 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 257 35.84% 35.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 120 16.74% 52.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 71 9.90% 62.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 49 6.83% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 19 2.65% 71.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 26 3.63% 75.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 20 2.79% 78.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 17 2.37% 80.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 17 2.37% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 40 5.58% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 17 2.37% 91.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 6 0.84% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 6 0.84% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 1.12% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 6 0.84% 94.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 5 0.70% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 4 0.56% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1 0.14% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.28% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.28% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.28% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 2 0.28% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 1 0.14% 97.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 1 0.14% 97.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 1 0.14% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.14% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.14% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.28% 98.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 1 0.14% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 2 0.28% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.14% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.14% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.14% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 1 0.14% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.14% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 1 0.14% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 1 0.14% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.14% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.14% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1 0.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation -system.physmem.totQLat 25208000 # Total ticks spent queuing -system.physmem.totMemAccLat 100718000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 18970000 # Total ticks spent in databus transfers -system.physmem.totBankLat 56540000 # Total ticks spent accessing banks -system.physmem.avgQLat 6644.18 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14902.48 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 398.476190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 217.440190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 401.372897 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 87 34.52% 34.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 58 23.02% 57.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 17 6.75% 64.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 1.98% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 2.78% 69.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8 3.17% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 1.59% 73.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 1.19% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 63 25.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 252 # Bytes accessed per row activation +system.physmem.totQLat 23847500 # Total ticks spent queuing +system.physmem.totMemAccLat 100702500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 18995000 # Total ticks spent in databus transfers +system.physmem.totBankLat 57860000 # Total ticks spent accessing banks +system.physmem.avgQLat 6277.31 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15230.32 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26546.65 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26507.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.27 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.28 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3077 # Number of row buffer hits during reads +system.physmem.readRowHits 3018 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.10 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19562443.99 # Average gap between requests -system.physmem.pageHitRate 81.10 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.24 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 3270712 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 2723 # Transaction distribution -system.membus.trans_dist::ReadResp 2722 # Transaction distribution +system.physmem.avgGap 19534549.09 # Average gap between requests +system.physmem.pageHitRate 79.44 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.21 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 3275383 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2728 # Transaction distribution +system.membus.trans_dist::ReadResp 2727 # Transaction distribution system.membus.trans_dist::ReadExReq 1071 # Transaction distribution system.membus.trans_dist::ReadExResp 1071 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7587 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7587 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 242752 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 242752 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 242752 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7597 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7597 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243072 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 243072 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 243072 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4681000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4687500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35532250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35592500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 94784239 # Number of BP lookups -system.cpu.branchPred.condPredicted 74783977 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6281559 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44678373 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43049971 # Number of BTB hits +system.cpu.branchPred.lookups 94795806 # Number of BP lookups +system.cpu.branchPred.condPredicted 74795654 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6279989 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 44691885 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43051051 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.355279 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4356641 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88400 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.328564 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4354918 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 88426 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -334,135 +335,135 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148439863 # number of cpu cycles simulated +system.cpu.numCycles 148423542 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39656875 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380179667 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94784239 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47406612 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80370607 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27283097 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7220794 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6206 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 39654967 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380195915 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94795806 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47405969 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80368300 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27279262 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7212539 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5988 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36850851 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1831977 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148240291 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.801605 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.152871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 36848695 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1833193 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148225221 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.802047 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.153051 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68038529 45.90% 45.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5265458 3.55% 49.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10540663 7.11% 56.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10285699 6.94% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8660453 5.84% 69.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6545120 4.42% 73.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6246377 4.21% 77.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8002820 5.40% 83.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24655172 16.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68026374 45.89% 45.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5263091 3.55% 49.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10536182 7.11% 56.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10285653 6.94% 63.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8660137 5.84% 69.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6544581 4.42% 73.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6243734 4.21% 77.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8007959 5.40% 83.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24657510 16.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148240291 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.638536 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.561170 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45513767 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5886575 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74804066 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1203498 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20832385 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14327909 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164350 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392779624 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 733803 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20832385 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50900716 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 730751 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 603183 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70558259 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4614997 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371307860 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 42 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 339068 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3661204 # Number of times rename has blocked due to LSQ full +system.cpu.fetch.rateDist::total 148225221 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.638684 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.561561 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45510679 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5881311 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74801618 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1201370 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20830243 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14327753 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164034 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392767808 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 749358 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20830243 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50895494 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 723680 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 602483 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70555782 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4617539 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371309891 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 37 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 338990 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3664355 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 25 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631703204 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1588513521 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1506815662 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3203425 # Number of floating rename lookups +system.cpu.rename.RenamedOperands 631718613 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1588504211 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1506839397 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3198087 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333659065 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25072 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25068 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13010227 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43012674 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16416368 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5733538 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3666489 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329189946 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 47154 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249456447 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 789359 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139503196 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362394637 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1938 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148240291 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.682784 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761427 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 333674474 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25005 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25002 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13030816 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43005440 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16429294 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5701095 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3639070 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329189812 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 47090 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 249460239 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 787524 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139505237 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362363758 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1874 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148225221 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.682981 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761692 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56059626 37.82% 37.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22638758 15.27% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24824129 16.75% 69.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20343397 13.72% 83.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12534810 8.46% 92.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6516110 4.40% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4026087 2.72% 99.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1116064 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181310 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56054819 37.82% 37.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22642547 15.28% 53.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24806201 16.74% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20327492 13.71% 83.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12550892 8.47% 92.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6518173 4.40% 96.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4029511 2.72% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1113373 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 182213 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148240291 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148225221 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 965209 38.57% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5593 0.22% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1158969 46.31% 85.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 372730 14.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 964965 38.34% 38.34% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5593 0.22% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 99 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 49 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1170821 46.51% 85.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 375623 14.92% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194899827 78.13% 78.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 979613 0.39% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194894311 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 979316 0.39% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued @@ -481,93 +482,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33082 0.01% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164367 0.07% 78.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 255141 0.10% 78.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76420 0.03% 78.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 466123 0.19% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33075 0.01% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164356 0.07% 78.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 254647 0.10% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76432 0.03% 78.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 465549 0.19% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206388 0.08% 79.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71859 0.03% 79.03% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38355265 15.38% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13948042 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38358541 15.38% 94.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13955444 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249456447 # Type of FU issued -system.cpu.iq.rate 1.680522 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2502650 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010032 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646705187 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466563017 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237885267 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3740007 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2195697 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1842613 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250082678 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1876419 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2013206 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249460239 # Type of FU issued +system.cpu.iq.rate 1.680732 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2517150 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010090 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 646712991 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466571759 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237891174 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3737382 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2188885 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1841279 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250102160 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1875229 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2007089 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13163190 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11604 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18881 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3771734 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13155956 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11631 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18977 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3784660 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 107 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 100 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20832385 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18544 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 886 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329254297 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 785292 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43012674 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16416368 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24746 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 181 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 276 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18881 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3889950 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3760088 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7650038 # Number of branch mispredicts detected at execute +system.cpu.iew.iewSquashCycles 20830243 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18508 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 911 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329253924 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 785902 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43005440 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16429294 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24682 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 206 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 274 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18977 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3891616 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3758665 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7650281 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 242960344 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36851914 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6496103 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecLoadInsts 36855491 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6499895 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17197 # number of nop insts executed -system.cpu.iew.exec_refs 50500351 # number of memory reference insts executed -system.cpu.iew.exec_branches 53426054 # Number of branches executed -system.cpu.iew.exec_stores 13648437 # Number of stores executed -system.cpu.iew.exec_rate 1.636759 # Inst execution rate -system.cpu.iew.wb_sent 240785488 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239727880 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148473973 # num instructions producing a value -system.cpu.iew.wb_consumers 267261246 # num instructions consuming a value +system.cpu.iew.exec_nop 17022 # number of nop insts executed +system.cpu.iew.exec_refs 50506525 # number of memory reference insts executed +system.cpu.iew.exec_branches 53424421 # Number of branches executed +system.cpu.iew.exec_stores 13651034 # Number of stores executed +system.cpu.iew.exec_rate 1.636939 # Inst execution rate +system.cpu.iew.wb_sent 240787816 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239732453 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148473522 # num instructions producing a value +system.cpu.iew.wb_consumers 267271209 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.614983 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back +system.cpu.iew.wb_rate 1.615192 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555516 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140583409 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140583033 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6128231 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127407906 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.480841 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.185453 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6126865 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127394978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.480992 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.186196 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57701601 45.29% 45.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31696921 24.88% 70.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13777775 10.81% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7640604 6.00% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4387783 3.44% 90.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1321955 1.04% 91.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1703214 1.34% 92.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1308007 1.03% 93.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7870046 6.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57713917 45.30% 45.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31674198 24.86% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13788488 10.82% 80.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7625423 5.99% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4380329 3.44% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1321262 1.04% 91.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1701589 1.34% 92.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1311888 1.03% 93.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7877884 6.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127407906 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127394978 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -578,230 +579,230 @@ system.cpu.commit.branches 40300311 # Nu system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7870046 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7877884 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448786959 # The number of ROB reads -system.cpu.rob.rob_writes 679450685 # The number of ROB writes -system.cpu.timesIdled 2806 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 199572 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 448765817 # The number of ROB reads +system.cpu.rob.rob_writes 679447245 # The number of ROB writes +system.cpu.timesIdled 2831 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 198321 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated -system.cpu.cpi 0.861505 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.861505 # CPI: Total CPI of All Threads -system.cpu.ipc 1.160760 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.160760 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079416198 # number of integer regfile reads -system.cpu.int_regfile_writes 384871537 # number of integer regfile writes -system.cpu.fp_regfile_reads 2913086 # number of floating regfile reads -system.cpu.fp_regfile_writes 2499105 # number of floating regfile writes -system.cpu.misc_regfile_reads 64870078 # number of misc regfile reads +system.cpu.cpi 0.861410 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.861410 # CPI: Total CPI of All Threads +system.cpu.ipc 1.160887 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.160887 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079439987 # number of integer regfile reads +system.cpu.int_regfile_writes 384873432 # number of integer regfile writes +system.cpu.fp_regfile_reads 2912671 # number of floating regfile reads +system.cpu.fp_regfile_writes 2497165 # number of floating regfile writes +system.cpu.misc_regfile_reads 64868455 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.throughput 5170363 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 4900 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 4899 # Transaction distribution +system.cpu.toL2Bus.throughput 5152821 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4879 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4878 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1079 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1079 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8253 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3722 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11975 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 264064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 383744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 383744 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8203 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3730 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11933 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 262464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 382400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 382400 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3016500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 3006000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6553746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6511747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3047989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3051239 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2395 # number of replacements -system.cpu.icache.tags.tagsinuse 1347.740461 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 36845513 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4126 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8930.080708 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2374 # number of replacements +system.cpu.icache.tags.tagsinuse 1347.666302 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 36843383 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4101 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8983.999756 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740461 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1731 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 544 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 27 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1037 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.845215 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 73705828 # Number of tag accesses -system.cpu.icache.tags.data_accesses 73705828 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 36845513 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36845513 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36845513 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36845513 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36845513 # number of overall hits -system.cpu.icache.overall_hits::total 36845513 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5338 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5338 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5338 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5338 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5338 # number of overall misses -system.cpu.icache.overall_misses::total 5338 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 225943745 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 225943745 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 225943745 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 225943745 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 225943745 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 225943745 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36850851 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36850851 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36850851 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36850851 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36850851 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36850851 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42327.415699 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42327.415699 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42327.415699 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42327.415699 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42327.415699 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42327.415699 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1128 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1347.666302 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.658040 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.658040 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1727 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 534 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1040 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.843262 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 73701491 # Number of tag accesses +system.cpu.icache.tags.data_accesses 73701491 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 36843383 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36843383 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36843383 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36843383 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36843383 # number of overall hits +system.cpu.icache.overall_hits::total 36843383 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5312 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5312 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5312 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5312 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5312 # number of overall misses +system.cpu.icache.overall_misses::total 5312 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 224724996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 224724996 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 224724996 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 224724996 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 224724996 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 224724996 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36848695 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36848695 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36848695 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36848695 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36848695 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36848695 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000144 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000144 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000144 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000144 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000144 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000144 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42305.157380 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42305.157380 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42305.157380 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42305.157380 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42305.157380 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42305.157380 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1646 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.368421 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 86.631579 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1211 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1211 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1211 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1211 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1211 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1211 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4127 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4127 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4127 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4127 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4127 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4127 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168102254 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 168102254 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168102254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 168102254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168102254 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 168102254 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40732.312576 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40732.312576 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40732.312576 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40732.312576 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40732.312576 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40732.312576 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1210 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1210 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1210 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1210 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1210 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1210 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4102 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4102 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4102 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4102 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4102 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4102 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 167739253 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 167739253 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 167739253 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 167739253 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 167739253 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 167739253 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000111 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000111 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40892.065578 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40892.065578 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40892.065578 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40892.065578 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40892.065578 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40892.065578 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1967.449595 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2163 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2732 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.791728 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 1968.326603 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2138 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2737 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.781147 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 4.994097 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569547 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 536.885951 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 4.994032 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.493487 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 537.839084 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043505 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.016384 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.060042 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2732 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 604 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043503 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.016414 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.060069 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2737 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 602 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1970 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083374 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 51787 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 51787 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2074 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2162 # number of ReadReq hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1971 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083527 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 51624 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 51624 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 2050 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 87 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2137 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2074 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 96 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2170 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2074 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 96 # number of overall hits -system.cpu.l2cache.overall_hits::total 2170 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2053 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 685 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2738 # number of ReadReq misses +system.cpu.l2cache.demand_hits::cpu.inst 2050 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 95 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2145 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2050 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 95 # number of overall hits +system.cpu.l2cache.overall_hits::total 2145 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2052 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 690 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2742 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 1071 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1071 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2053 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1756 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3809 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2053 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses -system.cpu.l2cache.overall_misses::total 3809 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143228250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51387250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 194615500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72292250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 72292250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 143228250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 123679500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 266907750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 143228250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 123679500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 266907750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4127 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 4900 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 2052 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1761 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3813 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2052 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1761 # number of overall misses +system.cpu.l2cache.overall_misses::total 3813 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143127750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 50855750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 193983500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72887500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 72887500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 143127750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 123743250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 266871000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 143127750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 123743250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 266871000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4102 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 777 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 4879 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1079 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1079 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4127 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1852 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 5979 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4127 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1852 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5979 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.497456 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.886158 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.558776 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 4102 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1856 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 5958 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4102 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1856 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 5958 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.500244 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888031 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.562000 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992586 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.992586 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.497456 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.948164 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.637063 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497456 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.948164 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.637063 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69765.343400 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75017.883212 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71079.437546 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.766573 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.766573 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69765.343400 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70432.517084 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70072.919401 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69765.343400 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70432.517084 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70072.919401 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.500244 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.948815 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.639980 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.500244 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.948815 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.639980 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69750.365497 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73703.985507 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70745.258935 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68055.555556 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68055.555556 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69750.365497 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70268.739353 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69989.771833 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69750.365497 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70268.739353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69989.771833 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -810,178 +811,178 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2049 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 674 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2723 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 679 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2728 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1071 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1071 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2049 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1745 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3794 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1750 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3799 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2049 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3794 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117257250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42300250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159557500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58841750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58841750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117257250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101142000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 218399250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117257250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101142000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 218399250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871928 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555714 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1750 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3799 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117223750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41708750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 158932500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59427500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59427500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117223750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101136250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 218360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117223750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101136250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 218360000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.499512 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.873874 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.559131 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992586 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992586 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.634554 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.634554 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57226.573939 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62760.014837 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58596.217407 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54940.943044 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54940.943044 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57226.573939 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57961.031519 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57564.377965 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57226.573939 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57961.031519 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57564.377965 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.499512 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942888 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.637630 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.499512 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942888 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.637630 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57210.224500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61426.730486 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58259.714076 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55487.861811 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55487.861811 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57210.224500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57792.142857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57478.283759 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57210.224500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57792.142857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57478.283759 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 57 # number of replacements -system.cpu.dcache.tags.tagsinuse 1406.103051 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 46786126 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1852 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25262.487041 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 59 # number of replacements +system.cpu.dcache.tags.tagsinuse 1407.038554 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 46795712 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1856 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25213.206897 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103051 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.343287 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.343287 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1795 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1407.038554 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.343515 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.343515 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 353 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1378 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.438232 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 93593354 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 93593354 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 34384681 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34384681 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356564 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356564 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22474 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22474 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_task_id_percent::1024 0.438721 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 93612504 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 93612504 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 34394263 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34394263 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356566 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356566 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22476 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22476 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46741245 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46741245 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46741245 # number of overall hits -system.cpu.dcache.overall_hits::total 46741245 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1900 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1900 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7723 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7723 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 46750829 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46750829 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46750829 # number of overall hits +system.cpu.dcache.overall_hits::total 46750829 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1889 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1889 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7721 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7721 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9623 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9623 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9623 # number of overall misses -system.cpu.dcache.overall_misses::total 9623 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 121712227 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 121712227 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623746 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 465623746 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9610 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9610 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9610 # number of overall misses +system.cpu.dcache.overall_misses::total 9610 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 119060977 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 119060977 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 479134996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 479134996 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 587335973 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 587335973 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 587335973 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 587335973 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34386581 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34386581 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 598195973 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 598195973 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 598195973 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 598195973 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34396152 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34396152 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22476 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22476 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22478 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22478 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46750868 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46750868 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46750868 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46750868 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 46760439 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46760439 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46760439 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46760439 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64059.066842 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64059.066842 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.527774 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.527774 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63028.574378 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63028.574378 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62056.080300 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62056.080300 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61034.601787 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61034.601787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61034.601787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61034.601787 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 314 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62247.239646 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62247.239646 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62247.239646 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62247.239646 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 566 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 318 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.818182 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 78.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.454545 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 79.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1126 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1126 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6645 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6645 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1111 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1111 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6643 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6643 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7771 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7771 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7771 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7771 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 7754 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7754 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7754 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7754 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 778 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 778 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1078 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1078 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1852 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1852 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1852 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1852 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53118011 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 53118011 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73393498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 73393498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126511509 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 126511509 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126511509 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 126511509 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52580511 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52580511 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73988748 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73988748 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126569259 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 126569259 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126569259 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 126569259 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses @@ -990,14 +991,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68627.921189 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68627.921189 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68083.022263 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68083.022263 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68310.750000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68310.750000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68310.750000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68310.750000 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67584.204370 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67584.204370 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68635.202226 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68635.202226 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68194.643858 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68194.643858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68194.643858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68194.643858 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 1427887bb..cc1011ed3 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.144463 # Number of seconds simulated -sim_ticks 144463317000 # Number of ticks simulated -final_tick 144463317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.144377 # Number of seconds simulated +sim_ticks 144377116000 # Number of ticks simulated +final_tick 144377116000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81167 # Simulator instruction rate (inst/s) -host_op_rate 136043 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88782348 # Simulator tick rate (ticks/s) -host_mem_usage 282908 # Number of bytes of host memory used -host_seconds 1627.16 # Real time elapsed on the host +host_inst_rate 66784 # Simulator instruction rate (inst/s) +host_op_rate 111936 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73006862 # Simulator tick rate (ticks/s) +host_mem_usage 319660 # Number of bytes of host memory used +host_seconds 1977.58 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 217088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125568 # Number of bytes read from this memory -system.physmem.bytes_read::total 342656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217088 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3392 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1962 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5354 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1502721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 869203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2371924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1502721 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1502721 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1502721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 869203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2371924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5354 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125056 # Number of bytes read from this memory +system.physmem.bytes_read::total 343040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1954 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5360 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1509824 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 866176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2376000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1509824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1509824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1509824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 866176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2376000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5361 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5354 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5361 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 342656 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 343104 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 342656 # Total read bytes from the system interface side +system.physmem.bytesReadSys 343104 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 163 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 289 # Per bank write bursts -system.physmem.perBankRdBursts::1 357 # Per bank write bursts -system.physmem.perBankRdBursts::2 453 # Per bank write bursts -system.physmem.perBankRdBursts::3 356 # Per bank write bursts -system.physmem.perBankRdBursts::4 332 # Per bank write bursts -system.physmem.perBankRdBursts::5 326 # Per bank write bursts -system.physmem.perBankRdBursts::6 402 # Per bank write bursts -system.physmem.perBankRdBursts::7 377 # Per bank write bursts -system.physmem.perBankRdBursts::8 341 # Per bank write bursts -system.physmem.perBankRdBursts::9 276 # Per bank write bursts -system.physmem.perBankRdBursts::10 232 # Per bank write bursts -system.physmem.perBankRdBursts::11 277 # Per bank write bursts -system.physmem.perBankRdBursts::12 205 # Per bank write bursts -system.physmem.perBankRdBursts::13 465 # Per bank write bursts -system.physmem.perBankRdBursts::14 384 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 150 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 281 # Per bank write bursts +system.physmem.perBankRdBursts::1 346 # Per bank write bursts +system.physmem.perBankRdBursts::2 449 # Per bank write bursts +system.physmem.perBankRdBursts::3 351 # Per bank write bursts +system.physmem.perBankRdBursts::4 335 # Per bank write bursts +system.physmem.perBankRdBursts::5 328 # Per bank write bursts +system.physmem.perBankRdBursts::6 398 # Per bank write bursts +system.physmem.perBankRdBursts::7 381 # Per bank write bursts +system.physmem.perBankRdBursts::8 343 # Per bank write bursts +system.physmem.perBankRdBursts::9 292 # Per bank write bursts +system.physmem.perBankRdBursts::10 228 # Per bank write bursts +system.physmem.perBankRdBursts::11 284 # Per bank write bursts +system.physmem.perBankRdBursts::12 208 # Per bank write bursts +system.physmem.perBankRdBursts::13 469 # Per bank write bursts +system.physmem.perBankRdBursts::14 386 # Per bank write bursts system.physmem.perBankRdBursts::15 282 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 144463266500 # Total gap between requests +system.physmem.totGap 144377080000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5354 # Read request sizes (log2) +system.physmem.readPktSize::6 5361 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 145 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -154,346 +154,337 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 957 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 353.103448 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.307957 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 612.115437 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 385 40.23% 40.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 164 17.14% 57.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 81 8.46% 65.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 46 4.81% 70.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 43 4.49% 75.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 20 2.09% 77.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 26 2.72% 79.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 19 1.99% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 17 1.78% 83.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 26 2.72% 86.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 27 2.82% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 7 0.73% 89.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 7 0.73% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 7 0.73% 91.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 3 0.31% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 5 0.52% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 6 0.63% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 6 0.63% 93.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 4 0.42% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 2 0.21% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 2 0.21% 94.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 3 0.31% 94.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 7 0.73% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 1 0.10% 95.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 5 0.52% 96.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 4 0.42% 96.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 2 0.21% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 2 0.21% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 2 0.21% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 3 0.31% 97.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 2 0.21% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 1 0.10% 97.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 1 0.10% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 1 0.10% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 1 0.10% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 1 0.10% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 2 0.21% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 1 0.10% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 2 0.21% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 3 0.31% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 1 0.10% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 1 0.10% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 1 0.10% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 1 0.10% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 1 0.10% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 1 0.10% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 1 0.10% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 1 0.10% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696 1 0.10% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952 1 0.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 957 # Bytes accessed per row activation -system.physmem.totQLat 28783000 # Total ticks spent queuing -system.physmem.totMemAccLat 137846750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26770000 # Total ticks spent in databus transfers -system.physmem.totBankLat 82293750 # Total ticks spent accessing banks -system.physmem.avgQLat 5375.98 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 15370.52 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 508.672783 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 294.998238 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 425.682375 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 88 26.91% 26.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 53 16.21% 43.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 28 8.56% 51.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 16 4.89% 56.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 9 2.75% 59.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 1.83% 61.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 0.92% 62.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 0.92% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 121 37.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 327 # Bytes accessed per row activation +system.physmem.totQLat 28551000 # Total ticks spent queuing +system.physmem.totMemAccLat 139987250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26805000 # Total ticks spent in databus transfers +system.physmem.totBankLat 84631250 # Total ticks spent accessing banks +system.physmem.avgQLat 5325.69 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15786.47 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25746.50 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26112.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.38 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.38 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4397 # Number of row buffer hits during reads +system.physmem.readRowHits 4274 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.13 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.72 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 26982306.03 # Average gap between requests -system.physmem.pageHitRate 82.13 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 2371924 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3822 # Transaction distribution -system.membus.trans_dist::ReadResp 3822 # Transaction distribution -system.membus.trans_dist::UpgradeReq 163 # Transaction distribution -system.membus.trans_dist::UpgradeResp 163 # Transaction distribution -system.membus.trans_dist::ReadExReq 1532 # Transaction distribution -system.membus.trans_dist::ReadExResp 1532 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11034 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11034 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11034 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342656 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342656 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 342656 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 342656 # Total data (bytes) +system.physmem.avgGap 26930997.95 # Average gap between requests +system.physmem.pageHitRate 79.72 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.40 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 2375113 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3828 # Transaction distribution +system.membus.trans_dist::ReadResp 3825 # Transaction distribution +system.membus.trans_dist::UpgradeReq 150 # Transaction distribution +system.membus.trans_dist::UpgradeResp 150 # Transaction distribution +system.membus.trans_dist::ReadExReq 1533 # Transaction distribution +system.membus.trans_dist::ReadExResp 1533 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11019 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11019 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11019 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 342912 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 342912 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6993500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50662837 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 50706850 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 18648233 # Number of BP lookups -system.cpu.branchPred.condPredicted 18648233 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1490176 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11407549 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10790529 # Number of BTB hits +system.cpu.branchPred.lookups 18662333 # Number of BP lookups +system.cpu.branchPred.condPredicted 18662333 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1490477 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11407057 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10802916 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.591126 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1320367 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 22841 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.703796 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1319575 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 23217 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 289221873 # number of cpu cycles simulated +system.cpu.numCycles 289035036 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 23458043 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 206724218 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18648233 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12110896 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54209097 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15518774 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 178161359 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1571 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9111 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22353211 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 224061 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269612469 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.268180 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.756310 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 23466628 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 206674196 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18662333 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12122491 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 54224578 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 15529649 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 177872737 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1739 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9780 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22363082 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 227556 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269352720 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.269654 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.757498 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 216842563 80.43% 80.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2848142 1.06% 81.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2312055 0.86% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2633842 0.98% 83.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3218714 1.19% 84.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3388946 1.26% 85.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3831195 1.42% 87.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2559437 0.95% 88.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31977575 11.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 216567147 80.40% 80.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2849140 1.06% 81.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2312743 0.86% 82.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2640443 0.98% 83.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3223496 1.20% 84.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3388678 1.26% 85.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3828931 1.42% 87.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2559342 0.95% 88.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31982800 11.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269612469 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064477 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.714760 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36899359 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 167130004 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41545229 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10264627 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13773250 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336001462 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13773250 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44972487 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116686698 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 32545 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 42701689 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51445800 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 329633775 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10827 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26123597 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22730549 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 382342090 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 917586713 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 605878272 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4127660 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 269352720 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064568 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.715049 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36872291 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 166882879 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 41583049 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10237266 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13777235 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336030589 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 13777235 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44927552 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116592006 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 33482 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 42725844 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51296601 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 329644603 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10793 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25973281 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22738118 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 382392326 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 917644681 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 605892364 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4122807 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 122912640 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2051 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2042 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 105140052 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84507276 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 30107186 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58355212 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 18979888 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322730905 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260501994 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 116055 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 100987191 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 210203655 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269612469 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.966209 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.343680 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 122962876 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2119 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2126 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 104910685 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 84442386 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 30099715 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58118082 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 18905602 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 322699954 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4280 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 260615725 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 114961 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 100953398 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 209924725 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3035 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 269352720 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.967563 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.344835 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143429912 53.20% 53.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55567346 20.61% 73.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34108148 12.65% 86.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19044980 7.06% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10887634 4.04% 97.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4152283 1.54% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1816697 0.67% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 472473 0.18% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 132996 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143250903 53.18% 53.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55370436 20.56% 73.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34176648 12.69% 86.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19094867 7.09% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10869897 4.04% 97.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4155062 1.54% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1825131 0.68% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 476500 0.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 133276 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269612469 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269352720 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 130605 4.82% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2279077 84.03% 88.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 302412 11.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 130941 4.84% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2275620 84.10% 88.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 299199 11.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1210810 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162055944 62.21% 62.67% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 789191 0.30% 62.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7035649 2.70% 65.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1445882 0.56% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65414513 25.11% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22550005 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1210799 0.46% 0.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 162097443 62.20% 62.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 790400 0.30% 62.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035783 2.70% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1447528 0.56% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65478586 25.12% 91.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22555186 8.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260501994 # Type of FU issued -system.cpu.iq.rate 0.900699 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2712094 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010411 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 788557578 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 420384868 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255147075 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4887028 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3615221 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2349564 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259544026 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2459252 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18903382 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 260615725 # Type of FU issued +system.cpu.iq.rate 0.901675 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2705760 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010382 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 788512519 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 420334227 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 255242293 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4892372 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3608187 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2352192 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 259648600 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2462086 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18920241 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27857689 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25992 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 283319 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9591469 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27792799 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26588 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 290410 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9583998 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49752 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49921 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13773250 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 85040639 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5471570 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322734974 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 133239 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84507276 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 30107186 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1979 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2708196 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13910 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 283319 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 639398 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 901242 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1540640 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 258732431 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64645019 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1769563 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 13777235 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 85064772 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5446513 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 322704234 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 135340 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 84442386 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 30099715 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2049 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2678194 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12950 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 290410 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 639185 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 902051 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1541236 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 258833919 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64703526 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1781806 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 86992194 # number of memory reference insts executed -system.cpu.iew.exec_branches 14265859 # Number of branches executed -system.cpu.iew.exec_stores 22347175 # Number of stores executed -system.cpu.iew.exec_rate 0.894581 # Inst execution rate -system.cpu.iew.wb_sent 258096693 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257496639 # cumulative count of insts written-back -system.cpu.iew.wb_producers 205928299 # num instructions producing a value -system.cpu.iew.wb_consumers 369130530 # num instructions consuming a value +system.cpu.iew.exec_refs 87053484 # number of memory reference insts executed +system.cpu.iew.exec_branches 14272898 # Number of branches executed +system.cpu.iew.exec_stores 22349958 # Number of stores executed +system.cpu.iew.exec_rate 0.895511 # Inst execution rate +system.cpu.iew.wb_sent 258192676 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 257594485 # cumulative count of insts written-back +system.cpu.iew.wb_producers 206043233 # num instructions producing a value +system.cpu.iew.wb_consumers 369200904 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.890308 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557874 # average fanout of values written-back +system.cpu.iew.wb_rate 0.891222 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.558079 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101448840 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 101415579 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1491529 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255839219 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.865244 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.654327 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1491917 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255575485 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.866137 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.656618 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156486617 61.17% 61.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57197635 22.36% 83.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14067876 5.50% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12054068 4.71% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4176261 1.63% 95.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2944387 1.15% 96.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 904564 0.35% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1049058 0.41% 97.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6958753 2.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156360594 61.18% 61.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57109316 22.35% 83.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13985683 5.47% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12037857 4.71% 93.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4182593 1.64% 95.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2963821 1.16% 96.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 909345 0.36% 96.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1046624 0.41% 97.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6979652 2.73% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255839219 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 255575485 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -504,240 +495,240 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. system.cpu.commit.function_calls 797818 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6958753 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6979652 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571692690 # The number of ROB reads -system.cpu.rob.rob_writes 659422914 # The number of ROB writes -system.cpu.timesIdled 5933064 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19609404 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571374796 # The number of ROB reads +system.cpu.rob.rob_writes 659361249 # The number of ROB writes +system.cpu.timesIdled 5927783 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19682316 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 2.189894 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.189894 # CPI: Total CPI of All Threads -system.cpu.ipc 0.456643 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.456643 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 451224153 # number of integer regfile reads -system.cpu.int_regfile_writes 233957254 # number of integer regfile writes -system.cpu.fp_regfile_reads 3215586 # number of floating regfile reads -system.cpu.fp_regfile_writes 2009211 # number of floating regfile writes -system.cpu.cc_regfile_reads 102809513 # number of cc regfile reads -system.cpu.cc_regfile_writes 59799383 # number of cc regfile writes -system.cpu.misc_regfile_reads 133324417 # number of misc regfile reads +system.cpu.cpi 2.188479 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.188479 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456938 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456938 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 451403378 # number of integer regfile reads +system.cpu.int_regfile_writes 234040975 # number of integer regfile writes +system.cpu.fp_regfile_reads 3219859 # number of floating regfile reads +system.cpu.fp_regfile_writes 2011879 # number of floating regfile writes +system.cpu.cc_regfile_reads 102824885 # number of cc regfile reads +system.cpu.cc_regfile_writes 59817361 # number of cc regfile writes +system.cpu.misc_regfile_reads 133392985 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.toL2Bus.throughput 3898568 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7250 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 163 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 163 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13403 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17751 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 552704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 552704 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 10496 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4495500 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 3846371 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7125 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7121 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 15 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 150 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 150 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1541 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13184 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4308 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17492 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 417024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 545664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 545664 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 9664 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4430500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10760250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10573999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3467413 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3437150 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 4653 # number of replacements -system.cpu.icache.tags.tagsinuse 1619.938452 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22344300 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6620 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3375.271903 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4547 # number of replacements +system.cpu.icache.tags.tagsinuse 1629.451963 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22354297 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6517 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3430.151450 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1619.938452 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.790986 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.790986 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1967 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 767 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 797 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.960449 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 44713203 # Number of tag accesses -system.cpu.icache.tags.data_accesses 44713203 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22344300 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22344300 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22344300 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22344300 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22344300 # number of overall hits -system.cpu.icache.overall_hits::total 22344300 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8910 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8910 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8910 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8910 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8910 # number of overall misses -system.cpu.icache.overall_misses::total 8910 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 368144999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 368144999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 368144999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 368144999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 368144999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 368144999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22353210 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22353210 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22353210 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22353210 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22353210 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22353210 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41318.181706 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41318.181706 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41318.181706 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41318.181706 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 877 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1629.451963 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.795631 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.795631 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1970 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 757 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 807 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.961914 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 44732829 # Number of tag accesses +system.cpu.icache.tags.data_accesses 44732829 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22354297 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22354297 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22354297 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22354297 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22354297 # number of overall hits +system.cpu.icache.overall_hits::total 22354297 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8784 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8784 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8784 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8784 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8784 # number of overall misses +system.cpu.icache.overall_misses::total 8784 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 365846249 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 365846249 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 365846249 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 365846249 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 365846249 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 365846249 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22363081 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22363081 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22363081 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22363081 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22363081 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22363081 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000393 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000393 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000393 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000393 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000393 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000393 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41649.163138 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41649.163138 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41649.163138 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41649.163138 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41649.163138 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41649.163138 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 800 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.850000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 57.142857 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2126 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2126 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2126 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2126 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2126 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2126 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6784 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6784 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6784 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6784 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6784 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6784 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271638749 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 271638749 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271638749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 271638749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271638749 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 271638749 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40041.089180 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40041.089180 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2116 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2116 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2116 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2116 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2116 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2116 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6668 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6668 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6668 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6668 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6668 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6668 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 272166001 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 272166001 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 272166001 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 272166001 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 272166001 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 272166001 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000298 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000298 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000298 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000298 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000298 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000298 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40816.736803 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40816.736803 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40816.736803 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40816.736803 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40816.736803 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40816.736803 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2543.926920 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3266 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3826 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.853633 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2545.733703 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3149 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3831 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.821979 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1.725256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334814 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 311.866849 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068064 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.009517 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.077634 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3826 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 876 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 145 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2560 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.116760 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 75773 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 75773 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 3227 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 1.666971 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2237.371026 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 306.695706 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000051 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068279 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.009360 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.077690 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3831 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 881 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 143 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2568 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.116913 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 74812 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 74812 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 3110 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 36 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3263 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3227 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 43 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3270 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3227 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 43 # number of overall hits -system.cpu.l2cache.overall_hits::total 3270 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3393 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 430 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3823 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 163 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 163 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1532 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1532 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3393 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1962 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5355 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3393 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1962 # number of overall misses -system.cpu.l2cache.overall_misses::total 5355 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232417000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32755500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 265172500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104434000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 104434000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 232417000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 137189500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 369606500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 232417000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 137189500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 369606500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 6620 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 466 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7086 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 163 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 163 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1539 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1539 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6620 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2005 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8625 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6620 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2005 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8625 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.512538 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.922747 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.539515 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_hits::total 3146 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 15 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 15 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3110 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 44 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3154 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3110 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 44 # number of overall hits +system.cpu.l2cache.overall_hits::total 3154 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3407 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 421 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3828 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 150 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 150 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1533 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1533 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3407 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1954 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5361 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3407 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1954 # number of overall misses +system.cpu.l2cache.overall_misses::total 5361 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234241000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32796500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 267037500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104661000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 104661000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 234241000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 137457500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 371698500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 234241000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 137457500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 371698500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6517 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 457 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 6974 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 15 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 15 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 150 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 150 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1541 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1541 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6517 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1998 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8515 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6517 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1998 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8515 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.522787 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.921225 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.548896 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995452 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.995452 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.512538 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.978554 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.620870 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.512538 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.978554 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.620870 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68498.968464 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76175.581395 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69362.411719 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68168.407311 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68168.407311 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69020.821662 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69020.821662 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994809 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994809 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.522787 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.977978 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.629595 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.522787 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.977978 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.629595 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68752.861755 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77901.425178 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69759.012539 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68272.015656 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68272.015656 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68752.861755 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70346.724667 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69333.799664 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68752.861755 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70346.724667 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69333.799664 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -746,175 +737,175 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3393 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 430 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3823 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 163 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 163 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1532 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1532 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3393 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1962 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5355 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3393 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5355 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 189899500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27426500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 217326000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1630163 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1630163 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 84874000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 84874000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189899500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 112300500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 302200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189899500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 112300500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 302200000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.922747 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.539515 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3407 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 421 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3828 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 150 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 150 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1533 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1533 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3407 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1954 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5361 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3407 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1954 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5361 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 191583500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27592500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 219176000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1500150 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1500150 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 85063500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 85063500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 191583500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 112656000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 304239500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 191583500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 112656000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 304239500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.522787 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.921225 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.548896 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995452 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995452 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.620870 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.620870 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55968.022399 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63782.558140 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56846.978812 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994809 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994809 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.522787 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977978 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.629595 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.522787 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977978 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.629595 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56232.315820 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65540.380048 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57256.008359 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55400.783290 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55400.783290 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55488.258317 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55488.258317 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56232.315820 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57654.042989 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56750.512964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56232.315820 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57654.042989 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56750.512964 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 57 # number of replacements -system.cpu.dcache.tags.tagsinuse 1438.861304 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66102356 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2004 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32985.207585 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1432.023881 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 66143701 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1995 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33154.737343 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1438.861304 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.351284 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.351284 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1947 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1432.023881 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.349615 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.349615 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1395 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.475342 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 132211530 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 132211530 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 45588097 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45588097 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514029 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514029 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66102126 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66102126 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66102126 # number of overall hits -system.cpu.dcache.overall_hits::total 66102126 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 935 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 935 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1702 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1702 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2637 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2637 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2637 # number of overall misses -system.cpu.dcache.overall_misses::total 2637 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 62763567 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 62763567 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 113907163 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 113907163 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 176670730 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 176670730 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 176670730 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 176670730 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45589032 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45589032 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 427 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1393 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.473145 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 132294203 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 132294203 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 45629460 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45629460 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514040 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514040 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 66143500 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66143500 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66143500 # number of overall hits +system.cpu.dcache.overall_hits::total 66143500 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 913 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 913 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1691 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1691 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2604 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2604 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2604 # number of overall misses +system.cpu.dcache.overall_misses::total 2604 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59632801 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59632801 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 113805150 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 113805150 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 173437951 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 173437951 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 173437951 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 173437951 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45630373 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45630373 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66104763 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66104763 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66104763 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66104763 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000083 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67126.809626 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67126.809626 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66925.477673 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66925.477673 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66996.863860 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66996.863860 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66996.863860 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66996.863860 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 66146104 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66146104 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66146104 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66146104 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000082 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000082 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65315.225630 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 65315.225630 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67300.502661 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67300.502661 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66604.435868 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66604.435868 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66604.435868 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66604.435868 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 319 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 77 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 79.750000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 13 # number of writebacks -system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 468 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 468 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 15 # number of writebacks +system.cpu.dcache.writebacks::total 15 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 455 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 455 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 469 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 469 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 469 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 469 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 467 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1701 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1701 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2168 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33590500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33590500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109769587 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 109769587 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 143360087 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 143360087 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 143360087 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 143360087 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 456 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 456 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 456 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 456 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 458 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1690 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1690 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2148 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2148 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2148 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2148 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33615250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33615250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109709600 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 109709600 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 143324850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 143324850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 143324850 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 143324850 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000083 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71928.265525 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71928.265525 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64532.385068 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64532.385068 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66125.501384 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66125.501384 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66125.501384 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66125.501384 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73395.742358 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73395.742358 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64916.923077 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64916.923077 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66724.790503 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66724.790503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66724.790503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66724.790503 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |