stats: Update stats to reflect cache changes

Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.

5 files changed, 24 insertions, 69 deletions

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
index 6eb6b8f50..db5b9481a 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.051906                       # Nu
 sim_ticks                                 51905634500                       # Number of ticks simulated
 final_tick                                51905634500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 327219                       # Simulator instruction rate (inst/s)
-host_op_rate                                   327219                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              184808729                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 257300                       # Number of bytes of host memory used
-host_seconds                                   280.86                       # Real time elapsed on the host
+host_inst_rate                                 330127                       # Simulator instruction rate (inst/s)
+host_op_rate                                   330127                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              186451175                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257296                       # Number of bytes of host memory used
+host_seconds                                   278.39                       # Real time elapsed on the host
 sim_insts                                    91903089                       # Number of instructions simulated
 sim_ops                                      91903089                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -415,8 +415,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          107                       # number of writebacks
 system.cpu.dcache.writebacks::total               107                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           36                       # number of ReadReq MSHR hits
@@ -459,7 +457,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75493.273543
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 75493.273543                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75493.273543                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 75493.273543                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             13853                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1642.330146                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            22935687                       # Total number of references to valid blocks.
@@ -520,8 +517,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        13853                       # number of writebacks
 system.cpu.icache.writebacks::total             13853                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15819                       # number of ReadReq MSHR misses
@@ -548,7 +543,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24717.681269
 system.cpu.icache.demand_avg_mshr_miss_latency::total 24717.681269                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24717.681269                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 24717.681269                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         2479.710860                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              26619                       # Total number of references to valid blocks.
@@ -657,8 +651,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1719                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1719                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3169                       # number of ReadCleanReq MSHR misses
@@ -707,7 +699,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64931.296992
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63987.219943                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66322.175732                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64931.296992                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        32058                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests        14010                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 5ce51dae8..96bd3631d 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.021909                       # Nu
 sim_ticks                                 21909208500                       # Number of ticks simulated
 final_tick                                21909208500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 236201                       # Simulator instruction rate (inst/s)
-host_op_rate                                   236201                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               61475451                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 258056                       # Number of bytes of host memory used
-host_seconds                                   356.39                       # Real time elapsed on the host
+host_inst_rate                                 220296                       # Simulator instruction rate (inst/s)
+host_op_rate                                   220296                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               57335863                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 258312                       # Number of bytes of host memory used
+host_seconds                                   382.12                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -672,8 +672,6 @@ system.cpu.dcache.blocked::no_mshrs               392                       # nu
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    83.017857                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    63.500000                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          108                       # number of writebacks
 system.cpu.dcache.writebacks::total               108                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          559                       # number of ReadReq MSHR hits
@@ -724,7 +722,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78282.306150
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 78282.306150                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78282.306150                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 78282.306150                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              9515                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1600.928709                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            15918297                       # Total number of references to valid blocks.
@@ -785,8 +782,6 @@ system.cpu.icache.blocked::no_mshrs                 4                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          159                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         9515                       # number of writebacks
 system.cpu.icache.writebacks::total              9515                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2951                       # number of ReadReq MSHR hits
@@ -819,7 +814,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29396.018858
 system.cpu.icache.demand_avg_mshr_miss_latency::total 29396.018858                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29396.018858                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 29396.018858                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         2407.364249                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              18027                       # Total number of references to valid blocks.
@@ -928,8 +922,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1703                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1703                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3062                       # number of ReadCleanReq MSHR misses
@@ -978,7 +970,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67000.095657
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65472.566950                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69160.508083                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67000.095657                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        23372                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests         9673                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
index 21492b1f0..aa163eec8 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.130383                       # Nu
 sim_ticks                                130382890500                       # Number of ticks simulated
 final_tick                               130382890500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 248644                       # Simulator instruction rate (inst/s)
-host_op_rate                                   262111                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              188134778                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 275596                       # Number of bytes of host memory used
-host_seconds                                   693.03                       # Real time elapsed on the host
+host_inst_rate                                 248771                       # Simulator instruction rate (inst/s)
+host_op_rate                                   262245                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              188230845                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 275588                       # Number of bytes of host memory used
+host_seconds                                   692.68                       # Real time elapsed on the host
 sim_insts                                   172317810                       # Number of instructions simulated
 sim_ops                                     181650743                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -515,8 +515,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
 system.cpu.dcache.writebacks::total                16                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           82                       # number of ReadReq MSHR hits
@@ -567,7 +565,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              2881                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1423.942746                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            70779397                       # Total number of references to valid blocks.
@@ -628,8 +625,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         2881                       # number of writebacks
 system.cpu.icache.writebacks::total              2881                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4678                       # number of ReadReq MSHR misses
@@ -656,7 +651,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055
 system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         1999.548128                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs               5178                       # Total number of references to valid blocks.
@@ -765,8 +759,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           14                       # number of ReadSharedReq MSHR hits
@@ -825,7 +817,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65733.902250
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63980.546549                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests         9412                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests         3057                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests          328                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 7b9f789c6..be1a4308b 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.084938                       # Nu
 sim_ticks                                 84937723500                       # Number of ticks simulated
 final_tick                                84937723500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 146803                       # Simulator instruction rate (inst/s)
-host_op_rate                                   154755                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               72367413                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 152098                       # Simulator instruction rate (inst/s)
+host_op_rate                                   160337                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               74977715                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 271624                       # Number of bytes of host memory used
-host_seconds                                  1173.70                       # Real time elapsed on the host
+host_seconds                                  1132.84                       # Real time elapsed on the host
 sim_insts                                   172303022                       # Number of instructions simulated
 sim_ops                                     181635954                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -772,8 +772,6 @@ system.cpu.dcache.blocked::no_mshrs                 2                       # nu
 system.cpu.dcache.blocked::no_targets             864                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs           83                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    12.428241                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks        72581                       # number of writebacks
 system.cpu.dcache.writebacks::total             72581                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24802                       # number of ReadReq MSHR hits
@@ -826,7 +824,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10129.083297
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 10129.083297                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10126.585295                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 10126.585295                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             53623                       # number of replacements
 system.cpu.icache.tags.tagsinuse           510.594536                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            78269055                       # Total number of references to valid blocks.
@@ -887,8 +884,6 @@ system.cpu.icache.blocked::no_mshrs              3246                       # nu
 system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    22.549291                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    13.500000                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        53623                       # number of writebacks
 system.cpu.icache.writebacks::total             53623                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3399                       # number of ReadReq MSHR hits
@@ -921,7 +916,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19208.778853
 system.cpu.icache.demand_avg_mshr_miss_latency::total 19208.778853                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.prefetcher.num_hwpf_issued         9269                       # number of hwpf issued
 system.cpu.l2cache.prefetcher.pfIdentified         9269                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
@@ -1040,8 +1034,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data            1                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadExReq_mshr_hits::total            1                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            5                       # number of ReadCleanReq MSHR hits
@@ -1114,7 +1106,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69132.327304
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.843023                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests       253433                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       126224                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        10473                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index f0a8cbf5a..d2b7d14ce 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.103324                       # Nu
 sim_ticks                                103324153500                       # Number of ticks simulated
 final_tick                               103324153500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  72241                       # Simulator instruction rate (inst/s)
-host_op_rate                                   121082                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               56516511                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 307592                       # Number of bytes of host memory used
-host_seconds                                  1828.21                       # Real time elapsed on the host
+host_inst_rate                                  75581                       # Simulator instruction rate (inst/s)
+host_op_rate                                   126680                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               59129521                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 307596                       # Number of bytes of host memory used
+host_seconds                                  1747.42                       # Real time elapsed on the host
 sim_insts                                   132071192                       # Number of instructions simulated
 sim_ops                                     221363384                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -632,8 +632,6 @@ system.cpu.dcache.blocked::no_mshrs                 8                       # nu
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    46.125000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    36.500000                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           18                       # number of writebacks
 system.cpu.dcache.writebacks::total                18                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          661                       # number of ReadReq MSHR hits
@@ -676,7 +674,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              6515                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1663.291735                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            41248897                       # Total number of references to valid blocks.
@@ -737,8 +734,6 @@ system.cpu.icache.blocked::no_mshrs                30                       # nu
 system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    69.666667                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          305                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         6515                       # number of writebacks
 system.cpu.icache.writebacks::total              6515                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4088                       # number of ReadReq MSHR hits
@@ -771,7 +766,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640
 system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         2796.844278                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              11471                       # Total number of references to valid blocks.
@@ -888,8 +882,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          500                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total          500                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1507                       # number of ReadExReq MSHR misses
@@ -946,7 +938,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66562.411598
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66037.600221                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67493.379107                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66562.411598                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        18206                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests         7138                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests          549                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.