diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/long/se/70.twolf | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/long/se/70.twolf')
7 files changed, 2422 insertions, 2274 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 38e101aaf..3a5076b7f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.052167 # Nu sim_ticks 52167245000 # Number of ticks simulated final_tick 52167245000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 231551 # Simulator instruction rate (inst/s) -host_op_rate 231551 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131435822 # Simulator tick rate (ticks/s) -host_mem_usage 240584 # Number of bytes of host memory used -host_seconds 396.90 # Real time elapsed on the host +host_inst_rate 368966 # Simulator instruction rate (inst/s) +host_op_rate 368966 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 209437459 # Simulator tick rate (ticks/s) +host_mem_usage 299464 # Number of bytes of host memory used +host_seconds 249.08 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 386 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -182,26 +182,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.254620 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 211.254822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.143137 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 322 33.06% 33.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 190 19.51% 52.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96 9.86% 62.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 102 10.47% 72.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 61 6.26% 79.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 36 3.70% 82.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 25 2.57% 85.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 2.57% 87.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 117 12.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 974 # Bytes accessed per row activation -system.physmem.totQLat 31955000 # Total ticks spent queuing -system.physmem.totMemAccLat 131667500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 972 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.971193 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 211.834828 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.374999 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 320 32.92% 32.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 191 19.65% 52.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 96 9.88% 62.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 99 10.19% 72.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 63 6.48% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 36 3.70% 82.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 24 2.47% 85.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 26 2.67% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 117 12.04% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 972 # Bytes accessed per row activation +system.physmem.totQLat 32099750 # Total ticks spent queuing +system.physmem.totMemAccLat 131812250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26590000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6008.84 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6036.06 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24758.84 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24786.06 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.52 # Average system read bandwidth in MiByte/s @@ -212,43 +212,48 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4336 # Number of row buffer hits during reads +system.physmem.readRowHits 4338 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.53 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 9809545.60 # Average gap between requests -system.physmem.pageHitRate 81.53 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49062382500 # Time in different power states -system.physmem.memoryStateTime::REF 1741740000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1356240000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3530520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3787560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1926375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2066625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 19827600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 21216000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3406843440 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3406843440 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1740241350 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1807017705 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29769681750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29711106000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34942051035 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34952037330 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.896806 # Core power per rank (mW) -system.physmem.averagePower::1 670.088260 # Core power per rank (mW) -system.cpu.branchPred.lookups 11476347 # Number of BP lookups +system.physmem.pageHitRate 81.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3530520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1926375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19827600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3406843440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1740830445 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29769165000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34942123380 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.898193 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49520504500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1741740000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 898118000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3772440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2058375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3406843440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1807143390 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29710995750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34952029395 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.088108 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49425818250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1741740000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 995309750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 11476348 # Number of BP lookups system.cpu.branchPred.condPredicted 8235349 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 785844 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 6672654 # Number of BTB lookups system.cpu.branchPred.BTBHits 5371509 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 80.500338 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1176736 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 1176737 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -267,10 +272,10 @@ system.cpu.dtb.data_hits 26977004 # DT system.cpu.dtb.data_misses 47407 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 27024411 # DTB accesses -system.cpu.itb.fetch_hits 23068125 # ITB hits +system.cpu.itb.fetch_hits 23068130 # ITB hits system.cpu.itb.fetch_misses 88 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 23068213 # ITB accesses +system.cpu.itb.fetch_accesses 23068218 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,15 +298,15 @@ system.cpu.discardedOps 2153944 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.135266 # CPI: cycles per instruction system.cpu.ipc 0.880851 # IPC: instructions per cycle -system.cpu.tickCycles 102681426 # Number of cycles that the object actually ticked -system.cpu.idleCycles 1653064 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 102681434 # Number of cycles that the object actually ticked +system.cpu.idleCycles 1653056 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.700924 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1448.700214 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26568138 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11913.963229 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.700924 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.700214 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.353687 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.353687 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id @@ -329,14 +334,14 @@ system.cpu.dcache.demand_misses::cpu.inst 3430 # n system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 3430 # number of overall misses system.cpu.dcache.overall_misses::total 3430 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 37712750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37712750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 194587500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 194587500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 232300250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 232300250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 232300250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 232300250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 37684500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37684500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 195045500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 195045500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 232730000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 232730000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 232730000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 232730000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 20070465 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20070465 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses) @@ -353,14 +358,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000129 system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 72664.258189 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72664.258189 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66845.585709 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66845.585709 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67726.020408 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67726.020408 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67726.020408 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67726.020408 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 72609.826590 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72609.826590 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 67002.919959 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67002.919959 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67851.311953 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67851.311953 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67851.311953 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67851.311953 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,14 +392,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 2230 system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 34134000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34134000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 117191500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 117191500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 151325500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 151325500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 151325500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151325500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 34103500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34103500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 117640500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 117640500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 151744000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 151744000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 151744000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 151744000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses @@ -403,24 +408,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 70379.381443 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70379.381443 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67158.452722 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67158.452722 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67858.968610 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67858.968610 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67858.968610 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67858.968610 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 70316.494845 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70316.494845 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67415.759312 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67415.759312 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68046.636771 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68046.636771 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13871 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.666168 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23052289 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1640.665289 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23052294 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15835 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1455.780802 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1455.781118 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.666168 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801107 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801107 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.665289 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801106 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801106 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id @@ -428,44 +433,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 669 system.cpu.icache.tags.age_task_id_blocks_1024::3 148 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 948 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 46152085 # Number of tag accesses -system.cpu.icache.tags.data_accesses 46152085 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23052289 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23052289 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23052289 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23052289 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23052289 # number of overall hits -system.cpu.icache.overall_hits::total 23052289 # number of overall hits +system.cpu.icache.tags.tag_accesses 46152095 # Number of tag accesses +system.cpu.icache.tags.data_accesses 46152095 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23052294 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23052294 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23052294 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23052294 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23052294 # number of overall hits +system.cpu.icache.overall_hits::total 23052294 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15836 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15836 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15836 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15836 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15836 # number of overall misses system.cpu.icache.overall_misses::total 15836 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 386603500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 386603500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 386603500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 386603500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 386603500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 386603500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 23068125 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 23068125 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 23068125 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 23068125 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 23068125 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 23068125 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 386327750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 386327750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 386327750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 386327750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 386327750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 386327750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 23068130 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 23068130 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 23068130 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 23068130 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 23068130 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 23068130 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000686 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000686 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000686 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000686 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000686 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000686 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24412.951503 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24412.951503 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24412.951503 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24412.951503 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24412.951503 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24412.951503 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24395.538646 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24395.538646 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24395.538646 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24395.538646 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24395.538646 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24395.538646 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -480,33 +485,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15836 system.cpu.icache.demand_mshr_misses::total 15836 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15836 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15836 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353567500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 353567500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353567500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 353567500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353567500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 353567500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353292250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 353292250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353292250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 353292250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353292250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 353292250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000686 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000686 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22326.818641 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22326.818641 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22326.818641 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22326.818641 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22326.818641 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22326.818641 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22309.437358 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22309.437358 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22309.437358 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22309.437358 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22309.437358 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22309.437358 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2479.834280 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2479.833240 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 12735 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3665 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 3.474761 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 17.780071 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2462.054210 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2462.053168 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075136 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.075679 # Average percentage of cache occupancy @@ -537,14 +542,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 5318 # system.cpu.l2cache.demand_misses::total 5318 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 5318 # number of overall misses system.cpu.l2cache.overall_misses::total 5318 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 244164500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 244164500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 115186000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 115186000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 359350500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 359350500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 359350500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 359350500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 243859250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 243859250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 115635000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 115635000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 359494250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 359494250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 359494250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 359494250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 16320 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 16320 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) @@ -563,14 +568,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.294381 system.cpu.l2cache.demand_miss_rate::total 0.294381 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.294381 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.294381 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67842.317310 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67842.317310 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67007.562536 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67007.562536 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67572.489658 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67572.489658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67572.489658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67572.489658 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67757.502084 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67757.502084 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67268.760908 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67268.760908 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67599.520496 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67599.520496 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67599.520496 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67599.520496 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -587,14 +592,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 5318 system.cpu.l2cache.demand_mshr_misses::total 5318 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 5318 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5318 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 198927000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198927000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 93369000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93369000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 292296000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 292296000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 292296000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 292296000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 198623250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198623250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 93817500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93817500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 292440750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 292440750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 292440750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 292440750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.220527 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.220527 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses @@ -603,14 +608,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.294381 system.cpu.l2cache.demand_mshr_miss_rate::total 0.294381 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.294381 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294381 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55272.853570 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55272.853570 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54315.881326 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54315.881326 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54963.520120 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54963.520120 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54963.520120 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54963.520120 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55188.455126 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55188.455126 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54576.788831 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54576.788831 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54990.739000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54990.739000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 16320 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 16320 # Transaction distribution @@ -637,9 +642,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 18172 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 9193000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24435500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24435250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3734500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3734000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 3599 # Transaction distribution system.membus.trans_dist::ReadResp 3599 # Transaction distribution @@ -660,9 +665,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5318 # Request fanout histogram -system.membus.reqLayer0.occupancy 6477500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6478000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50028000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 50027750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 3e567522b..fbd001a0c 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.022159 # Nu sim_ticks 22159411000 # Number of ticks simulated final_tick 22159411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173006 # Simulator instruction rate (inst/s) -host_op_rate 173006 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45541949 # Simulator tick rate (ticks/s) -host_mem_usage 243048 # Number of bytes of host memory used -host_seconds 486.57 # Real time elapsed on the host +host_inst_rate 210811 # Simulator instruction rate (inst/s) +host_op_rate 210811 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55493646 # Simulator tick rate (ticks/s) +host_mem_usage 299980 # Number of bytes of host memory used +host_seconds 399.31 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 35 4.04% 80.48% # By system.physmem.bytesPerActivate::896-1023 46 5.31% 85.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 123 14.20% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 866 # Bytes accessed per row activation -system.physmem.totQLat 41291750 # Total ticks spent queuing -system.physmem.totMemAccLat 139391750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 41292000 # Total ticks spent queuing +system.physmem.totMemAccLat 139392000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7892.15 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7892.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26642.15 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26642.20 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.11 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.11 # Average system read bandwidth in MiByte/s @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 83.22 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 4235344.32 # Average gap between requests system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 20543925500 # Time in different power states -system.physmem.memoryStateTime::REF 739700000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 868697500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3137400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3341520 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1711875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1823250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 19453200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 20802600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1446853200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1446853200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 893934990 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 919865430 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 12507131250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 12484385250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 14872221915 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 14877071250 # Total energy per rank (pJ) -system.physmem.averagePower::0 671.367239 # Core power per rank (mW) -system.physmem.averagePower::1 671.586150 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 3523 # Transaction distribution -system.membus.trans_dist::ReadResp 3523 # Transaction distribution -system.membus.trans_dist::ReadExReq 1709 # Transaction distribution -system.membus.trans_dist::ReadExResp 1709 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5232 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5232 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5232 # Request fanout histogram -system.membus.reqLayer0.occupancy 6530000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 48921000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 3137400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1711875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19453200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1446853200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 894020490 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12507056250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14872232415 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.367713 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20804380500 # Time in different power states +system.physmem_0.memoryStateTime::REF 739700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 608242500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20802600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1446853200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 920005650 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12484262250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14877088470 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.586927 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20766250250 # Time in different power states +system.physmem_1.memoryStateTime::REF 739700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 646430250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 16298030 # Number of BP lookups system.cpu.branchPred.condPredicted 11843884 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 974423 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 85.866424 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1608574 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 439 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -314,22 +296,22 @@ system.cpu.workload.num_syscalls 389 # Nu system.cpu.numCycles 44318823 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16859440 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 16859439 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 139373095 # Number of instructions fetch has processed system.cpu.fetch.Branches 16298030 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 9227373 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 26218420 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 26218422 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2029202 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 2359 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 16127186 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 380559 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44094962 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 44094963 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 3.160749 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.432020 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19653197 44.57% 44.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19653198 44.57% 44.57% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2660337 6.03% 50.60% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 1339868 3.04% 53.64% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 1948475 4.42% 58.06% # Number of instructions fetched each cycle (Total) @@ -341,11 +323,11 @@ system.cpu.fetch.rateDist::8 11866174 26.91% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44094962 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 44094963 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.367745 # Number of branch fetches per cycle system.cpu.fetch.rate 3.144783 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13063436 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8246929 # Number of cycles decode is blocked +system.cpu.decode.IdleCycles 13063435 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8246931 # Number of cycles decode is blocked system.cpu.decode.RunCycles 19674377 # Number of cycles decode is running system.cpu.decode.UnblockCycles 2107337 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1002883 # Number of cycles decode is squashing @@ -354,16 +336,16 @@ system.cpu.decode.BranchMispred 12053 # Nu system.cpu.decode.DecodedInsts 133445502 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 49010 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1002883 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 14206626 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4728528 # Number of cycles rename is blocking +system.cpu.rename.IdleCycles 14206625 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4728440 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 8922 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 20521133 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3626870 # Number of cycles rename is unblocking +system.cpu.rename.UnblockCycles 3626960 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 129917938 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 71936 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1987853 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 1348485 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 46116 # Number of times rename has blocked due to SQ full +system.cpu.rename.SQFullEvents 46206 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 95420653 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 168813407 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 161260201 # Number of integer rename lookups @@ -384,23 +366,23 @@ system.cpu.iq.iqSquashedInstsIssued 120259 # Nu system.cpu.iq.iqSquashedInstsExamined 27967887 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 21886191 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1551 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44094962 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 44094963 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.270157 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 2.096378 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 11535006 26.16% 26.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7754469 17.59% 43.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7754470 17.59% 43.75% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 7555421 17.13% 60.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 5737104 13.01% 73.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4489383 10.18% 84.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2977389 6.75% 90.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4489384 10.18% 84.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2977388 6.75% 90.82% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 2013844 4.57% 95.39% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 1160432 2.63% 98.02% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 871914 1.98% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44094962 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44094963 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 479018 20.14% 20.14% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available @@ -473,7 +455,7 @@ system.cpu.iq.FU_type_0::total 100102500 # Ty system.cpu.iq.rate 2.258690 # Inst issue rate system.cpu.iq.fu_busy_cnt 2377986 # FU busy when requested system.cpu.iq.fu_busy_rate 0.023756 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 231175585 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 231175586 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 131029945 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 90008848 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 15622622 # Number of floating instruction queue reads @@ -493,15 +475,15 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 42761 # system.cpu.iew.lsq.thread0.cacheBlocked 2468 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1002883 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3707628 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 461879 # Number of cycles IEW is unblocking +system.cpu.iew.iewBlockCycles 3707612 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 461807 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 123638491 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 278104 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 27105677 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 8747640 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 1940 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 39979 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 414957 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 414885 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 42241 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 554445 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 525545 # Number of branches that were predicted not taken incorrectly @@ -517,8 +499,8 @@ system.cpu.iew.exec_stores 7162603 # Nu system.cpu.iew.exec_rate 2.227716 # Inst execution rate system.cpu.iew.wb_sent 97918369 # cumulative count of insts sent to commit system.cpu.iew.wb_count 97175588 # cumulative count of insts written-back -system.cpu.iew.wb_producers 67088119 # num instructions producing a value -system.cpu.iew.wb_consumers 95122375 # num instructions consuming a value +system.cpu.iew.wb_producers 67088120 # num instructions producing a value +system.cpu.iew.wb_consumers 95122376 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.192648 # insts written-back per cycle system.cpu.iew.wb_fanout 0.705282 # average fanout of values written-back @@ -526,11 +508,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 31736961 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 962705 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39466886 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 39466887 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.328612 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.908948 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14969499 37.93% 37.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14969500 37.93% 37.93% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 8597582 21.78% 59.71% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 3898491 9.88% 69.59% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 1956472 4.96% 74.55% # Number of insts commited each cycle @@ -542,7 +524,7 @@ system.cpu.commit.committed_per_cycle::8 6211472 15.74% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39466886 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39466887 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -590,10 +572,10 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction system.cpu.commit.bw_lim_events 6211472 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 156894390 # The number of ROB reads +system.cpu.rob.rob_reads 156894391 # The number of ROB reads system.cpu.rob.rob_writes 251967276 # The number of ROB writes system.cpu.timesIdled 4539 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 223861 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 223860 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.cpi 0.526479 # CPI: Cycles Per Instruction @@ -606,42 +588,149 @@ system.cpu.fp_regfile_reads 6250590 # nu system.cpu.fp_regfile_writes 6153622 # number of floating regfile writes system.cpu.misc_regfile_reads 718773 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 12032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 12032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 110 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1735 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1735 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23038 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27644 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 888128 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 13877 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 13877 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13877 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17856500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3547750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.dcache.tags.replacements 160 # number of replacements +system.cpu.dcache.tags.tagsinuse 1457.564933 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28680753 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2248 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12758.342082 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.564933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355851 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355851 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 57382576 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57382576 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22187756 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22187756 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492735 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492735 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 262 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 262 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28680491 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28680491 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28680491 # number of overall hits +system.cpu.dcache.overall_hits::total 28680491 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1042 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1042 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8368 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8368 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9410 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9410 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9410 # number of overall misses +system.cpu.dcache.overall_misses::total 9410 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65475750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65475750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 523849968 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 523849968 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 589325718 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 589325718 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 589325718 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 589325718 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22188798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22188798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 263 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 263 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28689901 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28689901 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28689901 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28689901 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001287 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001287 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003802 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003802 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62836.612284 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62836.612284 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62601.573614 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62601.573614 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62627.600213 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62627.600213 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62627.600213 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62627.600213 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29227 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 416 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 894 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.692394 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 208 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 110 # number of writebacks +system.cpu.dcache.writebacks::total 110 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 529 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 529 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7163 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7163 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7163 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7163 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2247 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2247 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2247 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2247 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36153000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36153000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125731745 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 125731745 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161884745 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 161884745 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161884745 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161884745 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003802 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003802 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70473.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70473.684211 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72509.656863 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72509.656863 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72044.835336 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72044.835336 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72044.835336 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72044.835336 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9583 # number of replacements -system.cpu.icache.tags.tagsinuse 1600.631019 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1600.631053 # Cycle average of tags in use system.cpu.icache.tags.total_refs 16112652 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11519 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1398.789131 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1600.631019 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1600.631053 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.781558 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.781558 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id @@ -665,12 +754,12 @@ system.cpu.icache.demand_misses::cpu.inst 14533 # n system.cpu.icache.demand_misses::total 14533 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 14533 # number of overall misses system.cpu.icache.overall_misses::total 14533 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 419606250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 419606250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 419606250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 419606250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 419606250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 419606250 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 419570250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 419570250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 419570250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 419570250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 419570250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 419570250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 16127185 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 16127185 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 16127185 # number of demand (read+write) accesses @@ -683,12 +772,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000901 system.cpu.icache.demand_miss_rate::total 0.000901 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000901 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000901 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28872.651896 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28872.651896 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28872.651896 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28872.651896 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28872.651896 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28872.651896 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28870.174775 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28870.174775 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28870.174775 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28870.174775 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28870.174775 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28870.174775 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -709,34 +798,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11519 system.cpu.icache.demand_mshr_misses::total 11519 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11519 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11519 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306578000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 306578000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306578000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 306578000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306578000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 306578000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306551250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 306551250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306551250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 306551250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306551250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 306551250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000714 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000714 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000714 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26614.983940 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26614.983940 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26614.983940 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26614.983940 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26614.983940 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26614.983940 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26612.661689 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26612.661689 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26612.661689 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26612.661689 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26612.661689 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26612.661689 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2401.991277 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2401.991328 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8524 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3591 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.373712 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.703654 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.347182 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 376.940441 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.703660 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.347225 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 376.940444 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061259 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.011503 # Average percentage of cache occupancy @@ -774,17 +863,17 @@ system.cpu.l2cache.demand_misses::total 5232 # nu system.cpu.l2cache.overall_misses::cpu.inst 3065 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2167 # number of overall misses system.cpu.l2cache.overall_misses::total 5232 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210511250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35108000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 245619250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 123622250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 123622250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 210511250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 158730250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 369241500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 210511250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 158730250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 369241500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210484500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35100000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 245584500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 123658250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 123658250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 210484500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 158758250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 369242750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 210484500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 158758250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 369242750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 11519 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 513 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 12032 # number of ReadReq accesses(hits+misses) @@ -809,17 +898,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.380039 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266082 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963968 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.380039 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68682.300163 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76655.021834 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69718.776611 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72336.015214 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72336.015214 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68682.300163 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73248.846331 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70573.681193 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68682.300163 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73248.846331 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70573.681193 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68673.572594 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76637.554585 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69708.912858 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72357.080164 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72357.080164 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68673.572594 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73261.767420 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70573.920107 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68673.572594 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73261.767420 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70573.920107 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -839,17 +928,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5232 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3065 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2167 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5232 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171684750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29423500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201108250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 102762250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 102762250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171684750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132185750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 303870500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171684750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132185750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 303870500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171659500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29415000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201074500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 102798250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 102798250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171659500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132213250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 303872750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171659500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132213250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 303872750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892788 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.292803 # mshr miss rate for ReadReq accesses @@ -861,153 +950,69 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.380039 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963968 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.380039 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56014.600326 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64243.449782 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57084.374113 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60130.046811 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60130.046811 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56014.600326 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60999.423166 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58079.224006 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56014.600326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60999.423166 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58079.224006 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56006.362153 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64224.890830 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57074.794209 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60151.111761 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60151.111761 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56006.362153 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61012.113521 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58079.654052 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56006.362153 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61012.113521 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58079.654052 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 160 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.564755 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28680753 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2248 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12758.342082 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.564755 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355851 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355851 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57382576 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57382576 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22187756 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22187756 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492735 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492735 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 262 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 262 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28680491 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28680491 # 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number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65491750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 523624968 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 523624968 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 589116718 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 589116718 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 589116718 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 589116718 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22188798 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22188798 # 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miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001287 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003802 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003802 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62851.967370 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62851.967370 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62574.685468 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62574.685468 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62605.389798 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62605.389798 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62605.389798 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62605.389798 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29209 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 416 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 894 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.672260 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 208 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 110 # number of writebacks -system.cpu.dcache.writebacks::total 110 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 529 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 529 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7163 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7163 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7163 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7163 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2247 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2247 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2247 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2247 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36161000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36161000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125695745 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 125695745 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161856745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161856745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161856745 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161856745 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003802 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003802 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70489.278752 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70489.278752 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72488.895617 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72488.895617 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72032.374277 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72032.374277 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72032.374277 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72032.374277 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 12032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 110 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1735 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1735 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23038 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4606 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27644 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 888128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 13877 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 13877 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 13877 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 17856250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3547750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3523 # Transaction distribution +system.membus.trans_dist::ReadResp 3523 # Transaction distribution +system.membus.trans_dist::ReadExReq 1709 # Transaction distribution +system.membus.trans_dist::ReadExResp 1709 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5232 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5232 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5232 # Request fanout histogram +system.membus.reqLayer0.occupancy 6529000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 48920250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index be651ff21..75d7eb795 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131746 # Nu sim_ticks 131745950000 # Number of ticks simulated final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190259 # Simulator instruction rate (inst/s) -host_op_rate 200564 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 145463120 # Simulator tick rate (ticks/s) -host_mem_usage 256996 # Number of bytes of host memory used -host_seconds 905.70 # Real time elapsed on the host +host_inst_rate 246838 # Simulator instruction rate (inst/s) +host_op_rate 260207 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 188720644 # Simulator tick rate (ticks/s) +host_mem_usage 315756 # Number of bytes of host memory used +host_seconds 698.10 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated sim_ops 181650742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 14 1.54% 91.67% # By system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation -system.physmem.totQLat 28129500 # Total ticks spent queuing -system.physmem.totMemAccLat 100635750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 28130750 # Total ticks spent queuing +system.physmem.totMemAccLat 100637000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7274.24 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7274.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26024.24 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26024.57 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -218,29 +218,34 @@ system.physmem.readRowHitRate 76.29 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 34069268.55 # Average gap between requests system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 125856871250 # Time in different power states -system.physmem.memoryStateTime::REF 4399200000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1487617250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3092040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3787560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1687125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2066625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 16177200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 13767000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 8604835200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 8604835200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 3575888730 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 3595740120 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 75909421500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 75892008000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 88111101795 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 88112204505 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.807404 # Core power per rank (mW) -system.physmem.averagePower::1 668.815774 # Core power per rank (mW) +system.physmem_0.actEnergy 3092040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1687125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3575900700 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75909402750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88111095015 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.807422 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126280313250 # Time in different power states +system.physmem_0.memoryStateTime::REF 4399200000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1064296750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3787560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2066625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3595739265 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75892008750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88112204400 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.815773 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126251429250 # Time in different power states +system.physmem_1.memoryStateTime::REF 4399200000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1093059250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 49935043 # Number of BP lookups system.cpu.branchPred.condPredicted 39664695 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5744224 # Number of conditional branches incorrect @@ -251,6 +256,14 @@ system.cpu.branchPred.BTBHitPct 95.508866 # BT system.cpu.branchPred.usedRAS 1908457 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -272,6 +285,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -293,6 +314,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -314,6 +343,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -348,12 +385,12 @@ system.cpu.ipc 0.653978 # IP system.cpu.tickCycles 257145198 # Number of cycles that the object actually ticked system.cpu.idleCycles 6346702 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.772721 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1377.772724 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40762987 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1377.772721 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 1377.772724 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.336370 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id @@ -387,12 +424,12 @@ system.cpu.dcache.overall_misses::cpu.inst 2436 # system.cpu.dcache.overall_misses::total 2436 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.inst 54011984 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 54011984 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115580250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 115580250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 169592234 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 169592234 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 169592234 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 169592234 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115610250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 115610250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 169622234 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 169622234 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 169622234 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 169622234 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 28356322 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 28356322 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses) @@ -415,12 +452,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst 0.000060 system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68196.949495 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70304.288321 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70304.288321 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69619.143678 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69619.143678 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69619.143678 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69619.143678 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70322.536496 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70322.536496 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69631.458949 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69631.458949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69631.458949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69631.458949 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,12 +486,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst 1810 system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47293264 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 47293264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76493500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 76493500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 123786764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 123786764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 123786764 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 123786764 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76508500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 76508500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 123801764 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 123801764 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 123801764 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 123801764 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses @@ -465,20 +502,20 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000044 system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66423.123596 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66423.123596 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69666.211293 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69666.211293 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68390.477348 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68390.477348 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68390.477348 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68390.477348 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69679.872495 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69679.872495 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68398.764641 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68398.764641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2909 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.880839 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1424.880841 # Cycle average of tags in use system.cpu.icache.tags.total_refs 71614329 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4705 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15220.898831 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.880839 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.880841 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.695743 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.695743 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id @@ -502,12 +539,12 @@ system.cpu.icache.demand_misses::cpu.inst 4706 # n system.cpu.icache.demand_misses::total 4706 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4706 # number of overall misses system.cpu.icache.overall_misses::total 4706 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 186392247 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 186392247 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 186392247 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 186392247 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 186392247 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 186392247 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 186377497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 186377497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 186377497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 186377497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 186377497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 186377497 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 71619035 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 71619035 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 71619035 # number of demand (read+write) accesses @@ -520,12 +557,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39607.362303 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39607.362303 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39607.362303 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39607.362303 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39607.362303 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39607.362303 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39604.228007 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39604.228007 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39604.228007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39604.228007 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,33 +577,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4706 system.cpu.icache.demand_mshr_misses::total 4706 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4706 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4706 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176061753 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 176061753 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176061753 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 176061753 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176061753 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 176061753 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176047503 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 176047503 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176047503 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 176047503 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176047503 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 176047503 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37412.187208 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37412.187208 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37412.187208 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37412.187208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37412.187208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37412.187208 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37409.159159 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37409.159159 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2001.520468 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2001.520471 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2624 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.942190 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 3.029184 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.491284 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.491287 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060989 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.061082 # Average percentage of cache occupancy @@ -597,14 +634,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 3885 # system.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3885 # number of overall misses system.cpu.l2cache.overall_misses::total 3885 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191698500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 191698500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75314000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 75314000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 267012500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 267012500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 267012500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 267012500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191684250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 191684250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75329000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 75329000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 267013250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 267013250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 267013250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 267013250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 5418 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5418 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) @@ -623,14 +660,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.596225 system.cpu.l2cache.demand_miss_rate::total 0.596225 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.596225 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.596225 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68586.225403 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68586.225403 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69095.412844 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.412844 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68729.086229 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68729.086229 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68729.086229 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68729.086229 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68581.127013 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68581.127013 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69109.174312 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69109.174312 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68729.279279 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68729.279279 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68729.279279 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68729.279279 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -653,14 +690,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 3868 system.cpu.l2cache.demand_mshr_misses::total 3868 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3868 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3868 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 155803750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155803750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 61486500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61486500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 217290250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 217290250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 217290250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 217290250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 155790000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155790000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 61501500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61501500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 217291500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 217291500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 217291500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 217291500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512735 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.512735 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses @@ -669,14 +706,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.593616 system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.593616 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56084.863211 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56084.863211 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56409.633028 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56409.633028 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56176.383144 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.383144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56176.383144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.383144 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56079.913607 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56079.913607 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56423.394495 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56423.394495 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56176.706308 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56176.706308 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5417 # Transaction distribution @@ -707,7 +744,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value 5 # system.cpu.toL2Bus.snoop_fanout::total 6532 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 3282000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7517747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7517497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2996736 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) @@ -732,7 +769,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 3867 # Request fanout histogram system.membus.reqLayer0.occupancy 4723500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 36361250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 36361000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index eede9a19d..30df36f38 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.084956 # Number of seconds simulated -sim_ticks 84955935500 # Number of ticks simulated -final_tick 84955935500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085008 # Number of seconds simulated +sim_ticks 85008313500 # Number of ticks simulated +final_tick 85008313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133775 # Simulator instruction rate (inst/s) -host_op_rate 141021 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65959289 # Simulator tick rate (ticks/s) -host_mem_usage 311648 # Number of bytes of host memory used -host_seconds 1288.01 # Real time elapsed on the host +host_inst_rate 130085 # Simulator instruction rate (inst/s) +host_op_rate 137131 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64179279 # Simulator tick rate (ticks/s) +host_mem_usage 313784 # Number of bytes of host memory used +host_seconds 1324.54 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 181635953 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 18240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 35328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 268480 # Number of bytes read from this memory -system.physmem.bytes_read::total 322048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18240 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 285 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 552 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 4195 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5032 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 214700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 415839 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 3160227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3790765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 214700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 214700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 214700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 415839 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 3160227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3790765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5032 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 127168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 48000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71360 # Number of bytes read from this memory +system.physmem.bytes_read::total 246528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 127168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 127168 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1987 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 750 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1115 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3852 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1495948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 564651 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 839447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2900046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1495948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1495948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1495948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 564651 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 839447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2900046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3852 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5032 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3852 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 322048 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 246528 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 322048 # Total read bytes from the system interface side +system.physmem.bytesReadSys 246528 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 395 # Per bank write bursts -system.physmem.perBankRdBursts::1 288 # Per bank write bursts -system.physmem.perBankRdBursts::2 188 # Per bank write bursts -system.physmem.perBankRdBursts::3 388 # Per bank write bursts -system.physmem.perBankRdBursts::4 399 # Per bank write bursts -system.physmem.perBankRdBursts::5 367 # Per bank write bursts -system.physmem.perBankRdBursts::6 381 # Per bank write bursts -system.physmem.perBankRdBursts::7 279 # Per bank write bursts -system.physmem.perBankRdBursts::8 314 # Per bank write bursts -system.physmem.perBankRdBursts::9 341 # Per bank write bursts -system.physmem.perBankRdBursts::10 369 # Per bank write bursts -system.physmem.perBankRdBursts::11 260 # Per bank write bursts -system.physmem.perBankRdBursts::12 244 # Per bank write bursts -system.physmem.perBankRdBursts::13 279 # Per bank write bursts -system.physmem.perBankRdBursts::14 295 # Per bank write bursts -system.physmem.perBankRdBursts::15 245 # Per bank write bursts +system.physmem.perBankRdBursts::0 309 # Per bank write bursts +system.physmem.perBankRdBursts::1 223 # Per bank write bursts +system.physmem.perBankRdBursts::2 142 # Per bank write bursts +system.physmem.perBankRdBursts::3 310 # Per bank write bursts +system.physmem.perBankRdBursts::4 300 # Per bank write bursts +system.physmem.perBankRdBursts::5 302 # Per bank write bursts +system.physmem.perBankRdBursts::6 262 # Per bank write bursts +system.physmem.perBankRdBursts::7 237 # Per bank write bursts +system.physmem.perBankRdBursts::8 252 # Per bank write bursts +system.physmem.perBankRdBursts::9 218 # Per bank write bursts +system.physmem.perBankRdBursts::10 293 # Per bank write bursts +system.physmem.perBankRdBursts::11 194 # Per bank write bursts +system.physmem.perBankRdBursts::12 193 # Per bank write bursts +system.physmem.perBankRdBursts::13 212 # Per bank write bursts +system.physmem.perBankRdBursts::14 211 # Per bank write bursts +system.physmem.perBankRdBursts::15 194 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 84955621000 # Total gap between requests +system.physmem.totGap 85008170000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5032 # Read request sizes (log2) +system.physmem.readPktSize::6 3852 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 484 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 315 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 895 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -190,98 +190,88 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 689 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 467.413643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 304.114713 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 362.347713 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 143 20.75% 20.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 123 17.85% 38.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 63 9.14% 47.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 69 10.01% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 45 6.53% 64.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 51 7.40% 71.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 42 6.10% 77.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21 3.05% 80.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 132 19.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 689 # Bytes accessed per row activation -system.physmem.totQLat 114920157 # Total ticks spent queuing -system.physmem.totMemAccLat 209270157 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 25160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22837.87 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 321.936842 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 203.366462 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 304.047629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 237 31.18% 31.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 182 23.95% 55.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 69 9.08% 64.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 96 12.63% 76.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 4.61% 81.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 45 5.92% 87.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 2.37% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 14 1.84% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 64 8.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 760 # Bytes accessed per row activation +system.physmem.totQLat 36289181 # Total ticks spent queuing +system.physmem.totMemAccLat 108514181 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19260000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9420.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41587.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28170.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.79 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.97 # Average read queue length when enqueuing +system.physmem.avgRdQLen 3.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4343 # Number of row buffer hits during reads +system.physmem.readRowHits 3085 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.31 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 16883072.54 # Average gap between requests -system.physmem.pageHitRate 86.31 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 81214099250 # Time in different power states -system.physmem.memoryStateTime::REF 2836600000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 905088250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2585520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2623320 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1410750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1431375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 20943000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 18306600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 5548898160 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 5548898160 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 2301036705 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 2237438385 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 48955167000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 49010955000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 56830041135 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 56819652840 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.934726 # Core power per rank (mW) -system.physmem.averagePower::1 668.812447 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 4821 # Transaction distribution -system.membus.trans_dist::ReadResp 4821 # Transaction distribution -system.membus.trans_dist::ReadExReq 211 # Transaction distribution -system.membus.trans_dist::ReadExResp 211 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10064 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 322048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 322048 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5032 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5032 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5032 # Request fanout histogram -system.membus.reqLayer0.occupancy 5681641 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 46027985 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 85925623 # Number of BP lookups -system.cpu.branchPred.condPredicted 68405598 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6015157 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40113883 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39024614 # Number of BTB hits +system.physmem.avgGap 22068579.96 # Average gap between requests +system.physmem.pageHitRate 80.09 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2721600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1485000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16239600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5551949520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2339255205 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48949672500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 56861323425 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.935094 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81434793722 # Time in different power states +system.physmem_0.memoryStateTime::REF 2838420000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 733662278 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3001320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1637625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13540800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5551949520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2301878880 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 48982450500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56854458645 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.854443 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 81486384408 # Time in different power states +system.physmem_1.memoryStateTime::REF 2838420000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 678791592 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 85929478 # Number of BP lookups +system.cpu.branchPred.condPredicted 68409655 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6016514 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 40103730 # Number of BTB lookups +system.cpu.branchPred.BTBHits 39019729 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.284559 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3701789 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81904 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.297007 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3701200 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81899 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -303,6 +293,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -324,6 +322,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -345,6 +351,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -367,96 +381,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 169911872 # number of cpu cycles simulated +system.cpu.numCycles 170016628 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5595281 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349266175 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85925623 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42726403 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158254745 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12044333 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 129 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingQuiesceStallCycles 37 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 592 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78952832 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 17522 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169872950 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.151005 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.046766 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5612512 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349284796 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85929478 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42720929 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158258026 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12046973 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1522 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 2068 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78953849 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 17938 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169897637 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.150791 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.046975 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17324644 10.20% 10.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30203623 17.78% 27.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31840188 18.74% 46.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90504495 53.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17345965 10.21% 10.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30201314 17.78% 27.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31838054 18.74% 46.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90512304 53.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169872950 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.505707 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.055573 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17551129 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17096204 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122646615 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6731659 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5847343 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11137012 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 190128 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306601093 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27639828 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5847343 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37738327 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8403981 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 578579 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108919553 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8385167 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278647204 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13415116 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3048397 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 841923 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2187656 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 31854 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 78402 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483062515 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1196895890 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297562467 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3006395 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169897637 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.505418 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.054416 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17565023 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17095500 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 122663721 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6724834 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5848559 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11136257 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 190151 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 306621954 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27645544 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5848559 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37752791 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8406678 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 578098 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108929543 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8381968 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 278665579 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13416120 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3045260 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 842372 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2187359 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 31268 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 80203 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 483123422 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1196973277 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 297590130 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3005585 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190085586 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23528 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23420 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13351603 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34138378 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14478835 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2550837 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1806189 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 264810642 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 190146493 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23524 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23418 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13341047 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 34139788 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14476953 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2546690 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1793951 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 264825375 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 45850 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214907655 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5190996 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82629036 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219889900 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 214906973 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5192109 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82644277 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 219958197 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 634 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169872950 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.265108 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 169897637 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.264920 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017502 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52803027 31.08% 31.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36096104 21.25% 52.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65778237 38.72% 91.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13576092 7.99% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1571163 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47813 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 514 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52826553 31.09% 31.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36096362 21.25% 52.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65782146 38.72% 91.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13572889 7.99% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1571303 0.92% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47864 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 520 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169872950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169897637 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35609099 66.11% 66.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 152890 0.28% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35601312 66.11% 66.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 152935 0.28% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.39% # attempts to use FU when none available @@ -475,22 +489,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.39% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1075 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35725 0.07% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 330 0.00% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1069 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35738 0.07% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 318 0.00% 66.46% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 815 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34388 0.06% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 217 0.00% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 812 0.00% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34382 0.06% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 216 0.00% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14076935 26.13% 92.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3950981 7.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14078938 26.14% 92.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3947834 7.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167347451 77.87% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918969 0.43% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167350726 77.87% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 918985 0.43% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued @@ -509,93 +523,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33024 0.02% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33019 0.02% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165192 0.08% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245769 0.11% 78.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165190 0.08% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245718 0.11% 78.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460683 0.21% 78.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206710 0.10% 78.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71622 0.03% 78.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460475 0.21% 78.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206696 0.10% 78.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32005523 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13376375 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32004909 14.89% 93.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13373295 6.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214907655 # Type of FU issued -system.cpu.iq.rate 1.264818 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53862656 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.250632 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654786826 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 345480396 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204601887 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3955086 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2012108 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806636 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266634716 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2135595 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1601086 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214906973 # Type of FU issued +system.cpu.iq.rate 1.264035 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53853755 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.250591 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654805304 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 345511813 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204602678 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3952143 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2010627 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806422 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266627552 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2133176 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1600193 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6242234 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7548 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7115 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1834201 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6243644 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7556 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7106 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1832319 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25938 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 647 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25875 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 661 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5847343 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5682283 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37485 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 264872462 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5848559 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5681569 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 36478 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 264887188 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34138378 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14478835 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 34139788 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14476953 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 23442 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3828 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 30448 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7115 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3233466 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3245683 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6479149 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207525838 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30720478 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7381817 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 3814 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29479 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7106 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3233640 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3247282 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6480922 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207527385 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30721175 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7379588 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15970 # number of nop insts executed -system.cpu.iew.exec_refs 43862877 # number of memory reference insts executed -system.cpu.iew.exec_branches 44936358 # Number of branches executed -system.cpu.iew.exec_stores 13142399 # Number of stores executed -system.cpu.iew.exec_rate 1.221373 # Inst execution rate -system.cpu.iew.wb_sent 206743657 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206408523 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129467920 # num instructions producing a value -system.cpu.iew.wb_consumers 221670950 # num instructions consuming a value +system.cpu.iew.exec_nop 15963 # number of nop insts executed +system.cpu.iew.exec_refs 43860513 # number of memory reference insts executed +system.cpu.iew.exec_branches 44937173 # Number of branches executed +system.cpu.iew.exec_stores 13139338 # Number of stores executed +system.cpu.iew.exec_rate 1.220630 # Inst execution rate +system.cpu.iew.wb_sent 206744227 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206409100 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129466460 # num instructions producing a value +system.cpu.iew.wb_consumers 221676348 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.214798 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584055 # average fanout of values written-back +system.cpu.iew.wb_rate 1.214052 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.584034 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69532618 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69543087 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5840334 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158431709 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.146553 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.646732 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5841587 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158455572 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146380 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.646562 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73650115 46.49% 46.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41279051 26.05% 72.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22553954 14.24% 86.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9627262 6.08% 92.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3547678 2.24% 95.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2148088 1.36% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1282361 0.81% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 989322 0.62% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3353878 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73674398 46.50% 46.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41276379 26.05% 72.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22551197 14.23% 86.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9630660 6.08% 92.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3550983 2.24% 95.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2150131 1.36% 96.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1280461 0.81% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 988669 0.62% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3352694 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158431709 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158455572 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 181650341 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -641,487 +655,505 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction -system.cpu.commit.bw_lim_events 3353878 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3352694 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 406255589 # The number of ROB reads -system.cpu.rob.rob_writes 513821132 # The number of ROB writes -system.cpu.timesIdled 2630 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 38922 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 406291105 # The number of ROB reads +system.cpu.rob.rob_writes 513842853 # The number of ROB writes +system.cpu.timesIdled 3394 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 118991 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 181635953 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.986122 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.986122 # CPI: Total CPI of All Threads -system.cpu.ipc 1.014073 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.014073 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218958580 # number of integer regfile reads -system.cpu.int_regfile_writes 114511116 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904510 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441819 # number of floating regfile writes -system.cpu.cc_regfile_reads 709580018 # number of cc regfile reads -system.cpu.cc_regfile_writes 229533397 # number of cc regfile writes -system.cpu.misc_regfile_reads 59318521 # number of misc regfile reads +system.cpu.cpi 0.986730 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.986730 # CPI: Total CPI of All Threads +system.cpu.ipc 1.013448 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.013448 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218960053 # number of integer regfile reads +system.cpu.int_regfile_writes 114514072 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904445 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441481 # number of floating regfile writes +system.cpu.cc_regfile_reads 709585079 # number of cc regfile reads +system.cpu.cc_regfile_writes 229544416 # number of cc regfile writes +system.cpu.misc_regfile_reads 59313443 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 119664 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 119664 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 64873 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 7801 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8632 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109774 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211691 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 321465 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3512768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8850048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 12362816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 7801 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 200978 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.038815 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.193155 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 193177 96.12% 96.12% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 7801 3.88% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 200978 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 161464494 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82370974 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110177995 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 54375 # number of replacements -system.cpu.icache.tags.tagsinuse 510.661166 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78896017 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54887 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1437.426294 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 84218922500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.661166 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997385 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997385 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 251 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157960533 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157960533 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78896017 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78896017 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78896017 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78896017 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78896017 # number of overall hits -system.cpu.icache.overall_hits::total 78896017 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 56806 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 56806 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 56806 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 56806 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 56806 # number of overall misses -system.cpu.icache.overall_misses::total 56806 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 474677200 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 474677200 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 474677200 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 474677200 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 474677200 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 474677200 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78952823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78952823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78952823 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78952823 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78952823 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78952823 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000719 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000719 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000719 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000719 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000719 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000719 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8356.110270 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8356.110270 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8356.110270 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8356.110270 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8356.110270 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8356.110270 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 16306 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2267 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7.192766 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1919 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1919 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1919 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1919 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1919 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1919 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54887 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 54887 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 54887 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 54887 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 54887 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 54887 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 380604754 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 380604754 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 380604754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 380604754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 380604754 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 380604754 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000695 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000695 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000695 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6934.333339 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6934.333339 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6934.333339 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6934.333339 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6934.333339 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6934.333339 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 435044 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 3068 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 422406 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 3291 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 894 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 5385 # number of hwpf issued -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 26500 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3680.652694 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 181097 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4769 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 37.973789 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 700.245747 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 217.753448 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 276.465568 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2486.187931 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.042740 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.013291 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.016874 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.151745 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.224649 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 3319 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1450 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 45 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 109 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 648 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 26 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 2491 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 987 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.202576 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.088501 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3104105 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3104105 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 54552 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 64413 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 118965 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 64873 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 64873 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8421 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8421 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 54552 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 72834 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 127386 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 54552 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 72834 # number of overall hits -system.cpu.l2cache.overall_hits::total 127386 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 364 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 699 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 211 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 211 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 575 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 910 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 575 # number of overall misses -system.cpu.l2cache.overall_misses::total 910 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24852997 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 26184000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 51036997 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15318999 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 15318999 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24852997 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 41502999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 66355996 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24852997 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 41502999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 66355996 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 54887 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 64777 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 119664 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 64873 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 64873 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 8632 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 8632 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 54887 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 73409 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 128296 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 54887 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 73409 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 128296 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.006103 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.005619 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.005841 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.024444 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.024444 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.006103 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.007833 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.007093 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.006103 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.007833 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.007093 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74188.050746 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71934.065934 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73014.301860 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72601.890995 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72601.890995 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74188.050746 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72179.128696 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72918.676923 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74188.050746 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72179.128696 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72918.676923 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 2973 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 134 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 22.186567 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 50 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 50 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 50 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 285 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 341 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 5385 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 5385 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 211 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 211 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 285 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 552 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 837 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 285 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 552 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 5385 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 6222 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20480998 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22050750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 42531748 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 326822301 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 326822301 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13544999 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13544999 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20480998 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 35595749 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 56076747 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20480998 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 35595749 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 326822301 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 382899048 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005192 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.005264 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.005231 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.024444 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.024444 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005192 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.007520 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.006524 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005192 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.007520 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.048497 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71863.150877 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64664.956012 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67942.089457 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60691.235097 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 60691.235097 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64194.308057 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64194.308057 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71863.150877 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64485.052536 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66997.308244 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71863.150877 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64485.052536 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60691.235097 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61539.544841 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 72897 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.503812 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41115488 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 511.439547 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41117509 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 73409 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.087837 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 471699000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.503812 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999031 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999031 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 560.115367 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 497141250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.439547 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998905 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998905 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 220 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 222 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82528199 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82528199 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28728737 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28728737 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341838 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341838 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82532283 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82532283 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28730746 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28730746 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341850 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341850 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22145 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22145 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41070575 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41070575 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41070936 # number of overall hits -system.cpu.dcache.overall_hits::total 41070936 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89075 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89075 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22449 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22449 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 121 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 121 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 41072596 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41072596 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41072957 # number of overall hits +system.cpu.dcache.overall_hits::total 41072957 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89111 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89111 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22437 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22437 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 262 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 262 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 111524 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 111524 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 111645 # number of overall misses -system.cpu.dcache.overall_misses::total 111645 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 824002993 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 824002993 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 221780748 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 221780748 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2327000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2327000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1045783741 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1045783741 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1045783741 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1045783741 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28817812 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28817812 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 111548 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 111548 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 111666 # number of overall misses +system.cpu.dcache.overall_misses::total 111666 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 835319240 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 835319240 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 222952999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 222952999 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2325000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2325000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1058272239 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1058272239 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1058272239 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1058272239 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28819857 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28819857 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 482 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 482 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41182099 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41182099 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41182581 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41182581 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003091 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003091 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001816 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001816 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.251037 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.251037 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41184144 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41184144 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41184623 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41184623 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003092 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003092 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001815 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001815 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011693 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011693 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002708 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002708 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002709 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002709 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002711 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002711 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9250.665091 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9250.665091 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9879.315248 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9879.315248 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8881.679389 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8881.679389 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9377.207964 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9377.207964 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9367.045018 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9367.045018 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 279 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7362 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 531 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 93 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 13.864407 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9373.918371 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9373.918371 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9936.845345 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9936.845345 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8874.045802 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8874.045802 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9487.146690 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9487.146690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9477.121407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9477.121407 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 122 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7730 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 532 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 61 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14.530075 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 64873 # number of writebacks -system.cpu.dcache.writebacks::total 64873 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24343 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24343 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 13890 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 13890 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 64874 # number of writebacks +system.cpu.dcache.writebacks::total 64874 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24383 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24383 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 13871 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 13871 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 262 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 262 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38233 # 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Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1435.734951 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84258685250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.617911 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 421.096641 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 160.740422 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.042851 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084052 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.025702 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009811 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.162416 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 262 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3326 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 86 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 157 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 749 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2295 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015991 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.203003 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3103985 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3103985 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 52960 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 64249 # 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number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 15317000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 121584000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 49948250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 171532250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 121584000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 49948250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 171532250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 54952 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 64772 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 119724 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 64874 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 64874 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 8637 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 8637 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 54952 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 73409 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 128361 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 54952 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 73409 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 128361 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.036250 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.008074 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021007 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027209 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.027209 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.036250 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.010326 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.021424 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.036250 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.010326 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.021424 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61036.144578 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 66216.539197 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 62113.419483 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65178.723404 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65178.723404 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61036.144578 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65894.788918 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 62375.363636 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61036.144578 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65894.788918 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 62375.363636 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1987 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2502 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1816 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1816 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 235 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 235 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1987 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 750 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2737 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1987 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 750 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1816 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4553 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104199500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29901250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 134100750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 63393390 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 63393390 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13328500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13328500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104199500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 43229750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 147429250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104199500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 43229750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 63393390 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 210822640 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.036159 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.007951 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.020898 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027209 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027209 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036159 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010217 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.021323 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036159 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010217 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.035470 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52440.613991 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58060.679612 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53597.422062 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34908.254405 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34908.254405 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56717.021277 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56717.021277 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52440.613991 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57639.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53865.272196 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52440.613991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57639.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34908.254405 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 46304.115967 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 119724 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 119724 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 64874 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8637 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109904 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211692 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 321596 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8850112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12367040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2213 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 195448 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.011323 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105804 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 193235 98.87% 98.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 2213 1.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 195448 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 161491500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 82814471 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 110208992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3617 # Transaction distribution +system.membus.trans_dist::ReadResp 3617 # Transaction distribution +system.membus.trans_dist::ReadExReq 235 # Transaction distribution +system.membus.trans_dist::ReadExResp 235 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7704 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7704 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 246528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 246528 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3852 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3852 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3852 # Request fanout histogram +system.membus.reqLayer0.occupancy 5007645 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 36124927 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index b068c4279..7ececc2b6 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.099596 # Nu sim_ticks 99596491000 # Number of ticks simulated final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2060285 # Simulator instruction rate (inst/s) -host_op_rate 2171872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1190808654 # Simulator tick rate (ticks/s) -host_mem_usage 300012 # Number of bytes of host memory used -host_seconds 83.64 # Real time elapsed on the host +host_inst_rate 1699536 # Simulator instruction rate (inst/s) +host_op_rate 1791584 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 982302061 # Simulator tick rate (ticks/s) +host_mem_usage 304728 # Number of bytes of host memory used +host_seconds 101.39 # Real time elapsed on the host sim_insts 172317409 # Number of instructions simulated sim_ops 181650341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 454362795 # Wr system.physmem.bw_total::cpu.inst 7625170288 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1564177607 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9189347896 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 217614902 # Transaction distribution -system.membus.trans_dist::ReadResp 217637309 # Transaction distribution -system.membus.trans_dist::WriteReq 12364287 # Transaction distribution -system.membus.trans_dist::WriteResp 12364287 # Transaction distribution -system.membus.trans_dist::SoftPFReq 463 # Transaction distribution -system.membus.trans_dist::SoftPFResp 463 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution -system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution -system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720102 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 460048932 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 230024466 # Request fanout histogram -system.membus.snoop_fanout::mean 4.825391 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 40164415 17.46% 17.46% # Request fanout histogram -system.membus.snoop_fanout::5 189860051 82.54% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 230024466 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650742 # Class of executed instruction +system.membus.trans_dist::ReadReq 217614902 # Transaction distribution +system.membus.trans_dist::ReadResp 217637309 # Transaction distribution +system.membus.trans_dist::WriteReq 12364287 # Transaction distribution +system.membus.trans_dist::WriteResp 12364287 # Transaction distribution +system.membus.trans_dist::SoftPFReq 463 # Transaction distribution +system.membus.trans_dist::SoftPFResp 463 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution +system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution +system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 460048932 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440204 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 230024466 # Request fanout histogram +system.membus.snoop_fanout::mean 4.825391 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 40164415 17.46% 17.46% # Request fanout histogram +system.membus.snoop_fanout::5 189860051 82.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 230024466 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 394a8f6cf..62a10ca2c 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.230173 # Nu sim_ticks 230173357000 # Number of ticks simulated final_tick 230173357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1215411 # Simulator instruction rate (inst/s) -host_op_rate 1281349 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1627973861 # Simulator tick rate (ticks/s) -host_mem_usage 309492 # Number of bytes of host memory used -host_seconds 141.39 # Real time elapsed on the host +host_inst_rate 1229194 # Simulator instruction rate (inst/s) +host_op_rate 1295881 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1646435898 # Simulator tick rate (ticks/s) +host_mem_usage 312932 # Number of bytes of host memory used +host_seconds 139.80 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 181165370 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,30 +29,15 @@ system.physmem.bw_inst_read::total 480751 # In system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 2361 # Transaction distribution -system.membus.trans_dist::ReadResp 2361 # Transaction distribution -system.membus.trans_dist::ReadExReq 1092 # Transaction distribution -system.membus.trans_dist::ReadExResp 1092 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3453 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3453 # Request fanout histogram -system.membus.reqLayer0.occupancy 3596000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 31220000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -74,6 +59,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -95,6 +88,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -116,6 +117,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -198,6 +207,139 @@ system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650742 # Class of executed instruction +system.cpu.dcache.tags.replacements 40 # number of replacements +system.cpu.dcache.tags.tagsinuse 1363.619284 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619284 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits +system.cpu.dcache.overall_hits::total 40117812 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses +system.cpu.dcache.overall_misses::total 1789 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34093000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34093000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57994500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 57994500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 92087500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92140500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 92140500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1506 # number of replacements system.cpu.icache.tags.tagsinuse 1147.992604 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. @@ -430,139 +572,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.619284 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619284 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits -system.cpu.dcache.overall_hits::total 40117812 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses -system.cpu.dcache.overall_misses::total 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 16 # number of writebacks -system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34093000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34093000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57994500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 57994500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 92087500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92140500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 92140500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution @@ -596,5 +605,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 4576500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 2361 # Transaction distribution +system.membus.trans_dist::ReadResp 2361 # Transaction distribution +system.membus.trans_dist::ReadExReq 1092 # Transaction distribution +system.membus.trans_dist::ReadExResp 1092 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3453 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3453 # Request fanout histogram +system.membus.reqLayer0.occupancy 3596000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 31220000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index c2d74a54c..85460c89a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.148694 # Number of seconds simulated -sim_ticks 148694012000 # Number of ticks simulated -final_tick 148694012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.148652 # Number of seconds simulated +sim_ticks 148652306000 # Number of ticks simulated +final_tick 148652306000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81223 # Simulator instruction rate (inst/s) -host_op_rate 136137 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91445548 # Simulator tick rate (ticks/s) -host_mem_usage 288088 # Number of bytes of host memory used -host_seconds 1626.04 # Real time elapsed on the host +host_inst_rate 83185 # Simulator instruction rate (inst/s) +host_op_rate 139426 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 93628996 # Simulator tick rate (ticks/s) +host_mem_usage 346568 # Number of bytes of host memory used +host_seconds 1587.67 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 223936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125888 # Number of bytes read from this memory -system.physmem.bytes_read::total 349824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 223936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 223936 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3499 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1967 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5466 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1506019 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 846625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2352643 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1506019 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1506019 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1506019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 846625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2352643 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5466 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 224768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125696 # Number of bytes read from this memory +system.physmem.bytes_read::total 350464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 224768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 224768 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3512 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1964 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5476 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1512038 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 845570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2357609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1512038 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1512038 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1512038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 845570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2357609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5476 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5466 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5476 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 349824 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 350464 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 349824 # Total read bytes from the system interface side +system.physmem.bytesReadSys 350464 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 296 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 294 # Per bank write bursts -system.physmem.perBankRdBursts::1 361 # Per bank write bursts -system.physmem.perBankRdBursts::2 463 # Per bank write bursts -system.physmem.perBankRdBursts::3 372 # Per bank write bursts -system.physmem.perBankRdBursts::4 337 # Per bank write bursts -system.physmem.perBankRdBursts::5 332 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 324 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 295 # Per bank write bursts +system.physmem.perBankRdBursts::1 363 # Per bank write bursts +system.physmem.perBankRdBursts::2 461 # Per bank write bursts +system.physmem.perBankRdBursts::3 370 # Per bank write bursts +system.physmem.perBankRdBursts::4 335 # Per bank write bursts +system.physmem.perBankRdBursts::5 334 # Per bank write bursts system.physmem.perBankRdBursts::6 400 # Per bank write bursts -system.physmem.perBankRdBursts::7 384 # Per bank write bursts -system.physmem.perBankRdBursts::8 341 # Per bank write bursts -system.physmem.perBankRdBursts::9 282 # Per bank write bursts -system.physmem.perBankRdBursts::10 235 # Per bank write bursts -system.physmem.perBankRdBursts::11 262 # Per bank write bursts -system.physmem.perBankRdBursts::12 222 # Per bank write bursts -system.physmem.perBankRdBursts::13 508 # Per bank write bursts +system.physmem.perBankRdBursts::7 383 # Per bank write bursts +system.physmem.perBankRdBursts::8 340 # Per bank write bursts +system.physmem.perBankRdBursts::9 286 # Per bank write bursts +system.physmem.perBankRdBursts::10 236 # Per bank write bursts +system.physmem.perBankRdBursts::11 261 # Per bank write bursts +system.physmem.perBankRdBursts::12 219 # Per bank write bursts +system.physmem.perBankRdBursts::13 509 # Per bank write bursts system.physmem.perBankRdBursts::14 392 # Per bank write bursts -system.physmem.perBankRdBursts::15 281 # Per bank write bursts +system.physmem.perBankRdBursts::15 292 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 148693969000 # Total gap between requests +system.physmem.totGap 148652208500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5466 # Read request sizes (log2) +system.physmem.readPktSize::6 5476 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 896 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 909 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 176 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,336 +186,314 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1125 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 309.532444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.678629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.994757 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 454 40.36% 40.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 235 20.89% 61.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 101 8.98% 70.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 52 4.62% 74.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 60 5.33% 80.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 59 5.24% 85.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 19 1.69% 87.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 20 1.78% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 125 11.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1125 # Bytes accessed per row activation -system.physmem.totQLat 38946250 # Total ticks spent queuing -system.physmem.totMemAccLat 141433750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 27330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7125.18 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 304.265039 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.960981 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.625541 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 464 40.45% 40.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 245 21.36% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 104 9.07% 70.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 4.97% 75.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 54 4.71% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 57 4.97% 85.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 24 2.09% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 15 1.31% 88.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 127 11.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1147 # Bytes accessed per row activation +system.physmem.totQLat 37377750 # Total ticks spent queuing +system.physmem.totMemAccLat 140052750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 27380000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6825.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25875.18 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.35 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25575.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.35 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.36 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4331 # Number of row buffer hits during reads +system.physmem.readRowHits 4321 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.24 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.91 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 27203433.77 # Average gap between requests -system.physmem.pageHitRate 79.24 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 142073657250 # Time in different power states -system.physmem.memoryStateTime::REF 4964960000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1647900000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 4982040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3500280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2718375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1909875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 22776000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 19507800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 9711461760 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 9711461760 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 4022315865 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 3825718020 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 85683555000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 85856009250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 99447809040 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 99418106985 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.842205 # Core power per rank (mW) -system.physmem.averagePower::1 668.642442 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 3933 # Transaction distribution -system.membus.trans_dist::ReadResp 3932 # Transaction distribution -system.membus.trans_dist::UpgradeReq 296 # Transaction distribution -system.membus.trans_dist::UpgradeResp 296 # Transaction distribution -system.membus.trans_dist::ReadExReq 1533 # Transaction distribution -system.membus.trans_dist::ReadExResp 1533 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11523 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11523 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11523 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 349760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 349760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 349760 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5762 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5762 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5762 # Request fanout histogram -system.membus.reqLayer0.occupancy 7167000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 51861454 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 22382097 # Number of BP lookups -system.cpu.branchPred.condPredicted 22382097 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1553409 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 14143770 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13239374 # Number of BTB hits +system.physmem.avgGap 27146130.11 # Average gap between requests +system.physmem.pageHitRate 78.91 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5072760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2767875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 22791600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 9708918960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4015280925 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 85666359000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 99421191120 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.838371 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 142511183750 # Time in different power states +system.physmem_0.memoryStateTime::REF 4963660000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1172773250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3575880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1951125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19585800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 9708918960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3861811845 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 85800972750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 99396816360 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.674456 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 142739163750 # Time in different power states +system.physmem_1.memoryStateTime::REF 4963660000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 947728750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 22375930 # Number of BP lookups +system.cpu.branchPred.condPredicted 22375930 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1550820 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 14142904 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13245564 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.605694 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1523861 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 22060 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.655193 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1524021 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21798 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 297388032 # number of cpu cycles simulated +system.cpu.numCycles 297304620 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27880008 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 249058784 # Number of instructions fetch has processed -system.cpu.fetch.Branches 22382097 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 14763235 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 267434691 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3695049 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 15 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4561 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 42381 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 27866919 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 248846814 # Number of instructions fetch has processed +system.cpu.fetch.Branches 22375930 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 14769585 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 267364531 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3698749 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 56 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 42690 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 26649696 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 257275 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 297209306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.380725 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.789359 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 111 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 26638460 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 257102 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 297128244 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.381645 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.790124 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 229177022 77.11% 77.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5084587 1.71% 78.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4138437 1.39% 80.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4791887 1.61% 81.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4876855 1.64% 83.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5109175 1.72% 85.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5334492 1.79% 86.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4008000 1.35% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34688851 11.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 229068376 77.09% 77.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5099613 1.72% 78.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4127262 1.39% 80.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4784384 1.61% 81.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4893969 1.65% 83.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5110538 1.72% 85.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5334476 1.80% 86.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3994023 1.34% 88.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34715603 11.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 297209306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075262 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.837488 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16317003 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 231094890 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 26094955 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21854934 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1847524 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 359064274 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1847524 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24114798 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 162761005 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 33475 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 38241804 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 70210700 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 350324590 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 42142 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 61992199 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7946895 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 152925 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 405428411 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 972465740 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 641794462 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4665474 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 297128244 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075263 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.837010 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16329336 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 230975824 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 26113582 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21860128 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1849374 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 359242894 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1849374 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24118008 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 162656356 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 38273 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 38263619 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70202614 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 350538626 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 41453 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 61947521 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7945702 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 153558 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 405817730 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 972424276 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 641996744 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4657501 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 145998961 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2154 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2076 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 128653734 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89733483 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 32018253 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 63985001 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21567740 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 341091248 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4877 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 266696686 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 73290 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 119329162 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 250439001 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3632 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 297209306 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.897336 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.363195 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 146388280 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2397 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2322 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 128546417 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89512895 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 32023027 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 63891013 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21581901 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 341300793 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5145 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 266928835 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 76764 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 119543073 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 250225997 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3900 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 297128244 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.898362 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.364631 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 171484109 57.70% 57.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 54269493 18.26% 75.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33638460 11.32% 87.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19147986 6.44% 93.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10817239 3.64% 97.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4351297 1.46% 98.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2217356 0.75% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 890190 0.30% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 393176 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 171384973 57.68% 57.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54250707 18.26% 75.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33605057 11.31% 87.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19187938 6.46% 93.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10808168 3.64% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4369052 1.47% 98.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2227260 0.75% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 898004 0.30% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 397085 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 297209306 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 297128244 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 237582 7.35% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2582537 79.93% 87.28% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 410926 12.72% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 240256 7.42% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2591676 80.04% 87.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 406020 12.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211351 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167148119 62.67% 63.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 789126 0.30% 63.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7035938 2.64% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1214032 0.46% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 66518900 24.94% 91.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22779220 8.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211341 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167360520 62.70% 63.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 793230 0.30% 63.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7036198 2.64% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1213739 0.45% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 66512723 24.92% 91.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22801084 8.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 266696686 # Type of FU issued -system.cpu.iq.rate 0.896797 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3231045 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012115 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 828907957 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 456425026 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 260744620 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4999056 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4321531 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2398079 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266200144 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2516236 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18853700 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 266928835 # Type of FU issued +system.cpu.iq.rate 0.897829 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3237952 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012130 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 829304993 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 456859927 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 261005005 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4995637 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4315017 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2397122 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266441955 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2513491 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18899538 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 33083896 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14048 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 327034 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11502536 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 32863308 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14004 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 331776 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11507310 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 52807 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 52520 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1847524 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 126225383 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5553775 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 341096125 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 111900 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89733483 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 32018253 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2073 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2221761 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 397558 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 327034 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 687554 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 924641 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1612195 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 264577830 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 65651803 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2118856 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1849374 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 126083228 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5521965 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 341305938 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 113234 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89512895 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 32023027 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2291 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2224383 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 364956 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 331776 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 682604 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 926974 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1609578 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 264820941 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 65644877 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2107894 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 88227876 # number of memory reference insts executed -system.cpu.iew.exec_branches 14574542 # Number of branches executed -system.cpu.iew.exec_stores 22576073 # Number of stores executed -system.cpu.iew.exec_rate 0.889672 # Inst execution rate -system.cpu.iew.wb_sent 263857804 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 263142699 # cumulative count of insts written-back -system.cpu.iew.wb_producers 208771445 # num instructions producing a value -system.cpu.iew.wb_consumers 376756650 # num instructions consuming a value +system.cpu.iew.exec_refs 88243318 # number of memory reference insts executed +system.cpu.iew.exec_branches 14594562 # Number of branches executed +system.cpu.iew.exec_stores 22598441 # Number of stores executed +system.cpu.iew.exec_rate 0.890739 # Inst execution rate +system.cpu.iew.wb_sent 264116022 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 263402127 # cumulative count of insts written-back +system.cpu.iew.wb_producers 208929627 # num instructions producing a value +system.cpu.iew.wb_consumers 376950815 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.884846 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.554128 # average fanout of values written-back +system.cpu.iew.wb_rate 0.885967 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.554262 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119784082 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119991036 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1557714 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 280934178 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.787955 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.593006 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1555160 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 280815934 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.788286 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.594389 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 181002455 64.43% 64.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57799506 20.57% 85.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14236358 5.07% 90.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11930779 4.25% 94.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4218902 1.50% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2886432 1.03% 96.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 918195 0.33% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1050521 0.37% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6891030 2.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 180962849 64.44% 64.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57749972 20.57% 85.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14199777 5.06% 90.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11927311 4.25% 94.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4203723 1.50% 95.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2893126 1.03% 96.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 916943 0.33% 97.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1048119 0.37% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6914114 2.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 280934178 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 280815934 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -561,252 +539,336 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6891030 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6914114 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 615190614 # The number of ROB reads -system.cpu.rob.rob_writes 698614569 # The number of ROB writes -system.cpu.timesIdled 3122 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 178726 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 615256240 # The number of ROB reads +system.cpu.rob.rob_writes 699066092 # The number of ROB writes +system.cpu.timesIdled 3079 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 176376 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.251725 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.251725 # CPI: Total CPI of All Threads -system.cpu.ipc 0.444104 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.444104 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 456362005 # number of integer regfile reads -system.cpu.int_regfile_writes 239113538 # number of integer regfile writes -system.cpu.fp_regfile_reads 3275482 # number of floating regfile reads -system.cpu.fp_regfile_writes 2058196 # number of floating regfile writes -system.cpu.cc_regfile_reads 102983282 # number of cc regfile reads -system.cpu.cc_regfile_writes 60177632 # number of cc regfile writes -system.cpu.misc_regfile_reads 136798826 # number of misc regfile reads +system.cpu.cpi 2.251094 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.251094 # CPI: Total CPI of All Threads +system.cpu.ipc 0.444229 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.444229 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 456513966 # number of integer regfile reads +system.cpu.int_regfile_writes 239334814 # number of integer regfile writes +system.cpu.fp_regfile_reads 3274089 # number of floating regfile reads +system.cpu.fp_regfile_writes 2057271 # number of floating regfile writes +system.cpu.cc_regfile_reads 102998380 # number of cc regfile reads +system.cpu.cc_regfile_writes 60202762 # number of cc regfile writes +system.cpu.misc_regfile_reads 136901121 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 8736 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 8734 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1538 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1538 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16221 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4632 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 20853 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 509376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 638784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 301 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10583 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 10583 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10583 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5301999 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 12991249 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3546296 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 5983 # number of replacements -system.cpu.icache.tags.tagsinuse 1649.665059 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 26639065 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 7962 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3345.775559 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 52 # number of replacements +system.cpu.dcache.tags.tagsinuse 1443.647680 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 67095165 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2013 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33330.931446 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1443.647680 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352453 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352453 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1961 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 441 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1405 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.478760 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 134197329 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 134197329 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 46580786 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 46580786 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513865 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513865 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 67094651 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 67094651 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 67094651 # number of overall hits +system.cpu.dcache.overall_hits::total 67094651 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1141 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1141 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1866 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1866 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3007 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3007 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3007 # number of overall misses +system.cpu.dcache.overall_misses::total 3007 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64283437 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64283437 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 116004574 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 116004574 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 180288011 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 180288011 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 180288011 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 180288011 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 46581927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 46581927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 67097658 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 67097658 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 67097658 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 67097658 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000091 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000091 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56339.559159 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56339.559159 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62167.510182 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62167.510182 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59956.106086 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59956.106086 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59956.106086 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59956.106086 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 248 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 50 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.600000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 145260176 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 145260176 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000091 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000091 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70886.315789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70886.315789 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59833.338338 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59833.338338 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62076.998291 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62076.998291 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62076.998291 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62076.998291 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 5851 # number of replacements +system.cpu.icache.tags.tagsinuse 1641.461746 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 26627917 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 7830 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3400.755683 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1649.665059 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.805501 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.805501 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1641.461746 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801495 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801495 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1979 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 796 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 127 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 813 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 767 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.966309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 53307648 # Number of tag accesses -system.cpu.icache.tags.data_accesses 53307648 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 26639065 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 26639065 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 26639065 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 26639065 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 26639065 # number of overall hits -system.cpu.icache.overall_hits::total 26639065 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 10629 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 10629 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 10629 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 10629 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 10629 # number of overall misses -system.cpu.icache.overall_misses::total 10629 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 394374749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 394374749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 394374749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 394374749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 394374749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 394374749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 26649694 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 26649694 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 26649694 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 26649694 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 26649694 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 26649694 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37103.655000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37103.655000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37103.655000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37103.655000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37103.655000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37103.655000 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1302 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 53285074 # Number of tag accesses +system.cpu.icache.tags.data_accesses 53285074 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 26627919 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 26627919 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 26627919 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 26627919 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 26627919 # number of overall hits +system.cpu.icache.overall_hits::total 26627919 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 10540 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 10540 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 10540 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 10540 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 10540 # number of overall misses +system.cpu.icache.overall_misses::total 10540 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 391405749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 391405749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 391405749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 391405749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 391405749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 391405749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 26638459 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 26638459 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 26638459 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 26638459 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 26638459 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 26638459 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000396 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000396 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000396 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000396 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000396 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000396 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37135.270304 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37135.270304 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37135.270304 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37135.270304 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37135.270304 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37135.270304 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1286 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 49.461538 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2367 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2367 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2367 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2367 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2367 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2367 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8262 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 8262 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 8262 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 8262 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 8262 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 8262 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 293853251 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 293853251 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 293853251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 293853251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 293853251 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 293853251 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000310 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000310 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000310 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000310 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000310 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000310 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35566.842290 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35566.842290 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35566.842290 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35566.842290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35566.842290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35566.842290 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2383 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2383 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2383 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2383 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2383 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2383 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8157 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 8157 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 8157 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 8157 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 8157 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 8157 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292444251 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 292444251 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292444251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 292444251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292444251 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 292444251 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000306 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000306 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000306 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000306 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000306 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000306 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35851.937109 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35851.937109 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35851.937109 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35851.937109 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35851.937109 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35851.937109 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2653.963036 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4507 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3933 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.145945 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2637.518864 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4367 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3944 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.107252 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1.072767 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2333.691994 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 319.198275 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000033 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071219 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.009741 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.080993 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3933 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 904 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 148 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2687 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.120026 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 87730 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 87730 # 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miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989967 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989967 # miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 7830 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2013 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9843 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 7830 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2013 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9843 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.448659 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.907368 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.474895 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54695.205479 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56229.214286 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56617.437722 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56368.895189 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56229.214286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56617.437722 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56368.895189 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.975658 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.556436 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.975658 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.556436 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56008.539710 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63556.844548 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56833.417850 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.540123 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.540123 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54198.303979 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54198.303979 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56008.539710 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56252.036660 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56095.855395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56008.539710 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56252.036660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56095.855395 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 52 # number of replacements -system.cpu.dcache.tags.tagsinuse 1451.665096 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 67147234 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2012 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33373.376740 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1451.665096 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.354410 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.354410 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1960 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1416 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.478516 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 134301424 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 134301424 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 46632911 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 46632911 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513893 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513893 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 67146804 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 67146804 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 67146804 # number of overall hits -system.cpu.dcache.overall_hits::total 67146804 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1064 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1064 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1838 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1838 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2902 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2902 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2902 # number of overall misses -system.cpu.dcache.overall_misses::total 2902 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63689380 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63689380 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 116173296 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 116173296 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 179862676 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 179862676 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 179862676 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 179862676 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 46633975 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 46633975 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 67149706 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 67149706 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 67149706 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 67149706 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000090 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59858.439850 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59858.439850 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63206.363439 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63206.363439 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61978.868367 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61978.868367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61978.868367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61978.868367 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 303 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 50 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 60.600000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 10 # number of writebacks -system.cpu.dcache.writebacks::total 10 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 590 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 590 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 591 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 591 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 591 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 591 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 474 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 474 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1837 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1837 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2311 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2311 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2311 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2311 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33789250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33789250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111812454 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 111812454 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145601704 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 145601704 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 145601704 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 145601704 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000090 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000090 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71285.337553 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71285.337553 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60866.877518 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60866.877518 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63003.766335 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63003.766335 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63003.766335 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63003.766335 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 8632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 8631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 327 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 327 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1538 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1538 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15986 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4690 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 20676 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 501056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 630528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 327 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10507 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 10507 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 10507 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5263999 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 12826749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3560824 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3943 # Transaction distribution +system.membus.trans_dist::ReadResp 3943 # Transaction distribution +system.membus.trans_dist::UpgradeReq 324 # Transaction distribution +system.membus.trans_dist::UpgradeResp 324 # Transaction distribution +system.membus.trans_dist::ReadExReq 1533 # Transaction distribution +system.membus.trans_dist::ReadExResp 1533 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11600 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 350464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 350464 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5800 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5800 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5800 # Request fanout histogram +system.membus.reqLayer0.occupancy 7074000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 51890176 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |