diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
| commit | 0d46708dc20c438d29bd724fb7d4b54d4d2f318a (patch) | |
| tree | 337e1a7404c57817cd08106a0369542ea5c4ac30 /tests/long/se | |
| parent | 9b05e96b9efdb9cdcc4e40ef9c96b1228df7a175 (diff) | |
| download | gem5-0d46708dc20c438d29bd724fb7d4b54d4d2f318a.tar.xz | |
bp: fix up stats for changes to branch predictor
Diffstat (limited to 'tests/long/se')
48 files changed, 11254 insertions, 11206 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index 26d645fed..f0d94be3d 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:10:21 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:26 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 274500333500 because target called exit() +Exiting @ tick 274300226500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 1a8f04561..206fd9b5c 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.274500 # Number of seconds simulated -sim_ticks 274500333500 # Number of ticks simulated -final_tick 274500333500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.274300 # Number of seconds simulated +sim_ticks 274300226500 # Number of ticks simulated +final_tick 274300226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160535 # Simulator instruction rate (inst/s) -host_op_rate 160535 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73218214 # Simulator tick rate (ticks/s) +host_inst_rate 157937 # Simulator instruction rate (inst/s) +host_op_rate 157937 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71980747 # Simulator tick rate (ticks/s) host_mem_usage 209892 # Number of bytes of host memory used -host_seconds 3749.07 # Real time elapsed on the host +host_seconds 3810.74 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5894016 # Number of bytes read from this memory +system.physmem.bytes_read 5894080 # Number of bytes read from this memory system.physmem.bytes_inst_read 54720 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3798080 # Number of bytes written to this memory -system.physmem.num_reads 92094 # Number of read requests responded to by this memory -system.physmem.num_writes 59345 # Number of write requests responded to by this memory +system.physmem.bytes_written 3798144 # Number of bytes written to this memory +system.physmem.num_reads 92095 # Number of read requests responded to by this memory +system.physmem.num_writes 59346 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 21471799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 199344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 13836340 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 35308139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 21487696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 199489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 13846667 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 35334364 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517568 # DTB read hits +system.cpu.dtb.read_hits 114517577 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520199 # DTB read accesses -system.cpu.dtb.write_hits 39666597 # DTB write hits +system.cpu.dtb.read_accesses 114520208 # DTB read accesses +system.cpu.dtb.write_hits 39666608 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39668899 # DTB write accesses -system.cpu.dtb.data_hits 154184165 # DTB hits +system.cpu.dtb.write_accesses 39668910 # DTB write accesses +system.cpu.dtb.data_hits 154184185 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154189098 # DTB accesses -system.cpu.itb.fetch_hits 27986226 # ITB hits +system.cpu.dtb.data_accesses 154189118 # DTB accesses +system.cpu.itb.fetch_hits 25020502 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 27986248 # ITB accesses +system.cpu.itb.fetch_accesses 25020524 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,16 +54,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 549000668 # number of cpu cycles simulated +system.cpu.numCycles 548600454 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 538772486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 538371184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 412059 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59486579 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 489514089 # Number of cycles cpu stages are processed. -system.cpu.activity 89.164571 # Percentage of cycles cpu is active +system.cpu.timesIdled 412150 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59439534 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 489160920 # Number of cycles cpu stages are processed. +system.cpu.activity 89.165242 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -75,158 +75,158 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.912178 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.911513 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.912178 # CPI: Total CPI of All Threads -system.cpu.ipc 1.096277 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.911513 # CPI: Total CPI of All Threads +system.cpu.ipc 1.097077 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.096277 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 86959577 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 82118654 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36581334 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 45689066 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 35726566 # Number of BTB hits +system.cpu.ipc_total 1.097077 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 86318297 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 81372201 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36359139 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 52872243 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 34320184 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 78.195002 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 38245021 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 48714556 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 540577865 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 64.911534 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 36897167 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49421130 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541659172 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1004432711 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 1005514018 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255585026 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 154582342 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 35142167 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 1434180 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36576347 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 25971564 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.477328 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 411886396 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 254972528 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 155051949 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 33760596 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 2593556 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36354152 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26193756 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.122091 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 412334574 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 209828742 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 339171926 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 61.779875 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 238624991 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310375677 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 56.534663 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 207052073 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341948595 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.285643 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 437467887 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111532781 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.315600 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 201947249 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 347053419 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 63.215482 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 209725198 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338875256 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 61.770867 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 237724577 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310875877 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 56.667083 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 206774969 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341825485 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.308641 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 437071966 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111528488 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.329638 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 201598142 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 347002312 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 63.252283 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 728.259897 # Cycle average of tags in use -system.cpu.icache.total_refs 27985205 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 728.232127 # Cycle average of tags in use +system.cpu.icache.total_refs 25019479 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 32731.233918 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29262.548538 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 728.259897 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.355596 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.355596 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 27985205 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27985205 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27985205 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27985205 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27985205 # number of overall hits -system.cpu.icache.overall_hits::total 27985205 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1019 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1019 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1019 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1019 # number of overall misses -system.cpu.icache.overall_misses::total 1019 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 56646500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 56646500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 56646500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 56646500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 56646500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 56646500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27986224 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27986224 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27986224 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27986224 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27986224 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27986224 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55590.284593 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55590.284593 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55590.284593 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 728.232127 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.355582 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.355582 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25019479 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25019479 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25019479 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25019479 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25019479 # number of overall hits +system.cpu.icache.overall_hits::total 25019479 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses +system.cpu.icache.overall_misses::total 1021 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 56709500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 56709500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 56709500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 56709500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 56709500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 56709500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25020500 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25020500 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25020500 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25020500 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25020500 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25020500 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55543.095005 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 21750 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 164 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 164 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 164 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 164 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 164 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 164 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45774000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45774000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45774000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45774000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45774000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45774000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53536.842105 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53536.842105 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53536.842105 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45765000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45765000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45765000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45765000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45765000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45765000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53526.315789 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.126386 # Cycle average of tags in use -system.cpu.dcache.total_refs 152394244 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.124914 # Cycle average of tags in use +system.cpu.dcache.total_refs 152394215 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 334.641891 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 267624000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.126386 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999543 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999543 # Average percentage of cache occupancy +system.cpu.dcache.avg_refs 334.641827 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 267632000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.124914 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999542 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999542 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114120509 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114120509 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38273735 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38273735 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 152394244 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152394244 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152394244 # number of overall hits -system.cpu.dcache.overall_hits::total 152394244 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 38273706 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38273706 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 152394215 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152394215 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152394215 # number of overall hits +system.cpu.dcache.overall_hits::total 152394215 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 393533 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 393533 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1177586 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1177586 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1571119 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1571119 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1571119 # number of overall misses -system.cpu.dcache.overall_misses::total 1571119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8150453500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8150453500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25245531000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25245531000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33395984500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33395984500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33395984500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33395984500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 1177615 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1177615 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1571148 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1571148 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1571148 # number of overall misses +system.cpu.dcache.overall_misses::total 1571148 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8150462000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8150462000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25247540000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25247540000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33398002000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33398002000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33398002000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33398002000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -236,31 +236,31 @@ system.cpu.dcache.demand_accesses::total 153965363 # nu system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029849 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010204 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010204 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20710.978495 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21438.375626 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21256.177603 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21256.177603 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12016500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3424460500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2770 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 216245 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4338.086643 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15836.021642 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029850 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010205 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010205 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.000094 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21439.553674 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12006000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3424818500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2777 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 216268 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4323.370544 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15835.992842 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 408188 # number of writebacks -system.cpu.dcache.writebacks::total 408188 # number of writebacks +system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks +system.cpu.dcache.writebacks::total 408190 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192301 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 192301 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 923423 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 923423 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1115724 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1115724 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1115724 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1115724 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 923452 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 923452 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1115753 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1115753 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1115753 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1115753 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -269,75 +269,75 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3562138000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3562138000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466740000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466740000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9028878000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9028878000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028878000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9028878000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3562095500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3562095500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466864500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466864500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9028960000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9028960000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028960000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9028960000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.647849 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21508.795537 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.475917 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.475917 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.436650 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21509.285380 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73797 # number of replacements -system.cpu.l2cache.tagsinuse 17695.095192 # Cycle average of tags in use -system.cpu.l2cache.total_refs 445688 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89683 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.969593 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 73798 # number of replacements +system.cpu.l2cache.tagsinuse 17696.811171 # Cycle average of tags in use +system.cpu.l2cache.total_refs 445686 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89684 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.969515 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 16056.957351 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 28.224139 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1609.913702 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.490019 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000861 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.049131 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.540011 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 170051 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 170051 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 408188 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 408188 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 194105 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 194105 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 364156 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 364156 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 364156 # number of overall hits -system.cpu.l2cache.overall_hits::total 364156 # number of overall hits +system.cpu.l2cache.occ_blocks::writebacks 16057.614667 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 28.392088 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1610.804416 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.490040 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000866 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.049158 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.540064 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 170049 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 170049 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 408190 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 194106 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 194106 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 364155 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 364155 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 364155 # number of overall hits +system.cpu.l2cache.overall_hits::total 364155 # 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number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 91239 # number of overall misses -system.cpu.l2cache.overall_misses::total 92094 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44769000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1630148000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1674917000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3134446000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3134446000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 44769000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4764594000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 4809363000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 44769000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4764594000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 4809363000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 91240 # number of overall misses +system.cpu.l2cache.overall_misses::total 92095 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44767500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1630159000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1674926500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3134429000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3134429000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 44767500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4764588000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4809355500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 44767500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4764588000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4809355500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 201215 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 202070 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 408188 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 408188 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254180 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254180 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 201213 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 202068 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 408190 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 408190 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254182 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254182 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses @@ -345,65 +345,65 @@ system.cpu.l2cache.overall_accesses::cpu.inst 855 system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154879 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236348 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236350 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.200351 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.200354 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.200351 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52361.403509 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52308.689514 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52175.547233 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52361.403509 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52221.023904 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52361.403509 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52221.023904 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 1295000 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.200354 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52359.649123 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.042485 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52174.395765 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 1278500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10196.850394 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10066.929134 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59345 # number of writebacks -system.cpu.l2cache.writebacks::total 59345 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59346 # number of writebacks +system.cpu.l2cache.writebacks::total 59346 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31164 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 32019 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60075 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 60075 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60076 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 60076 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 91239 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 92094 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 91240 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 92095 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 91239 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 92094 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 91240 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 92095 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34345000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246681000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1281026000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2406899500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2406899500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246682000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1281027000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2406884500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2406884500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34345000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3653580500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 3687925500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3653566500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3687911500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34345000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653580500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 3687925500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653566500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 3687911500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154879 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236348 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236350 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200351 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200351 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40169.590643 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.882685 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.910529 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.914773 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40063.993941 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40044.065586 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40044.065586 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index e473c70fd..2e14d6c64 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:10:26 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:40 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 144450185500 because target called exit() +Exiting @ tick 134621123500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 6a8942beb..001739477 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.144450 # Number of seconds simulated -sim_ticks 144450185500 # Number of ticks simulated -final_tick 144450185500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.134621 # Number of seconds simulated +sim_ticks 134621123500 # Number of ticks simulated +final_tick 134621123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 270959 # Simulator instruction rate (inst/s) -host_op_rate 270959 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69206896 # Simulator tick rate (ticks/s) -host_mem_usage 211048 # Number of bytes of host memory used -host_seconds 2087.22 # Real time elapsed on the host +host_inst_rate 282179 # Simulator instruction rate (inst/s) +host_op_rate 282179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67168296 # Simulator tick rate (ticks/s) +host_mem_usage 211096 # Number of bytes of host memory used +host_seconds 2004.24 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5936768 # Number of bytes read from this memory -system.physmem.bytes_inst_read 60416 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3797120 # Number of bytes written to this memory -system.physmem.num_reads 92762 # Number of read requests responded to by this memory -system.physmem.num_writes 59330 # Number of write requests responded to by this memory +system.physmem.bytes_read 5937600 # Number of bytes read from this memory +system.physmem.bytes_inst_read 64128 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3797952 # Number of bytes written to this memory +system.physmem.num_reads 92775 # Number of read requests responded to by this memory +system.physmem.num_writes 59343 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 41099068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 418248 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 26286709 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 67385777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 44106005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 476359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 28212155 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 72318160 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 125584378 # DTB read hits -system.cpu.dtb.read_misses 26780 # DTB read misses +system.cpu.dtb.read_hits 123836708 # DTB read hits +system.cpu.dtb.read_misses 23555 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 125611158 # DTB read accesses -system.cpu.dtb.write_hits 41433696 # DTB write hits -system.cpu.dtb.write_misses 32002 # DTB write misses +system.cpu.dtb.read_accesses 123860263 # DTB read accesses +system.cpu.dtb.write_hits 40831838 # DTB write hits +system.cpu.dtb.write_misses 31545 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 41465698 # DTB write accesses -system.cpu.dtb.data_hits 167018074 # DTB hits -system.cpu.dtb.data_misses 58782 # DTB misses +system.cpu.dtb.write_accesses 40863383 # DTB write accesses +system.cpu.dtb.data_hits 164668546 # DTB hits +system.cpu.dtb.data_misses 55100 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 167076856 # DTB accesses -system.cpu.itb.fetch_hits 70952399 # ITB hits -system.cpu.itb.fetch_misses 40 # ITB misses +system.cpu.dtb.data_accesses 164723646 # DTB accesses +system.cpu.itb.fetch_hits 66483943 # ITB hits +system.cpu.itb.fetch_misses 37 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 70952439 # ITB accesses +system.cpu.itb.fetch_accesses 66483980 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,247 +54,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 288900372 # number of cpu cycles simulated +system.cpu.numCycles 269242248 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 81329377 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 74804974 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4133006 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 77032590 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 69317648 # Number of BTB hits +system.cpu.BPredUnit.lookups 78494350 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 72856279 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3049613 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 42772936 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41636011 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1953991 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 213 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 73654881 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 736311086 # Number of instructions fetch has processed -system.cpu.fetch.Branches 81329377 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 71271639 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 138478958 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 16551941 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 64286783 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 957 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 70952399 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1183706 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 288831482 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.549276 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.199825 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1626078 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 617 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68428248 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 710832339 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78494350 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43262089 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 119193912 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12932117 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 71677823 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 965 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 66483943 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 942005 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269174552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.640786 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.458790 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 150352524 52.06% 52.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 11670569 4.04% 56.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15804098 5.47% 61.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 15798949 5.47% 67.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13114109 4.54% 71.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15608541 5.40% 76.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6620136 2.29% 79.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3484931 1.21% 80.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 56377625 19.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 149980640 55.72% 55.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10366067 3.85% 59.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11842490 4.40% 63.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10610817 3.94% 67.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6990702 2.60% 70.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2664486 0.99% 71.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3492691 1.30% 72.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3105815 1.15% 73.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 70120844 26.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 288831482 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.281514 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.548668 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 89767727 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 50572891 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 125759213 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10322601 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 12409050 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4445174 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 884 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 724769065 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3300 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 12409050 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 98007088 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12678191 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 619 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 122576240 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43160294 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 711155131 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 265 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 33840558 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3866582 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 542435988 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 934956599 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 934954553 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2046 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 269174552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.291538 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.640122 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 85707948 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 55913414 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 104656914 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13023782 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9872494 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3909156 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1160 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 702084562 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4999 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9872494 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 93982559 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12740757 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2287 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104137265 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 48439190 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 690176100 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 220 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36870562 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5345683 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 527299875 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 906867454 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 906864467 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2987 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 78581099 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 84659517 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 130961315 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43800509 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14632120 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10811841 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 641773186 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 620620587 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 312645 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 75146534 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 39896926 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 288831482 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.148729 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.863512 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 63444986 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 171 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 186 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 107659132 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 129005013 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42430995 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14679275 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9584938 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 626474820 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 120 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608397310 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 335936 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60222555 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33444580 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 103 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 269174552 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.260233 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.839356 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 69246295 23.97% 23.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 56834943 19.68% 43.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 56336980 19.51% 63.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34937865 12.10% 75.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31450731 10.89% 86.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 24967668 8.64% 94.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10438059 3.61% 98.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3923057 1.36% 99.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 695884 0.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54646313 20.30% 20.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54798689 20.36% 40.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53375432 19.83% 60.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36717503 13.64% 74.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 30865027 11.47% 85.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 24096775 8.95% 94.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10651297 3.96% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3344645 1.24% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 678871 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 288831482 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269174552 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3711133 78.36% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 47 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 592679 12.51% 90.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 432117 9.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2904763 73.47% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 39 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 634502 16.05% 89.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 414382 10.48% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 450541493 72.60% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7929 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 127924018 20.61% 93.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 42147099 6.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 441013335 72.49% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7329 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126118254 20.73% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41258345 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 620620587 # Type of FU issued -system.cpu.iq.rate 2.148217 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4735976 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007631 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1535117897 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 716922572 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 608986825 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3380 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1870 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1597 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 625354857 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1706 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11780563 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 608397310 # Type of FU issued +system.cpu.iq.rate 2.259665 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3953686 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006499 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1490254859 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 686699872 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 598814509 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3935 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2431 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1728 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 612349032 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1964 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12165746 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 16447273 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 150139 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4778 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4349188 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14490971 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33593 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4856 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2979674 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 5903 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 50771 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6726 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 51107 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 12409050 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1537752 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 101062 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 686807741 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2379158 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 130961315 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 43800509 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 40948 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13806 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4778 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4044271 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 603642 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4647913 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 613128186 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 125611295 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7492401 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 9872494 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1561922 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 98319 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 670401264 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1688610 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 129005013 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42430995 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 120 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 41033 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13811 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 4856 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1345444 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2209649 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3555093 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 602577350 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 123860441 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5819960 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 45034525 # number of nop insts executed -system.cpu.iew.exec_refs 167096489 # number of memory reference insts executed -system.cpu.iew.exec_branches 68658345 # Number of branches executed -system.cpu.iew.exec_stores 41485194 # Number of stores executed -system.cpu.iew.exec_rate 2.122282 # Inst execution rate -system.cpu.iew.wb_sent 610318268 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 608988422 # cumulative count of insts written-back -system.cpu.iew.wb_producers 420036286 # num instructions producing a value -system.cpu.iew.wb_consumers 531421352 # num instructions consuming a value +system.cpu.iew.exec_nop 43926324 # number of nop insts executed +system.cpu.iew.exec_refs 164740912 # number of memory reference insts executed +system.cpu.iew.exec_branches 67006670 # Number of branches executed +system.cpu.iew.exec_stores 40880471 # Number of stores executed +system.cpu.iew.exec_rate 2.238049 # Inst execution rate +system.cpu.iew.wb_sent 600066569 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 598816237 # cumulative count of insts written-back +system.cpu.iew.wb_producers 417486240 # num instructions producing a value +system.cpu.iew.wb_consumers 531487841 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.107953 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.790402 # average fanout of values written-back +system.cpu.iew.wb_rate 2.224080 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.785505 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitCommittedOps 601856963 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 84796787 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 68396273 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4132184 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 276422432 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.177309 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.603924 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3048532 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259302058 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.321065 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.702332 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 90291943 32.66% 32.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 75645741 27.37% 60.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 32420379 11.73% 71.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8741969 3.16% 74.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10320203 3.73% 78.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19633028 7.10% 85.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6964693 2.52% 88.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5325361 1.93% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 27079115 9.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 80379492 31.00% 31.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72839999 28.09% 59.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 26734500 10.31% 69.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8121130 3.13% 72.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10288458 3.97% 76.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20405541 7.87% 84.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6352213 2.45% 86.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3556041 1.37% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30624684 11.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 276422432 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 259302058 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -305,64 +305,64 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 27079115 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 30624684 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 935932678 # The number of ROB reads -system.cpu.rob.rob_writes 1385724156 # The number of ROB writes -system.cpu.timesIdled 2221 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 68890 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 898866221 # The number of ROB reads +system.cpu.rob.rob_writes 1350401622 # The number of ROB writes +system.cpu.timesIdled 2160 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 67696 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.510829 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.510829 # CPI: Total CPI of All Threads -system.cpu.ipc 1.957604 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.957604 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 863490102 # number of integer regfile reads -system.cpu.int_regfile_writes 500818441 # number of integer regfile writes -system.cpu.fp_regfile_reads 272 # number of floating regfile reads +system.cpu.cpi 0.476069 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.476069 # CPI: Total CPI of All Threads +system.cpu.ipc 2.100534 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.100534 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 848641681 # number of integer regfile reads +system.cpu.int_regfile_writes 492726607 # number of integer regfile writes +system.cpu.fp_regfile_reads 387 # number of floating regfile reads system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 36 # number of replacements -system.cpu.icache.tagsinuse 801.236568 # Cycle average of tags in use -system.cpu.icache.total_refs 70951127 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 944 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 75160.092161 # Average number of references to valid blocks. +system.cpu.icache.replacements 49 # number of replacements +system.cpu.icache.tagsinuse 844.563885 # Cycle average of tags in use +system.cpu.icache.total_refs 66482496 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1002 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 66349.796407 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 801.236568 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.391229 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.391229 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 70951127 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 70951127 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 70951127 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 70951127 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 70951127 # number of overall hits -system.cpu.icache.overall_hits::total 70951127 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1272 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1272 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1272 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1272 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1272 # number of overall misses -system.cpu.icache.overall_misses::total 1272 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 45919500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 45919500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 45919500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 45919500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 45919500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 45919500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 70952399 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 70952399 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 70952399 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 70952399 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 70952399 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 70952399 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000018 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000018 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000018 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36100.235849 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36100.235849 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36100.235849 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 844.563885 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.412385 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.412385 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 66482496 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 66482496 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 66482496 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 66482496 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 66482496 # number of overall hits +system.cpu.icache.overall_hits::total 66482496 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1447 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1447 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1447 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1447 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1447 # number of overall misses +system.cpu.icache.overall_misses::total 1447 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 50567500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 50567500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 50567500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 50567500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 50567500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 50567500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66483943 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66483943 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66483943 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66483943 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66483943 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66483943 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34946.440912 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -371,245 +371,253 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 328 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 328 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 328 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 328 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 944 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 944 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 944 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 944 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 944 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 944 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33676000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33676000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33676000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33676000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33676000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33676000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000013 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000013 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000013 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35673.728814 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35673.728814 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35673.728814 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 445 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 445 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 445 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 445 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 445 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 445 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1002 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1002 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1002 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1002 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1002 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1002 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35750000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 35750000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35750000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 35750000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35750000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 35750000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35678.642715 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 470690 # number of replacements -system.cpu.dcache.tagsinuse 4093.940031 # Cycle average of tags in use -system.cpu.dcache.total_refs 151212527 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 474786 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 318.485648 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126051000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.940031 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999497 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999497 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 113064898 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 113064898 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38147626 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38147626 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 151212524 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 151212524 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 151212524 # number of overall hits -system.cpu.dcache.overall_hits::total 151212524 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 732041 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 732041 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1303695 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1303695 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2035736 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2035736 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2035736 # number of overall misses -system.cpu.dcache.overall_misses::total 2035736 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11783533000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11783533000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19632740219 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19632740219 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31416273219 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31416273219 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31416273219 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31416273219 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 113796939 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 113796939 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 460743 # number of replacements +system.cpu.dcache.tagsinuse 4093.783086 # Cycle average of tags in use +system.cpu.dcache.total_refs 149091432 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 464839 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 320.737787 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126301000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.783086 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999459 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999459 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 110940808 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 110940808 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38150562 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38150562 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 149091370 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 149091370 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 149091370 # number of overall hits +system.cpu.dcache.overall_hits::total 149091370 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 722352 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 722352 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1300759 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1300759 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2023111 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2023111 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2023111 # number of overall misses +system.cpu.dcache.overall_misses::total 2023111 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11755158500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11755158500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19630287922 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19630287922 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 3500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 3500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31385446422 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31385446422 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31385446422 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31385446422 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 111663160 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 111663160 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 153248260 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 153248260 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 153248260 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 153248260 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006433 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.033046 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.013284 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.013284 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16096.821080 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15059.304683 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15432.390653 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15432.390653 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 804496 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 236500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 63 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 63 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 151114481 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 151114481 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 151114481 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 151114481 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006469 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032971 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.015873 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.013388 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.013388 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16273.449094 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15091.410417 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 3500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 678496 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 191500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 100 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6935.310345 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6784.960000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17409.090909 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 423044 # number of writebacks -system.cpu.dcache.writebacks::total 423044 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 513277 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 513277 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1047673 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1047673 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1560950 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1560950 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1560950 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1560950 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 218764 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 218764 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 256022 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 256022 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 474786 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 474786 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 474786 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 474786 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1640072500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1640072500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3027658494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3027658494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4667730994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4667730994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4667730994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4667730994 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001922 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003098 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003098 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7496.994478 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11825.774715 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9831.231321 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9831.231321 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 415225 # number of writebacks +system.cpu.dcache.writebacks::total 415225 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 512035 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 512035 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1046237 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1046237 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1558272 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1558272 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1558272 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1558272 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210317 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210317 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254522 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254522 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464839 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464839 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464839 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464839 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1619332500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1619332500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3028681995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3028681995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4648014495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4648014495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4648014495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4648014495 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001883 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7699.484588 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11899.490005 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 74463 # number of replacements -system.cpu.l2cache.tagsinuse 17661.712037 # Cycle average of tags in use -system.cpu.l2cache.total_refs 478021 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 90363 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.290008 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 74480 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.233589 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.151842 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193388 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.197430 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193388 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31153.601695 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31015.680640 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31394.948498 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31153.601695 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31262.709926 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31153.601695 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31262.709926 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.197430 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31140.718563 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31015.093158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31392.467997 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31140.718563 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31261.149794 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31140.718563 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31261.149794 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index c2143f70c..4180d507c 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:39:44 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:00:24 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 177116942500 because target called exit() +Exiting @ tick 164280509500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index e204ea2b2..65753c5e3 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.177117 # Number of seconds simulated -sim_ticks 177116942500 # Number of ticks simulated -final_tick 177116942500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164281 # Number of seconds simulated +sim_ticks 164280509500 # Number of ticks simulated +final_tick 164280509500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 193712 # Simulator instruction rate (inst/s) -host_op_rate 204690 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60186856 # Simulator tick rate (ticks/s) -host_mem_usage 223404 # Number of bytes of host memory used -host_seconds 2942.78 # Real time elapsed on the host -sim_insts 570051603 # Number of instructions simulated -sim_ops 602359810 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5833792 # Number of bytes read from this memory -system.physmem.bytes_inst_read 46976 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3720320 # Number of bytes written to this memory -system.physmem.num_reads 91153 # Number of read requests responded to by this memory -system.physmem.num_writes 58130 # Number of write requests responded to by this memory +host_inst_rate 203818 # Simulator instruction rate (inst/s) +host_op_rate 215370 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58737354 # Simulator tick rate (ticks/s) +host_mem_usage 223536 # Number of bytes of host memory used +host_seconds 2796.87 # Real time elapsed on the host +sim_insts 570051663 # Number of instructions simulated +sim_ops 602359870 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 5845888 # Number of bytes read from this memory +system.physmem.bytes_inst_read 49408 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3721728 # Number of bytes written to this memory +system.physmem.num_reads 91342 # Number of read requests responded to by this memory +system.physmem.num_writes 58152 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 32937515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 265226 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 21004879 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 53942395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 35584793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 300754 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 22654714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 58239508 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,315 +64,315 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 354233886 # number of cpu cycles simulated +system.cpu.numCycles 328561020 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 91144697 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 84232652 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4003225 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 86347481 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 80064419 # Number of BTB hits +system.cpu.BPredUnit.lookups 85502166 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80303538 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2364558 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47128818 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46810492 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1704141 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1603 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 76798037 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 703840817 # Number of instructions fetch has processed -system.cpu.fetch.Branches 91144697 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 81768560 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 159197395 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 18458844 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 103018501 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 596 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 74422546 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1338162 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 353393528 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.127927 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.980484 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1441322 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2014 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68931697 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669727391 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85502166 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48251814 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130042659 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13473975 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 117702916 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 20 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67497554 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 807456 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 327710434 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.177756 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.200257 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 194196282 54.95% 54.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25625707 7.25% 62.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 19294200 5.46% 67.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 24432014 6.91% 74.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11774546 3.33% 77.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13391437 3.79% 81.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4604134 1.30% 83.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7796226 2.21% 85.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52278982 14.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 197667987 60.32% 60.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20955558 6.39% 66.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4944545 1.51% 68.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14317291 4.37% 72.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8979833 2.74% 75.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9404994 2.87% 78.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4387469 1.34% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5814392 1.77% 81.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61238365 18.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 353393528 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.257301 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.986938 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 98941962 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 83442113 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 137180071 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19452898 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14376484 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6300700 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 2518 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 740147617 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 7037 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14376484 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 111904204 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9631562 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 118839 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 143566748 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73795691 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 727217623 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 278 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59684680 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10267337 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 352 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 752950298 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3380504235 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3380504107 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 327710434 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.260232 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.038365 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 93127005 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 94874868 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108614475 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20063382 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11030704 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4784748 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1773 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 706010986 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5362 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11030704 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107410901 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13982712 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 118932 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114322879 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 80844306 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 697216799 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 201 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59255173 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 19368550 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 660 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723821711 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3241352610 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3241352482 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627417402 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 125532896 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 13135 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 13128 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 131736703 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 179759563 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 82851365 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 19142240 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 24648771 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 702464419 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 9443 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 663065354 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 737309 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 99563138 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 237077273 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3096 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 353393528 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.876280 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.733355 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627417498 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 96404213 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11542 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11540 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 169974240 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172906537 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80619433 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21532364 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 27969964 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 681972253 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 9148 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646841509 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1424100 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79435960 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 197814866 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2789 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 327710434 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.973820 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.737996 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 85420653 24.17% 24.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 90592891 25.64% 49.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 76061550 21.52% 71.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 42517322 12.03% 83.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 25489615 7.21% 90.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 18140901 5.13% 95.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7279964 2.06% 97.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6670408 1.89% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1220224 0.35% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68514298 20.91% 20.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 84850419 25.89% 46.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75242172 22.96% 69.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40564366 12.38% 82.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28638763 8.74% 90.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15215694 4.64% 95.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5886369 1.80% 97.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6524912 1.99% 99.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2273441 0.69% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 353393528 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 327710434 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 202199 4.87% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2984693 71.84% 76.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 967527 23.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 205233 5.10% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2909479 72.37% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 905756 22.53% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 412589272 62.22% 62.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6572 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 172499638 26.02% 88.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 77969869 11.76% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403929410 62.45% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6579 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166116267 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76789250 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 663065354 # Type of FU issued -system.cpu.iq.rate 1.871829 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4154419 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006265 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1684415928 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 802048612 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 650214601 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646841509 # Type of FU issued +system.cpu.iq.rate 1.968710 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4020468 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006216 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1626837984 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761428768 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638548229 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 667219753 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650861957 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 29667951 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30419634 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 30806967 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 225012 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11842 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12630350 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23953929 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 128648 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11649 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10398406 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 13680 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12577 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12846 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12456 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14376484 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 831826 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 58719 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 702543187 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1852399 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 179759563 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 82851365 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 8113 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13094 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5271 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11842 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4161334 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 494337 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4655671 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 656082264 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 169130146 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6983090 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 11030704 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 854813 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 57677 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 682047620 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 663984 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172906537 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80619433 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7812 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 12999 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4667 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11649 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1314819 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1584401 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2899220 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642689835 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163986431 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4151674 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 69325 # number of nop insts executed -system.cpu.iew.exec_refs 245820033 # number of memory reference insts executed -system.cpu.iew.exec_branches 76462484 # Number of branches executed -system.cpu.iew.exec_stores 76689887 # Number of stores executed -system.cpu.iew.exec_rate 1.852116 # Inst execution rate -system.cpu.iew.wb_sent 652222843 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 650214617 # cumulative count of insts written-back -system.cpu.iew.wb_producers 423345319 # num instructions producing a value -system.cpu.iew.wb_consumers 657402766 # num instructions consuming a value +system.cpu.iew.exec_nop 66219 # number of nop insts executed +system.cpu.iew.exec_refs 239991845 # number of memory reference insts executed +system.cpu.iew.exec_branches 74670108 # Number of branches executed +system.cpu.iew.exec_stores 76005414 # Number of stores executed +system.cpu.iew.exec_rate 1.956075 # Inst execution rate +system.cpu.iew.wb_sent 640041427 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638548245 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420154647 # num instructions producing a value +system.cpu.iew.wb_consumers 654937446 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.835552 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.643966 # average fanout of values written-back +system.cpu.iew.wb_rate 1.943469 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.641519 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 570051654 # The number of committed instructions -system.cpu.commit.commitCommittedOps 602359861 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 100193357 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 6347 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4062580 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 339017045 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.776783 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.152670 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 570051714 # The number of committed instructions +system.cpu.commit.commitCommittedOps 602359921 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 79697124 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 6359 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2424958 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 316679731 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.902111 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.239397 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 108187576 31.91% 31.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 106522126 31.42% 63.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 49316522 14.55% 77.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9859363 2.91% 80.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 23336266 6.88% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14305882 4.22% 91.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7916477 2.34% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1329398 0.39% 94.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 18243435 5.38% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 92723381 29.28% 29.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 103992421 32.84% 62.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43071500 13.60% 75.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8912974 2.81% 78.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25679598 8.11% 86.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13104188 4.14% 90.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7581196 2.39% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1156714 0.37% 93.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20457759 6.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 339017045 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570051654 # Number of instructions committed -system.cpu.commit.committedOps 602359861 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 316679731 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570051714 # Number of instructions committed +system.cpu.commit.committedOps 602359921 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219173611 # Number of memory references committed -system.cpu.commit.loads 148952596 # Number of loads committed +system.cpu.commit.refs 219173635 # Number of memory references committed +system.cpu.commit.loads 148952608 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828603 # Number of branches committed +system.cpu.commit.branches 70828615 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533522647 # Number of committed integer instructions. +system.cpu.commit.int_insts 533522695 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 18243435 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20457759 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1023326216 # The number of ROB reads -system.cpu.rob.rob_writes 1419524916 # The number of ROB writes -system.cpu.timesIdled 37353 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 840358 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570051603 # Number of Instructions Simulated -system.cpu.committedOps 602359810 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570051603 # Number of Instructions Simulated -system.cpu.cpi 0.621407 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.621407 # CPI: Total CPI of All Threads -system.cpu.ipc 1.609252 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.609252 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3275977261 # number of integer regfile reads -system.cpu.int_regfile_writes 676006750 # number of integer regfile writes +system.cpu.rob.rob_reads 978278405 # The number of ROB reads +system.cpu.rob.rob_writes 1375177371 # The number of ROB writes +system.cpu.timesIdled 40898 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 850586 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570051663 # Number of Instructions Simulated +system.cpu.committedOps 602359870 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570051663 # Number of Instructions Simulated +system.cpu.cpi 0.576371 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.576371 # CPI: Total CPI of All Threads +system.cpu.ipc 1.734995 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.734995 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3210435772 # number of integer regfile reads +system.cpu.int_regfile_writes 664215714 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 943708295 # number of misc regfile reads -system.cpu.misc_regfile_writes 2660 # number of misc regfile writes -system.cpu.icache.replacements 41 # number of replacements -system.cpu.icache.tagsinuse 657.275674 # Cycle average of tags in use -system.cpu.icache.total_refs 74421550 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 765 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 97283.071895 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 905058829 # number of misc regfile reads +system.cpu.misc_regfile_writes 2684 # number of misc regfile writes +system.cpu.icache.replacements 57 # number of replacements +system.cpu.icache.tagsinuse 691.796995 # Cycle average of tags in use +system.cpu.icache.total_refs 67496461 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 810 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 83328.964198 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 657.275674 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.320935 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.320935 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 74421550 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 74421550 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 74421550 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 74421550 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 74421550 # number of overall hits -system.cpu.icache.overall_hits::total 74421550 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 996 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 996 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 996 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 996 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 996 # number of overall misses -system.cpu.icache.overall_misses::total 996 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34937500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34937500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34937500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34937500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34937500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34937500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 74422546 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 74422546 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 74422546 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 74422546 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 74422546 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 74422546 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000013 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000013 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000013 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35077.811245 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35077.811245 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35077.811245 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 691.796995 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.337792 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.337792 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67496461 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67496461 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67496461 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67496461 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67496461 # number of overall hits +system.cpu.icache.overall_hits::total 67496461 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1093 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1093 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1093 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1093 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1093 # number of overall misses +system.cpu.icache.overall_misses::total 1093 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37450500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37450500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37450500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37450500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37450500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37450500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67497554 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67497554 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67497554 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67497554 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67497554 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67497554 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34263.952425 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34263.952425 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34263.952425 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,269 +381,270 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 231 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 231 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 231 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 231 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 231 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 231 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 765 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 765 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 765 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 765 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 765 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 765 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26235000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26235000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26235000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26235000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26235000 # 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number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 282 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 282 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 811 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 811 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 811 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 811 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 811 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 811 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27589000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27589000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27589000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27589000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27589000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27589000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34018.495684 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34018.495684 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34018.495684 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 441200 # number of replacements -system.cpu.dcache.tagsinuse 4094.750887 # Cycle average of tags in use -system.cpu.dcache.total_refs 205785268 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 445296 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 462.131409 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 87972000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.750887 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999695 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 137930344 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 137930344 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 67852261 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 67852261 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1334 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1334 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1329 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1329 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 205782605 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 205782605 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 205782605 # number of overall hits -system.cpu.dcache.overall_hits::total 205782605 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 248964 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 248964 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1565270 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1565270 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 9 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 9 # 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number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 249332 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 249332 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1543912 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543912 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 16 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 16 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1793244 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1793244 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1793244 # number of overall misses +system.cpu.dcache.overall_misses::total 1793244 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3286822500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3286822500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27023570462 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27023570462 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 163000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 163000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30310392962 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30310392962 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30310392962 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30310392962 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 132322362 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 132322362 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # 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miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008739 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008739 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13185.930496 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17266.245775 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22333.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16706.311603 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16706.311603 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1473 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1473 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1341 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1341 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 201739893 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201739893 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201739893 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201739893 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001884 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022241 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.010862 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008889 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008889 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13182.513677 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17503.310073 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10187.500000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16902.548098 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16902.548098 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9610962 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2243 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4284.869371 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 395250 # number of writebacks -system.cpu.dcache.writebacks::total 395250 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51046 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51046 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1317892 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1317892 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 9 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 9 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1368938 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1368938 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1368938 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1368938 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197918 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197918 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247378 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247378 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 445296 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 445296 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 445296 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 445296 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1625205500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1625205500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2544318027 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2544318027 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4169523527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4169523527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4169523527 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4169523527 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001432 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003564 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002145 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002145 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8211.509312 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10285.142684 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9363.487494 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9363.487494 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 394903 # number of writebacks +system.cpu.dcache.writebacks::total 394903 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51902 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 51902 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1296808 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1296808 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 26527000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3108568000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 3135095000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 810 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 197428 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 198238 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 394903 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 394903 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247105 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247105 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 810 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 444533 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 445343 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 810 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 444533 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 445343 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.953086 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163498 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235936 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.953086 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.203764 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.953086 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.203764 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34361.398964 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34325.288888 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34314.711583 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34361.398964 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34318.480901 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34361.398964 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34318.480901 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 1658000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 329 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5039.513678 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 58130 # number of writebacks -system.cpu.l2cache.writebacks::total 58130 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 58152 # number of writebacks +system.cpu.l2cache.writebacks::total 58152 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32064 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 32798 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58355 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 58355 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 90419 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 91153 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 734 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 90419 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 91153 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22853000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 996487000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1019340000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1822214500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1822214500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22853000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2818701500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2841554500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22853000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2818701500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2841554500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162010 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235890 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203054 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203054 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31134.877384 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31078.062625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31226.364493 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31134.877384 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31173.774317 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31134.877384 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31173.774317 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 772 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32269 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33041 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58301 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 58301 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 772 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 90570 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 91342 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 772 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 90570 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 91342 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24032500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1003471000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1027503500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1820086500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1820086500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24032500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2823557500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2847590000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24032500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2823557500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2847590000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.953086 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163447 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235936 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.953086 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203742 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.953086 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203742 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31130.181347 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31097.059097 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31218.786985 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31130.181347 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31175.416805 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31130.181347 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31175.416805 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index 337dcecf7..709a4d648 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:56:12 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:18:25 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 408816360000 because target called exit() +Exiting @ tick 388554296500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 3c7a99cbd..dd253efff 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,266 +1,266 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.408816 # Number of seconds simulated -sim_ticks 408816360000 # Number of ticks simulated -final_tick 408816360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.388554 # Number of seconds simulated +sim_ticks 388554296500 # Number of ticks simulated +final_tick 388554296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 218783 # Simulator instruction rate (inst/s) -host_op_rate 219472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63832966 # Simulator tick rate (ticks/s) -host_mem_usage 214000 # Number of bytes of host memory used -host_seconds 6404.47 # Real time elapsed on the host +host_inst_rate 229375 # Simulator instruction rate (inst/s) +host_op_rate 230098 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63606554 # Simulator tick rate (ticks/s) +host_mem_usage 214136 # Number of bytes of host memory used +host_seconds 6108.71 # Real time elapsed on the host sim_insts 1401188958 # Number of instructions simulated sim_ops 1405604152 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 6021376 # Number of bytes read from this memory -system.physmem.bytes_inst_read 81792 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3792448 # Number of bytes written to this memory -system.physmem.num_reads 94084 # Number of read requests responded to by this memory -system.physmem.num_writes 59257 # Number of write requests responded to by this memory +system.physmem.bytes_read 5987456 # Number of bytes read from this memory +system.physmem.bytes_inst_read 85056 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3788160 # Number of bytes written to this memory +system.physmem.num_reads 93554 # Number of read requests responded to by this memory +system.physmem.num_writes 59190 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 14728804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 200070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 9276654 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 24005458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 15409574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 218904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 9749371 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 25158945 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 817632721 # number of cpu cycles simulated +system.cpu.numCycles 777108594 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 103174324 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 92051331 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 5438120 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 100325127 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 99277633 # Number of BTB hits +system.cpu.BPredUnit.lookups 98192290 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88412741 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3784661 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 66025458 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65664289 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1230 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 220 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 175005792 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1720391035 # Number of instructions fetch has processed -system.cpu.fetch.Branches 103174324 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99278863 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 370286255 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31094297 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 246539947 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 21 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1680 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 170773896 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 991956 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 817274934 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.110623 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.012258 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1392 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 307 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 165888791 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648818264 # Number of instructions fetch has processed +system.cpu.fetch.Branches 98192290 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65665681 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330417282 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 21685615 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 262756820 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 127 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2717 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 162823525 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 752138 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 776762747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.128564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.147845 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 446988679 54.69% 54.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 82419688 10.08% 64.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 45028734 5.51% 70.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 23714407 2.90% 73.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 33177153 4.06% 77.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 33877408 4.15% 81.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 14961867 1.83% 83.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7384305 0.90% 84.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 129722693 15.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 446345465 57.46% 57.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74375625 9.58% 67.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37980087 4.89% 71.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9083330 1.17% 73.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28159964 3.63% 76.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18826619 2.42% 79.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11515688 1.48% 80.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3871202 0.50% 81.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146604767 18.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 817274934 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126187 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.104112 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 224321388 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 200349407 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 337624010 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 29538890 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 25441239 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1710162106 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 25441239 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 255728945 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 34334751 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 55175561 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 334633255 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 111961183 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1694040603 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 27905496 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 64677715 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3154928 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1413596061 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2861791975 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2827818793 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33973182 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 776762747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126356 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.121735 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 217443439 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 213446803 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 285373546 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42801949 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 17697010 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1642584513 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 17697010 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 241484414 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36505924 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52170824 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303041095 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 125863480 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1631270043 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30873302 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 72930971 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3136079 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1360952247 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2755876290 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2721902713 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 33973577 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 168825609 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3228150 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3270628 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 258968806 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 454536844 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 185491805 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 260927641 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 90896258 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1566773345 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3062819 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1493172729 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 111198 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 163655037 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 180232812 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 819148 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 817274934 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.827014 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.412188 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 116181795 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2680713 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2696169 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271856221 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 438705092 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 180250261 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 255265663 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83296081 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1517040384 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2636529 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1460865188 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 67073 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 113729678 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 136677669 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 392858 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 776762747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.880710 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.430803 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 168134039 20.57% 20.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 190992211 23.37% 43.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 210117454 25.71% 69.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 154482053 18.90% 88.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 65263213 7.99% 96.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16377311 2.00% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7979086 0.98% 99.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3751008 0.46% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 178559 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 147116911 18.94% 18.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184456460 23.75% 42.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 210881862 27.15% 69.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131212379 16.89% 86.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70768732 9.11% 95.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20345025 2.62% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7834706 1.01% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3973798 0.51% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 172874 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 817274934 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 776762747 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 154618 7.33% 7.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 176227 8.36% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1421289 67.40% 83.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 356622 16.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 106719 6.05% 6.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 167382 9.50% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1159607 65.79% 81.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 328958 18.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 886609078 59.38% 59.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2623677 0.18% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 430399729 28.82% 88.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173540245 11.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 867175983 59.36% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2649316 0.18% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419771639 28.73% 88.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171268250 11.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1493172729 # Type of FU issued -system.cpu.iq.rate 1.826214 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2108756 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001412 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3787980335 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1724526520 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1473498966 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17860011 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9206634 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8523998 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1486074999 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9206486 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 205830187 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1460865188 # Type of FU issued +system.cpu.iq.rate 1.879873 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1762666 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3682454836 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1624473314 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1444449939 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17868026 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9170759 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8547404 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1453439561 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9188293 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215395742 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 52024000 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 213849 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 253991 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 18643663 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 36192248 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 54154 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 246172 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 13402119 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 681 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 45180 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3683 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 46778 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 25441239 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2526766 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 145081 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1668881823 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4258646 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 454536844 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 185491805 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2961001 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 59126 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7519 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 253991 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5294422 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 459505 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 5753927 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1485801812 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 427360543 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7370917 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 17697010 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2543877 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 131664 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1613864484 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4125995 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 438705092 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 180250261 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2550339 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 45235 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 9141 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 246172 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2357197 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1561193 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3918390 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1455317466 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 417050361 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5547722 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 99045659 # number of nop insts executed -system.cpu.iew.exec_refs 599531836 # number of memory reference insts executed -system.cpu.iew.exec_branches 90620288 # Number of branches executed -system.cpu.iew.exec_stores 172171293 # Number of stores executed -system.cpu.iew.exec_rate 1.817200 # Inst execution rate -system.cpu.iew.wb_sent 1483493878 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1482022964 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1178273779 # num instructions producing a value -system.cpu.iew.wb_consumers 1228157747 # num instructions consuming a value +system.cpu.iew.exec_nop 94187571 # number of nop insts executed +system.cpu.iew.exec_refs 587627055 # number of memory reference insts executed +system.cpu.iew.exec_branches 89112581 # Number of branches executed +system.cpu.iew.exec_stores 170576694 # Number of stores executed +system.cpu.iew.exec_rate 1.872734 # Inst execution rate +system.cpu.iew.wb_sent 1453915806 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1452997343 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1154378236 # num instructions producing a value +system.cpu.iew.wb_consumers 1205398776 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.812578 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.959383 # average fanout of values written-back +system.cpu.iew.wb_rate 1.869748 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957673 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1485108101 # The number of committed instructions system.cpu.commit.commitCommittedOps 1489523295 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 179255835 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 124237250 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5438120 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 791834306 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.881105 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.451655 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3784661 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 759066348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.962310 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.504596 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 260467018 32.89% 32.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288028220 36.37% 69.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 45072234 5.69% 74.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 56206737 7.10% 82.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24021941 3.03% 85.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8787658 1.11% 86.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30300633 3.83% 90.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10698376 1.35% 91.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 68251489 8.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 240497837 31.68% 31.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 276436046 36.42% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43137006 5.68% 73.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54981228 7.24% 81.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19702278 2.60% 83.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13356697 1.76% 85.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30450827 4.01% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10463438 1.38% 90.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70040991 9.23% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 791834306 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 759066348 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108101 # Number of instructions committed system.cpu.commit.committedOps 1489523295 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -271,64 +271,64 @@ system.cpu.commit.branches 86248929 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 68251489 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70040991 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2392297077 # The number of ROB reads -system.cpu.rob.rob_writes 3363039880 # The number of ROB writes -system.cpu.timesIdled 11286 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 357787 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2302721032 # The number of ROB reads +system.cpu.rob.rob_writes 3245242057 # The number of ROB writes +system.cpu.timesIdled 11126 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 345847 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188958 # Number of Instructions Simulated system.cpu.committedOps 1405604152 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188958 # Number of Instructions Simulated -system.cpu.cpi 0.583528 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.583528 # CPI: Total CPI of All Threads -system.cpu.ipc 1.713714 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.713714 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2016058791 # number of integer regfile reads -system.cpu.int_regfile_writes 1303867666 # number of integer regfile writes -system.cpu.fp_regfile_reads 16986540 # number of floating regfile reads -system.cpu.fp_regfile_writes 10452290 # number of floating regfile writes -system.cpu.misc_regfile_reads 605383822 # number of misc regfile reads +system.cpu.cpi 0.554607 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.554607 # CPI: Total CPI of All Threads +system.cpu.ipc 1.803080 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.803080 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1980619731 # number of integer regfile reads +system.cpu.int_regfile_writes 1276281052 # number of integer regfile writes +system.cpu.fp_regfile_reads 16978878 # number of floating regfile reads +system.cpu.fp_regfile_writes 10499994 # number of floating regfile writes +system.cpu.misc_regfile_reads 593300909 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 166 # number of replacements -system.cpu.icache.tagsinuse 1031.400456 # Cycle average of tags in use -system.cpu.icache.total_refs 170772098 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1298 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 131565.560863 # Average number of references to valid blocks. +system.cpu.icache.replacements 200 # number of replacements +system.cpu.icache.tagsinuse 1048.828471 # Cycle average of tags in use +system.cpu.icache.total_refs 162821549 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1351 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 120519.281273 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1031.400456 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.503614 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.503614 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 170772098 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 170772098 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 170772098 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 170772098 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 170772098 # number of overall hits -system.cpu.icache.overall_hits::total 170772098 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1798 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1798 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1798 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1798 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1798 # number of overall misses -system.cpu.icache.overall_misses::total 1798 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62741500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62741500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62741500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62741500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62741500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62741500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 170773896 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 170773896 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 170773896 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 170773896 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 170773896 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 170773896 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000011 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000011 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000011 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34895.161290 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34895.161290 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34895.161290 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1048.828471 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.512123 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.512123 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 162821549 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 162821549 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 162821549 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 162821549 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 162821549 # number of overall hits +system.cpu.icache.overall_hits::total 162821549 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1976 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1976 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1976 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1976 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1976 # number of overall misses +system.cpu.icache.overall_misses::total 1976 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 67232500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 67232500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 67232500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 67232500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 67232500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 67232500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162823525 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162823525 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162823525 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162823525 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162823525 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162823525 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34024.544534 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -337,214 +337,214 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 499 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 499 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 499 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 499 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 499 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 499 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1299 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1299 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1299 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1299 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1299 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1299 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45206000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45206000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45206000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45206000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45206000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45206000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 624 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 624 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 624 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 624 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 624 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 624 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1352 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1352 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1352 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1352 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1352 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1352 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47023000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 47023000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47023000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 47023000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47023000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 47023000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34800.615858 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34800.615858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34800.615858 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34780.325444 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 475353 # number of replacements -system.cpu.dcache.tagsinuse 4095.165283 # Cycle average of tags in use -system.cpu.dcache.total_refs 385593109 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 479449 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 804.242180 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 131001000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.165283 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999796 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999796 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 220654856 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 220654856 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164936934 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164936934 # number of WriteReq hits +system.cpu.dcache.replacements 458031 # number of replacements +system.cpu.dcache.tagsinuse 4095.115790 # Cycle average of tags in use +system.cpu.dcache.total_refs 365778673 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 462127 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 791.511150 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 131565000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.115790 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999784 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999784 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 200803152 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200803152 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164974202 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164974202 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 385591790 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 385591790 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 385591790 # number of overall hits -system.cpu.dcache.overall_hits::total 385591790 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 815916 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 815916 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1909882 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1909882 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365777354 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365777354 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365777354 # number of overall hits +system.cpu.dcache.overall_hits::total 365777354 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 803342 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 803342 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1872614 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1872614 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2725798 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2725798 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2725798 # number of overall misses -system.cpu.dcache.overall_misses::total 2725798 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11966603000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11966603000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 29861651909 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 29861651909 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 268000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 268000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41828254909 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41828254909 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41828254909 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41828254909 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 221470772 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 221470772 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2675956 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2675956 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2675956 # number of overall misses +system.cpu.dcache.overall_misses::total 2675956 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11885207000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11885207000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 29671016952 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 29671016952 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 267000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 267000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41556223952 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41556223952 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41556223952 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41556223952 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201606494 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201606494 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 388317588 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 388317588 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 388317588 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 388317588 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003684 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011447 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 368453310 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 368453310 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 368453310 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 368453310 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003985 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011224 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007020 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007020 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14666.464440 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15635.338680 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38285.714286 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15345.324528 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15345.324528 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2153.846154 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 3000 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.007263 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007263 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14794.703875 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15844.705290 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38142.857143 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2214.285714 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 426654 # number of writebacks -system.cpu.dcache.writebacks::total 426654 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 603731 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 603731 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642625 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1642625 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2246356 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2246356 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2246356 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2246356 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 212185 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 212185 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 267257 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 267257 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 413195 # number of writebacks +system.cpu.dcache.writebacks::total 413195 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 603294 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 603294 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1610542 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1610542 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2213836 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2213836 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2213836 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2213836 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200048 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200048 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262072 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262072 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 479442 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 479442 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 479442 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 479442 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1589383500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1589383500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3625603341 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3625603341 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 247000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 247000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5214986841 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5214986841 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5214986841 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5214986841 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000958 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001602 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 462120 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 462120 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 462120 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 462120 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1554226000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1554226000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3602715222 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3602715222 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 246000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 246000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5156941222 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5156941222 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5156941222 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5156941222 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001235 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001235 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7490.555412 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13565.980839 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 35285.714286 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10877.200665 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10877.200665 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7769.265376 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13747.043644 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 35142.857143 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 75859 # number of replacements -system.cpu.l2cache.tagsinuse 17814.801426 # Cycle average of tags in use -system.cpu.l2cache.total_refs 464590 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 91380 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.084154 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 75325 # number of replacements +system.cpu.l2cache.tagsinuse 17833.274372 # Cycle average of tags in use +system.cpu.l2cache.total_refs 440162 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 90846 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.845145 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15735.123399 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 94.212469 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1985.465558 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.480198 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.002875 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.060592 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.543665 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 179801 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 179822 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 426654 # 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miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199566 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982988 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199566 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34238.148984 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34029.222495 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34411.294082 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34238.148984 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34278.031987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34238.148984 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34278.031987 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -553,44 +553,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59257 # number of writebacks -system.cpu.l2cache.writebacks::total 59257 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1278 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32384 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 33662 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60422 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 60422 # 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average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 59190 # number of writebacks +system.cpu.l2cache.writebacks::total 59190 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1329 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32167 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33496 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60058 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 60058 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1329 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 92225 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 93554 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1329 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 92225 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 93554 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41203500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 997353500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1038557000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1880936000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1880936000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41203500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2878289500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2919493000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41203500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2878289500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2919493000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.160796 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.229160 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31003.386005 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31005.486990 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31318.658630 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index dd2c66002..0aefca8ea 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:08:06 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:30:36 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -19,9 +19,9 @@ info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 3 -info: Increasing stack size by one page. Compressed data 97831 bytes in length Uncompressing Data +info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 5 @@ -40,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 586834596000 because target called exit() +Exiting @ tick 637054100000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index db3272b03..b9dc005fb 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,265 +1,265 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.586835 # Number of seconds simulated -sim_ticks 586834596000 # Number of ticks simulated -final_tick 586834596000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.637054 # Number of seconds simulated +sim_ticks 637054100000 # Number of ticks simulated +final_tick 637054100000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106927 # Simulator instruction rate (inst/s) -host_op_rate 197018 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71302744 # Simulator tick rate (ticks/s) -host_mem_usage 220908 # Number of bytes of host memory used -host_seconds 8230.18 # Real time elapsed on the host +host_inst_rate 99624 # Simulator instruction rate (inst/s) +host_op_rate 183562 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72118142 # Simulator tick rate (ticks/s) +host_mem_usage 221144 # Number of bytes of host memory used +host_seconds 8833.48 # Real time elapsed on the host sim_insts 880025312 # Number of instructions simulated sim_ops 1621493982 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5879616 # Number of bytes read from this memory -system.physmem.bytes_inst_read 57024 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3743488 # Number of bytes written to this memory -system.physmem.num_reads 91869 # Number of read requests responded to by this memory -system.physmem.num_writes 58492 # Number of write requests responded to by this memory +system.physmem.bytes_read 5835840 # Number of bytes read from this memory +system.physmem.bytes_inst_read 58688 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3733184 # Number of bytes written to this memory +system.physmem.num_reads 91185 # Number of read requests responded to by this memory +system.physmem.num_writes 58331 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 10019205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 97172 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 6379119 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 16398324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 9160666 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 92124 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 5860074 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 15020740 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1173669193 # number of cpu cycles simulated +system.cpu.numCycles 1274108201 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 140536614 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 140536614 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7896314 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 133769291 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 132901689 # Number of BTB hits +system.cpu.BPredUnit.lookups 154805091 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 154805091 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 26670333 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 76796607 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 76433583 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 138231227 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1143529036 # Number of instructions fetch has processed -system.cpu.fetch.Branches 140536614 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 132901689 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330118681 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 56348337 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 656952944 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 378 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 136534174 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2392311 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1173574785 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.778199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.100517 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180707581 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1491843077 # Number of instructions fetch has processed +system.cpu.fetch.Branches 154805091 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 76433583 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 402290589 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 93779674 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 624095429 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 186 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1350 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 186629859 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 9332096 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1274045731 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.001845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.237422 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 846464435 72.13% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 17271965 1.47% 73.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15892053 1.35% 74.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 19142892 1.63% 76.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 23218397 1.98% 78.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 16689415 1.42% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 22145456 1.89% 81.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30830267 2.63% 84.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 181919905 15.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 878972627 68.99% 68.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24230578 1.90% 70.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15474142 1.21% 72.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 17847771 1.40% 73.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26734269 2.10% 75.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18266815 1.43% 77.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 28459666 2.23% 79.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39787641 3.12% 82.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 224272222 17.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1173574785 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119741 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.974320 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 240018155 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 564065687 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 224667967 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 96551481 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 48271495 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2053347825 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 48271495 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 288250921 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 136396250 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3594 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 255481832 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 445170693 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2022383034 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 772 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 278054588 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 132157059 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2011799289 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4917261318 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4917257566 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3752 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1274045731 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.121501 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.170892 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 300115536 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 537090427 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 281718880 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 88170292 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 66950596 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2369584116 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 66950596 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 352574967 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 124103280 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2679 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302559797 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 427854412 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2273931919 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 193 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 293394028 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 103133099 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2267658104 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5579907383 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5579899199 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 8184 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 393804639 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 92 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 92 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 795963127 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 515675644 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 225280197 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 353360778 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 147850226 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1972232230 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 190 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1776284004 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 173989 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 350598274 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 640215855 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 140 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1173574785 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.513567 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.313751 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 649663454 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 100 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 100 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 745849512 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 546580267 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 222259773 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 352635383 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 146994929 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2027928806 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 590 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1785553597 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 119193 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 406267408 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 856006289 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 540 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1274045731 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.401483 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.311552 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 268099715 22.84% 22.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 420406461 35.82% 58.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 239398162 20.40% 79.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 159391711 13.58% 92.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 48358537 4.12% 96.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 24330955 2.07% 98.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 11625243 0.99% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1646303 0.14% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 317698 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 347008054 27.24% 27.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 447518543 35.13% 62.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 243291159 19.10% 81.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 151236902 11.87% 93.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 40950901 3.21% 96.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 32374953 2.54% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9944821 0.78% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1368449 0.11% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 351949 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1173574785 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1274045731 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 185497 7.34% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2190114 86.61% 93.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 153108 6.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 236653 9.21% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2158500 84.00% 93.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 174415 6.79% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 26819156 1.51% 1.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1098315644 61.83% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 456429787 25.70% 89.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194719417 10.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46809774 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1066762754 59.74% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 479507335 26.85% 89.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192473734 10.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1776284004 # Type of FU issued -system.cpu.iq.rate 1.513445 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2528719 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001424 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4728845466 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2323038766 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1755173186 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 448 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1751993548 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 207962564 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1785553597 # Type of FU issued +system.cpu.iq.rate 1.401414 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2569568 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001439 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4847841100 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2434377268 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1726804996 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 586 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2320 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 60 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1741313206 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 185 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 208932159 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 96633519 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 76725 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 215178 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 37094140 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 127538142 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 36788 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 189688 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 34073716 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1306 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 2016 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 48271495 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1965747 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 154206 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1972232420 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7113535 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 515675644 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 225280197 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 85 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 69568 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 118 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 215178 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4620478 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3457907 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8078385 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1762068190 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 450602678 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 14215814 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 66950596 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 381980 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 88146 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2027929396 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63814072 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 546580267 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 222259773 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 94 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 48025 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 420 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 189688 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2136326 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24658477 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26794803 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1767571508 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 473890078 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 17982089 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 644481818 # number of memory reference insts executed -system.cpu.iew.exec_branches 111935144 # Number of branches executed -system.cpu.iew.exec_stores 193879140 # Number of stores executed -system.cpu.iew.exec_rate 1.501333 # Inst execution rate -system.cpu.iew.wb_sent 1756702193 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1755173198 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1327558450 # num instructions producing a value -system.cpu.iew.wb_consumers 1975144997 # num instructions consuming a value +system.cpu.iew.exec_refs 665732549 # number of memory reference insts executed +system.cpu.iew.exec_branches 109682584 # Number of branches executed +system.cpu.iew.exec_stores 191842471 # Number of stores executed +system.cpu.iew.exec_rate 1.387301 # Inst execution rate +system.cpu.iew.wb_sent 1728142176 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1726805056 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1262100818 # num instructions producing a value +system.cpu.iew.wb_consumers 1868205499 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.495458 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.672132 # average fanout of values written-back +system.cpu.iew.wb_rate 1.355305 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675569 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 880025312 # The number of committed instructions system.cpu.commit.commitCommittedOps 1621493982 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 350742946 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 406439731 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7896364 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1125303290 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.440940 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.651939 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26670511 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1207095135 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.343303 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.660532 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 343524257 30.53% 30.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 441933791 39.27% 69.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 99674686 8.86% 78.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 136523006 12.13% 90.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 31731928 2.82% 93.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26136643 2.32% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22505633 2.00% 97.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8189692 0.73% 98.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15083654 1.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 437349851 36.23% 36.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 432546759 35.83% 72.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 93488393 7.74% 79.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 134921626 11.18% 90.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 35737028 2.96% 93.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23235805 1.92% 95.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 25789335 2.14% 98.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8868292 0.73% 98.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15158046 1.26% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1125303290 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1207095135 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025312 # Number of instructions committed system.cpu.commit.committedOps 1621493982 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -270,62 +270,62 @@ system.cpu.commit.branches 107161579 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15083654 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15158046 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3082456564 # The number of ROB reads -system.cpu.rob.rob_writes 3992764754 # The number of ROB writes -system.cpu.timesIdled 21723 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 94408 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3219870802 # The number of ROB reads +system.cpu.rob.rob_writes 4122835024 # The number of ROB writes +system.cpu.timesIdled 1341 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 62470 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025312 # Number of Instructions Simulated system.cpu.committedOps 1621493982 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025312 # Number of Instructions Simulated -system.cpu.cpi 1.333677 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.333677 # CPI: Total CPI of All Threads -system.cpu.ipc 0.749807 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.749807 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3268959976 # number of integer regfile reads -system.cpu.int_regfile_writes 1746565098 # number of integer regfile writes -system.cpu.fp_regfile_reads 12 # number of floating regfile reads -system.cpu.misc_regfile_reads 905288155 # number of misc regfile reads -system.cpu.icache.replacements 12 # number of replacements -system.cpu.icache.tagsinuse 807.278486 # Cycle average of tags in use -system.cpu.icache.total_refs 136532946 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 894 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 152721.416107 # Average number of references to valid blocks. +system.cpu.cpi 1.447809 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.447809 # CPI: Total CPI of All Threads +system.cpu.ipc 0.690699 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.690699 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3282350370 # number of integer regfile reads +system.cpu.int_regfile_writes 1699874197 # number of integer regfile writes +system.cpu.fp_regfile_reads 60 # number of floating regfile reads +system.cpu.misc_regfile_reads 911417902 # number of misc regfile reads +system.cpu.icache.replacements 15 # number of replacements +system.cpu.icache.tagsinuse 828.919506 # Cycle average of tags in use +system.cpu.icache.total_refs 186628505 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 920 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 202857.070652 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 807.278486 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.394179 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.394179 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 136532946 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 136532946 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 136532946 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 136532946 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 136532946 # number of overall hits -system.cpu.icache.overall_hits::total 136532946 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1228 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1228 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1228 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1228 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1228 # number of overall misses -system.cpu.icache.overall_misses::total 1228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 43195500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 43195500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 43195500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 43195500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 43195500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 43195500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 136534174 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 136534174 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 136534174 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 136534174 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 136534174 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 136534174 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35175.488599 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35175.488599 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35175.488599 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 828.919506 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.404746 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.404746 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 186628507 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 186628507 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 186628507 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 186628507 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 186628507 # number of overall hits +system.cpu.icache.overall_hits::total 186628507 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1352 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1352 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1352 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1352 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1352 # number of overall misses +system.cpu.icache.overall_misses::total 1352 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 45933500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 45933500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 45933500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 45933500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 45933500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 45933500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 186629859 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 186629859 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 186629859 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 186629859 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 186629859 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 186629859 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33974.482249 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33974.482249 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33974.482249 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -334,80 +334,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 334 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 334 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 334 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 334 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 334 # 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number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 428 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 428 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 924 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 924 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 924 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 924 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 924 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 924 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32509500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32509500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32509500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32509500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32509500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32509500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35183.441558 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35183.441558 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35183.441558 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459037 # number of replacements -system.cpu.dcache.tagsinuse 4094.269422 # Cycle average of tags in use -system.cpu.dcache.total_refs 430357004 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463133 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 929.229841 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 414463000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.269422 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999577 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999577 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 242420503 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 242420503 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 187936501 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 187936501 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 430357004 # 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Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1006.963684 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 723787000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.514188 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999393 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999393 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 264747763 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264747763 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939802 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939802 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 452687565 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 452687565 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 452687565 # 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number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -416,116 +416,120 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 409999 # number of writebacks -system.cpu.dcache.writebacks::total 409999 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3488 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3488 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 35 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3523 # 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mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001075 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7134.356831 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9898.000569 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8623.311777 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8623.311777 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 400737 # number of writebacks +system.cpu.dcache.writebacks::total 400737 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3424 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3424 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 26 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3450 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.545080 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31060.044893 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.428917 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31060.044893 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.428917 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 58331 # number of writebacks +system.cpu.l2cache.writebacks::total 58331 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 917 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31902 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 32819 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58366 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 58366 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 917 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 90268 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 91185 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 917 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 90268 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 91185 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28488000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 989063500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1017551500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1809374000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1809374000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28488000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2798437500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2826925500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28488000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2798437500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2826925500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996739 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.156902 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.237034 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996739 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200792 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996739 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200792 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31066.521265 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.181619 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.479731 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31066.521265 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.434617 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31066.521265 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.434617 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index bc658a4d7..2b7b5d7d4 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:46:15 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:09:43 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 33080570000 because target called exit() +Exiting @ tick 30872383000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 0264f97d4..8b866508b 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033081 # Number of seconds simulated -sim_ticks 33080570000 # Number of ticks simulated -final_tick 33080570000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.030872 # Number of seconds simulated +sim_ticks 30872383000 # Number of ticks simulated +final_tick 30872383000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183696 # Simulator instruction rate (inst/s) -host_op_rate 185015 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67072888 # Simulator tick rate (ticks/s) -host_mem_usage 356156 # Number of bytes of host memory used -host_seconds 493.20 # Real time elapsed on the host -sim_insts 90599331 # Number of instructions simulated -sim_ops 91249885 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 997440 # Number of bytes read from this memory -system.physmem.bytes_inst_read 44864 # Number of instructions bytes read from this memory +host_inst_rate 191980 # Simulator instruction rate (inst/s) +host_op_rate 193358 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65418525 # Simulator tick rate (ticks/s) +host_mem_usage 356268 # Number of bytes of host memory used +host_seconds 471.92 # Real time elapsed on the host +sim_insts 90599371 # Number of instructions simulated +sim_ops 91249925 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 997760 # Number of bytes read from this memory +system.physmem.bytes_inst_read 44992 # Number of instructions bytes read from this memory system.physmem.bytes_written 2048 # Number of bytes written to this memory -system.physmem.num_reads 15585 # Number of read requests responded to by this memory +system.physmem.num_reads 15590 # Number of read requests responded to by this memory system.physmem.num_writes 32 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 30151838 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1356204 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 61909 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 30213748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 32318853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1457354 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 66338 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 32385190 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,316 +64,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 66161141 # number of cpu cycles simulated +system.cpu.numCycles 61744767 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 27503856 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21975755 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1408867 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 24498145 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 23511296 # Number of BTB hits +system.cpu.BPredUnit.lookups 27625975 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21961767 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1057803 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12484908 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 12217504 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 109835 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 10070 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15373267 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 131330347 # Number of instructions fetch has processed -system.cpu.fetch.Branches 27503856 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23621131 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 32575588 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5466804 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 14146452 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 14 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14744727 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 369536 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 66131345 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.004854 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.741973 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 63839 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 9989 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14937013 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 131159638 # Number of instructions fetch has processed +system.cpu.fetch.Branches 27625975 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12281343 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 25187217 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5166004 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 17501831 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 968 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14529102 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 404990 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 61714285 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.143323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.095410 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 33609060 50.82% 50.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6636469 10.04% 60.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5762437 8.71% 69.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4857985 7.35% 76.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2814890 4.26% 81.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1640731 2.48% 83.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1559273 2.36% 86.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2974432 4.50% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6276068 9.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 36568128 59.25% 59.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3588248 5.81% 65.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2263683 3.67% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1635825 2.65% 71.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2193562 3.55% 74.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3029199 4.91% 79.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1536493 2.49% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1081808 1.75% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9817339 15.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 66131345 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.415710 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.985007 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17946387 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12652277 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30529032 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 996648 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4007001 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4433202 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 29411 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 129091783 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32642 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4007001 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 19654593 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1107803 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8424491 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 29777338 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3160119 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 124853428 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 254616 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1879607 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 145685596 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 543523130 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 543516149 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6981 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 38256157 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 662188 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 664356 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 7619540 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29336358 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5741000 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1194254 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 692979 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 117270526 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 648807 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 106162051 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 30561 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26211100 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 62748267 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 93963 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 66131345 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.605321 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761707 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 61714285 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.447422 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.124223 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17894765 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15294092 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 23449441 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 997710 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4078277 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4446063 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 9028 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 129128963 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42641 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4078277 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 19986704 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1990048 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8372890 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 22331092 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4955274 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 124988307 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 34 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 274534 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3719943 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 334 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 145477524 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 543658099 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 543650283 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7816 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429503 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 38048021 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 624217 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 628906 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13326064 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29929002 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5552922 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1387770 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 675384 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118695204 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 614278 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105786177 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 44246 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27759340 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 68809466 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 59426 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 61714285 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.714128 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.857544 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24322505 36.78% 36.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14238731 21.53% 58.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9857797 14.91% 73.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 8080871 12.22% 85.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4216459 6.38% 91.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2267136 3.43% 95.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2478029 3.75% 98.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 463113 0.70% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 206704 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21784376 35.30% 35.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13573552 21.99% 57.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8691007 14.08% 71.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6574195 10.65% 82.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4926850 7.98% 90.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2861627 4.64% 94.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2480649 4.02% 98.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 367635 0.60% 99.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 454394 0.74% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 66131345 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 61714285 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 52363 10.30% 10.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.01% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 192835 37.95% 48.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 262907 51.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 29792 4.51% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 350883 53.15% 57.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 279419 42.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74696385 70.36% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11141 0.01% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 159 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 260 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26155386 24.64% 95.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5298717 4.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74674896 70.59% 70.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10966 0.01% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 250 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 304 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25913310 24.50% 95.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5186446 4.90% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 106162051 # Type of FU issued -system.cpu.iq.rate 1.604598 # Inst issue rate -system.cpu.iq.fu_busy_cnt 508132 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.004786 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 278993240 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144129636 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102521130 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 900 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1354 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 412 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 106669731 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 452 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 366279 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105786177 # Type of FU issued +system.cpu.iq.rate 1.713282 # Inst issue rate +system.cpu.iq.fu_busy_cnt 660121 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006240 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 273989825 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 147067719 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102775878 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1181 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1722 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 504 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106445710 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 588 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 360974 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6760486 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 42468 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 731 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 994251 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7353122 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24732 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 910 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 806165 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30282 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 206 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 30723 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4007001 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 182542 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 28701 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 117958139 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 810273 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29336358 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5741000 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 643936 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9429 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1050 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 731 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1288873 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 210071 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1498944 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104530427 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25743276 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1631624 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4078277 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 189303 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 32978 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 119345782 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 472137 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29929002 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5552922 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 610367 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13002 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 909 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 910 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 660488 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 474136 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1134624 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104503498 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25461820 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1282679 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 38806 # number of nop insts executed -system.cpu.iew.exec_refs 30946109 # number of memory reference insts executed -system.cpu.iew.exec_branches 21214083 # Number of branches executed -system.cpu.iew.exec_stores 5202833 # Number of stores executed -system.cpu.iew.exec_rate 1.579937 # Inst execution rate -system.cpu.iew.wb_sent 102941812 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102521542 # cumulative count of insts written-back -system.cpu.iew.wb_producers 60312663 # num instructions producing a value -system.cpu.iew.wb_consumers 96996327 # num instructions consuming a value +system.cpu.iew.exec_nop 36300 # number of nop insts executed +system.cpu.iew.exec_refs 30578127 # number of memory reference insts executed +system.cpu.iew.exec_branches 21320345 # Number of branches executed +system.cpu.iew.exec_stores 5116307 # Number of stores executed +system.cpu.iew.exec_rate 1.692508 # Inst execution rate +system.cpu.iew.wb_sent 103143555 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102776382 # cumulative count of insts written-back +system.cpu.iew.wb_producers 60808791 # num instructions producing a value +system.cpu.iew.wb_consumers 98854571 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.549573 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.621804 # average fanout of values written-back +system.cpu.iew.wb_rate 1.664536 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.615134 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 90611940 # The number of committed instructions -system.cpu.commit.commitCommittedOps 91262494 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26696996 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 554844 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1392644 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 62124345 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.469029 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.224973 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 90611980 # The number of committed instructions +system.cpu.commit.commitCommittedOps 91262534 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 28084875 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 554852 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1060689 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 57636009 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.583429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.316969 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 28387912 45.70% 45.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16565318 26.66% 72.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5280655 8.50% 80.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3908699 6.29% 87.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2045216 3.29% 90.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 660602 1.06% 91.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 536847 0.86% 92.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 207955 0.33% 92.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4531141 7.29% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 25053220 43.47% 43.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 15762866 27.35% 70.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4731133 8.21% 79.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3928107 6.82% 85.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1673357 2.90% 88.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 949808 1.65% 90.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 650100 1.13% 91.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 189331 0.33% 91.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4698087 8.15% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 62124345 # Number of insts commited each cycle -system.cpu.commit.committedInsts 90611940 # Number of instructions committed -system.cpu.commit.committedOps 91262494 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 57636009 # Number of insts commited each cycle +system.cpu.commit.committedInsts 90611980 # Number of instructions committed +system.cpu.commit.committedOps 91262534 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322621 # Number of memory references committed -system.cpu.commit.loads 22575872 # Number of loads committed +system.cpu.commit.refs 27322637 # Number of memory references committed +system.cpu.commit.loads 22575880 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18722466 # Number of branches committed +system.cpu.commit.branches 18722474 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533302 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533334 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4531141 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4698087 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 175546960 # The number of ROB reads -system.cpu.rob.rob_writes 239939856 # The number of ROB writes -system.cpu.timesIdled 1543 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29796 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 90599331 # Number of Instructions Simulated -system.cpu.committedOps 91249885 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 90599331 # Number of Instructions Simulated -system.cpu.cpi 0.730261 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.730261 # CPI: Total CPI of All Threads -system.cpu.ipc 1.369374 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.369374 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 496902735 # number of integer regfile reads -system.cpu.int_regfile_writes 120936098 # number of integer regfile writes -system.cpu.fp_regfile_reads 197 # number of floating regfile reads -system.cpu.fp_regfile_writes 534 # number of floating regfile writes -system.cpu.misc_regfile_reads 184886717 # number of misc regfile reads -system.cpu.misc_regfile_writes 11594 # number of misc regfile writes -system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 611.587679 # Cycle average of tags in use -system.cpu.icache.total_refs 14743811 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 20420.790859 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 172279597 # The number of ROB reads +system.cpu.rob.rob_writes 242795229 # The number of ROB writes +system.cpu.timesIdled 1482 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30482 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 90599371 # Number of Instructions Simulated +system.cpu.committedOps 91249925 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 90599371 # Number of Instructions Simulated +system.cpu.cpi 0.681514 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.681514 # CPI: Total CPI of All Threads +system.cpu.ipc 1.467321 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.467321 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 496888008 # number of integer regfile reads +system.cpu.int_regfile_writes 120864998 # number of integer regfile writes +system.cpu.fp_regfile_reads 242 # number of floating regfile reads +system.cpu.fp_regfile_writes 665 # number of floating regfile writes +system.cpu.misc_regfile_reads 184727514 # number of misc regfile reads +system.cpu.misc_regfile_writes 11610 # number of misc regfile writes +system.cpu.icache.replacements 3 # number of replacements +system.cpu.icache.tagsinuse 619.944154 # Cycle average of tags in use +system.cpu.icache.total_refs 14528145 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 728 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 19956.243132 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 611.587679 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.298627 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.298627 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14743811 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14743811 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14743811 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14743811 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14743811 # number of overall hits -system.cpu.icache.overall_hits::total 14743811 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 916 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 916 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 916 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 916 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 916 # number of overall misses -system.cpu.icache.overall_misses::total 916 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32376000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32376000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32376000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32376000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32376000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32376000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14744727 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14744727 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14744727 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14744727 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14744727 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14744727 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000062 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000062 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000062 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35344.978166 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35344.978166 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35344.978166 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 619.944154 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.302707 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.302707 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14528145 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14528145 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14528145 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14528145 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14528145 # number of overall hits +system.cpu.icache.overall_hits::total 14528145 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 957 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 957 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 957 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 957 # number of overall misses +system.cpu.icache.overall_misses::total 957 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33256500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33256500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33256500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33256500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33256500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33256500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14529102 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14529102 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14529102 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14529102 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14529102 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14529102 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34750.783699 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34750.783699 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34750.783699 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,214 +382,214 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 194 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 194 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 194 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 194 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 194 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 194 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 722 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24887000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24887000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24887000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24887000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24887000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24887000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000049 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000049 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000049 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34469.529086 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34469.529086 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34469.529086 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 229 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 229 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 229 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 229 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 229 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 229 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 728 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 728 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 728 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 728 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 728 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 728 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24950500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24950500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24950500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24950500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24950500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24950500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000050 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000050 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000050 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34272.664835 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34272.664835 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34272.664835 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943456 # number of replacements -system.cpu.dcache.tagsinuse 3558.808733 # Cycle average of tags in use -system.cpu.dcache.total_refs 28819271 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947552 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 30.414448 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12353041000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3558.808733 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.868850 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.868850 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 24247440 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 24247440 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4559242 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4559242 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 6797 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 6797 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5792 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5792 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28806682 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28806682 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28806682 # number of overall hits -system.cpu.dcache.overall_hits::total 28806682 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 989267 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 989267 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 175739 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 175739 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1165006 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1165006 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1165006 # number of overall misses -system.cpu.dcache.overall_misses::total 1165006 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5475545000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5475545000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4498707428 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4498707428 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 124500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 124500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9974252428 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9974252428 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9974252428 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9974252428 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 25236707 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 25236707 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 943467 # number of replacements +system.cpu.dcache.tagsinuse 3573.833384 # Cycle average of tags in use +system.cpu.dcache.total_refs 28543530 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947563 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 30.123095 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 11199321000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3573.833384 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.872518 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.872518 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23972222 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23972222 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4559610 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4559610 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5898 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5898 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5800 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5800 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28531832 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28531832 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28531832 # number of overall hits +system.cpu.dcache.overall_hits::total 28531832 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 990009 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 990009 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 175371 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 175371 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1165380 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1165380 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1165380 # number of overall misses +system.cpu.dcache.overall_misses::total 1165380 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5599290000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5599290000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4531637443 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4531637443 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 127000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10130927443 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10130927443 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10130927443 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10130927443 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24962231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24962231 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6804 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 6804 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5792 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5792 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29971688 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29971688 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29971688 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29971688 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039200 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037115 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001029 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.038870 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038870 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5534.951636 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25598.799515 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17785.714286 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8561.545973 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8561.545973 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23239503 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5906 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5906 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5800 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5800 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29697212 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29697212 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29697212 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29697212 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039660 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037037 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001355 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.039242 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039242 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5655.797069 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25840.289689 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15875 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8693.239495 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8693.239495 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23215506 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8123 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8117 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.950757 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.109154 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942907 # number of writebacks -system.cpu.dcache.writebacks::total 942907 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 86240 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 86240 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131213 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 131213 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 217453 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 217453 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 217453 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 217453 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903027 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903027 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 44526 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 44526 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947553 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947553 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947553 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947553 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2253076500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2253076500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1081063056 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1081063056 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3334139556 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3334139556 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3334139556 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3334139556 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035782 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009404 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031615 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031615 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2495.026727 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24279.366123 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3518.683974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3518.683974 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 942867 # number of writebacks +system.cpu.dcache.writebacks::total 942867 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 86758 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 86758 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131059 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 131059 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 217817 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 217817 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 217817 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 217817 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903251 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903251 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 44312 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 44312 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947563 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947563 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947563 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947563 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2324909500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2324909500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1081042568 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1081042568 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3405952068 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3405952068 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3405952068 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3405952068 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036185 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009358 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031907 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031907 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2573.935152 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24396.158332 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3594.433371 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3594.433371 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 744 # number of replacements -system.cpu.l2cache.tagsinuse 9229.669691 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1596774 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15569 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 102.561115 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 755 # number of replacements +system.cpu.l2cache.tagsinuse 9376.851207 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1597250 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15574 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 102.558752 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8836.877415 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 199.760007 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 193.032269 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.269680 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.006096 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.005891 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.281667 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 901393 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 901413 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942907 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942907 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 31267 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 31267 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932660 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932680 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932660 # number of overall hits -system.cpu.l2cache.overall_hits::total 932680 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 702 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 355 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1057 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 702 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14893 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15595 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 702 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14893 # number of overall misses -system.cpu.l2cache.overall_misses::total 15595 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24071000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12138000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 36209000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 498763000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 498763000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24071000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 510901000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 534972000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24071000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 510901000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 534972000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 901748 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 902470 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 942907 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942907 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 45805 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 45805 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 722 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 947553 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 948275 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 722 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 947553 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 948275 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.972299 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000394 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.317389 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.972299 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015717 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.972299 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015717 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34289.173789 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34191.549296 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34307.538864 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34289.173789 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34304.774055 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34289.173789 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34304.774055 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 8984.898235 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 195.884523 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 196.068450 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.274197 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.005978 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.005984 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.286159 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 901676 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 901700 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942867 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942867 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 30990 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 30990 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932666 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932690 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 932666 # number of overall hits +system.cpu.l2cache.overall_hits::total 932690 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 704 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 360 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1064 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 14537 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 14537 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 704 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14897 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15601 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 704 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14897 # number of overall misses +system.cpu.l2cache.overall_misses::total 15601 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24129500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12327000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 36456500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 499453000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 499453000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24129500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 511780000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 535909500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24129500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 511780000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 535909500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 728 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 902036 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 902764 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942867 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942867 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 45527 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 45527 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 728 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 947563 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 948291 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 728 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 947563 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948291 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967033 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000399 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.319305 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967033 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015721 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967033 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015721 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34274.857955 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34241.666667 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34357.363968 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34274.857955 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34354.568034 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34274.857955 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34354.568034 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,50 +601,50 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks system.cpu.l2cache.writebacks::total 32 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 701 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 346 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1047 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 701 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14884 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15585 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 701 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14884 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15585 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21793500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10767000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32560500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 451777500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 451777500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21793500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 462544500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 484338000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21793500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 462544500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 484338000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.970914 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000384 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.317389 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.970914 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015708 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.970914 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015708 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31089.158345 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31118.497110 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31075.629385 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31089.158345 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31076.625907 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31089.158345 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31076.625907 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 703 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 350 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1053 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14537 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14537 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 703 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14887 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15590 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 703 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14887 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15590 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21846000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10912500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32758500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 452369000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 452369000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21846000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 463281500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 485127500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21846000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 463281500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 485127500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000388 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.319305 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31075.391181 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31178.571429 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31118.456353 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31075.391181 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31119.869685 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31075.391181 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31119.869685 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 90035090e..f02df016b 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:13:01 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:37:07 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,6 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 70046988500 because target called exit() +info: Increasing stack size by one page. +info: Increasing stack size by one page. +Exiting @ tick 67367177000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 1bd6324e3..652133ba6 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,265 +1,265 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.070047 # Number of seconds simulated -sim_ticks 70046988500 # Number of ticks simulated -final_tick 70046988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.067367 # Number of seconds simulated +sim_ticks 67367177000 # Number of ticks simulated +final_tick 67367177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120922 # Simulator instruction rate (inst/s) -host_op_rate 212925 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53613076 # Simulator tick rate (ticks/s) -host_mem_usage 355612 # Number of bytes of host memory used -host_seconds 1306.53 # Real time elapsed on the host +host_inst_rate 124120 # Simulator instruction rate (inst/s) +host_op_rate 218555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52925417 # Simulator tick rate (ticks/s) +host_mem_usage 355732 # Number of bytes of host memory used +host_seconds 1272.87 # Real time elapsed on the host sim_insts 157988582 # Number of instructions simulated sim_ops 278192519 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 3895936 # Number of bytes read from this memory -system.physmem.bytes_inst_read 65216 # Number of instructions bytes read from this memory -system.physmem.bytes_written 892288 # Number of bytes written to this memory -system.physmem.num_reads 60874 # Number of read requests responded to by this memory -system.physmem.num_writes 13942 # Number of write requests responded to by this memory +system.physmem.bytes_read 3905024 # Number of bytes read from this memory +system.physmem.bytes_inst_read 69056 # Number of instructions bytes read from this memory +system.physmem.bytes_written 895552 # Number of bytes written to this memory +system.physmem.num_reads 61016 # Number of read requests responded to by this memory +system.physmem.num_writes 13993 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 55618894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 931032 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 12738421 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 68357314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 57966270 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1025069 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 13293595 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 71259866 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 140093978 # number of cpu cycles simulated +system.cpu.numCycles 134734355 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 37937752 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 37937752 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1331995 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 33815417 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 33320649 # Number of BTB hits +system.cpu.BPredUnit.lookups 36117705 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 36117705 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1086223 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 25647744 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 25539011 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29024363 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 203514307 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37937752 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33320649 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 63466806 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 10233892 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37945043 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 68 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 28213885 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 212642 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 139306492 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.579216 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.290579 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27986454 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 196428178 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36117705 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 25539011 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59419496 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8404854 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 39237097 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 161 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 27269445 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 142050 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 133931620 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.578005 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.358197 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 78286088 56.20% 56.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3759512 2.70% 58.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2809249 2.02% 60.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4511465 3.24% 64.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7046412 5.06% 69.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5071327 3.64% 72.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 7671850 5.51% 78.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4389018 3.15% 81.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25761571 18.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 77253594 57.68% 57.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2167416 1.62% 59.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2996676 2.24% 61.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4105343 3.07% 64.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8023701 5.99% 70.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5042154 3.76% 74.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2892095 2.16% 76.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1463696 1.09% 77.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 29986945 22.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 139306492 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.270802 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.452698 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 41961886 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 28163540 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 52299140 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8011732 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8870194 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 354926885 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 8870194 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 48488899 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4721769 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9082 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 53110553 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24105995 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 349921643 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 18 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 105361 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20166032 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 314159745 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 860584858 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 860581891 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2967 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 133931620 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.268066 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.457892 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40456608 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 30121503 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46487725 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9577404 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7288380 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 341192383 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 7288380 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45850157 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5075267 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9166 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 50344983 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25363667 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 337332641 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 37 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24553 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 23217040 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 301814702 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 829797290 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 829794179 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3111 # Number of floating rename lookups system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65815553 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 479 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 473 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 57293063 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 112603571 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37556545 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 47800126 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8208845 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343290045 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2336 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 316029105 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 76885 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 64917017 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 92716043 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1890 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 139306492 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.268588 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.744230 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 53470510 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 483 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 475 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 56181617 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 108142373 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37171875 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 46300098 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7898843 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 331653497 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2738 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 311383007 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 186497 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 53202508 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 70962751 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2292 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 133931620 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.324940 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.724540 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 32068137 23.02% 23.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17712067 12.71% 35.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24423194 17.53% 53.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 32289069 23.18% 76.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18335734 13.16% 89.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 9491103 6.81% 96.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3154604 2.26% 98.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1783304 1.28% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 49280 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 27909124 20.84% 20.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17260254 12.89% 33.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25571257 19.09% 52.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 31151034 23.26% 76.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 17658757 13.18% 89.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 9043417 6.75% 96.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3762327 2.81% 98.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1502538 1.12% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 72912 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 139306492 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 133931620 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 25569 1.30% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1859415 94.86% 96.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 75095 3.83% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 23628 1.12% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1962682 92.75% 93.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 129707 6.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 180131547 57.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 149 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101432595 32.10% 89.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34448103 10.90% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31371 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 177172854 56.90% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 149 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 99705652 32.02% 88.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34472981 11.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 316029105 # Type of FU issued -system.cpu.iq.rate 2.255836 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1960079 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006202 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 773400844 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 408240794 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 312293905 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 822 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1922 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 316 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 317972066 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 407 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 52311971 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 311383007 # Type of FU issued +system.cpu.iq.rate 2.311088 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2116017 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006796 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 758999086 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 384888890 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 308243683 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1062 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1674 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 367 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 313467157 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 496 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 52573681 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 21824183 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 143830 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34021 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6116794 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17362985 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 99732 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32451 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 5732124 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3244 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3822 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3310 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3854 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8870194 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 981730 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 88786 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343292381 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 39929 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 112603571 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37556545 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 466 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1316 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 42406 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34021 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1234482 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 211725 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1446207 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 313835720 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100810143 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2193385 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7288380 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 913145 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 89980 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 331656235 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 45880 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 108142373 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 37171875 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 476 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1173 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 43472 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32451 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 613492 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 579011 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1192503 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 309419383 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 99171010 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1963624 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 134854161 # number of memory reference insts executed -system.cpu.iew.exec_branches 31726163 # Number of branches executed -system.cpu.iew.exec_stores 34044018 # Number of stores executed -system.cpu.iew.exec_rate 2.240180 # Inst execution rate -system.cpu.iew.wb_sent 313006075 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 312294221 # cumulative count of insts written-back -system.cpu.iew.wb_producers 231754622 # num instructions producing a value -system.cpu.iew.wb_consumers 317218208 # num instructions consuming a value +system.cpu.iew.exec_refs 133254790 # number of memory reference insts executed +system.cpu.iew.exec_branches 31526578 # Number of branches executed +system.cpu.iew.exec_stores 34083780 # Number of stores executed +system.cpu.iew.exec_rate 2.296514 # Inst execution rate +system.cpu.iew.wb_sent 308790761 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 308244050 # cumulative count of insts written-back +system.cpu.iew.wb_producers 227493444 # num instructions producing a value +system.cpu.iew.wb_consumers 314310835 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.229177 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.730584 # average fanout of values written-back +system.cpu.iew.wb_rate 2.287791 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.723785 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 157988582 # The number of committed instructions system.cpu.commit.commitCommittedOps 278192519 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 65103374 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 53467881 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1332005 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130436298 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.132785 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.651894 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1086244 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126643240 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.196663 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.674492 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 49351461 37.84% 37.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 24978168 19.15% 56.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 17073618 13.09% 70.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12436945 9.53% 79.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3526211 2.70% 82.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3453253 2.65% 84.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2711146 2.08% 87.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1125673 0.86% 87.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15779823 12.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 46336828 36.59% 36.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 24193827 19.10% 55.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 16853923 13.31% 69.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12623187 9.97% 78.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3354078 2.65% 81.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3557907 2.81% 84.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2707686 2.14% 86.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1157110 0.91% 87.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15858694 12.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130436298 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126643240 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988582 # Number of instructions committed system.cpu.commit.committedOps 278192519 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -270,63 +270,63 @@ system.cpu.commit.branches 29309710 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186227 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15779823 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15858694 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 457952368 # The number of ROB reads -system.cpu.rob.rob_writes 695479183 # The number of ROB writes -system.cpu.timesIdled 23894 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 787486 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 442444946 # The number of ROB reads +system.cpu.rob.rob_writes 670617818 # The number of ROB writes +system.cpu.timesIdled 23939 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 802735 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988582 # Number of Instructions Simulated system.cpu.committedOps 278192519 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988582 # Number of Instructions Simulated -system.cpu.cpi 0.886735 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.886735 # CPI: Total CPI of All Threads -system.cpu.ipc 1.127733 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.127733 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 554395898 # number of integer regfile reads -system.cpu.int_regfile_writes 279799467 # number of integer regfile writes -system.cpu.fp_regfile_reads 352 # number of floating regfile reads -system.cpu.fp_regfile_writes 262 # number of floating regfile writes -system.cpu.misc_regfile_reads 200946158 # number of misc regfile reads -system.cpu.icache.replacements 64 # number of replacements -system.cpu.icache.tagsinuse 822.534021 # Cycle average of tags in use -system.cpu.icache.total_refs 28212585 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1024 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 27551.352539 # Average number of references to valid blocks. +system.cpu.cpi 0.852811 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.852811 # CPI: Total CPI of All Threads +system.cpu.ipc 1.172593 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.172593 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 549500021 # number of integer regfile reads +system.cpu.int_regfile_writes 275642637 # number of integer regfile writes +system.cpu.fp_regfile_reads 429 # number of floating regfile reads +system.cpu.fp_regfile_writes 242 # number of floating regfile writes +system.cpu.misc_regfile_reads 197910962 # number of misc regfile reads +system.cpu.icache.replacements 103 # number of replacements +system.cpu.icache.tagsinuse 848.450455 # Cycle average of tags in use +system.cpu.icache.total_refs 27268036 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1093 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24947.882891 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 822.534021 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.401628 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.401628 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 28212585 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 28212585 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 28212585 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 28212585 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 28212585 # number of overall hits -system.cpu.icache.overall_hits::total 28212585 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1300 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1300 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1300 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1300 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1300 # number of overall misses -system.cpu.icache.overall_misses::total 1300 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 46952500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 46952500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 46952500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 46952500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 46952500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 46952500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 28213885 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 28213885 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 28213885 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 28213885 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 28213885 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 28213885 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000046 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000046 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000046 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36117.307692 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36117.307692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36117.307692 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 848.450455 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.414282 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.414282 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 27268036 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27268036 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27268036 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27268036 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27268036 # number of overall hits +system.cpu.icache.overall_hits::total 27268036 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1409 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1409 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1409 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1409 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1409 # number of overall misses +system.cpu.icache.overall_misses::total 1409 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 50108000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 50108000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 50108000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 50108000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 50108000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 50108000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27269445 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27269445 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27269445 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27269445 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27269445 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27269445 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35562.810504 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35562.810504 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35562.810504 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -335,80 +335,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 275 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 275 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 275 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 275 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 275 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 275 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1025 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1025 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1025 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1025 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1025 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36071500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36071500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36071500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36071500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36071500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36071500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000036 # 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number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1094 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1094 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1094 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38230000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 38230000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38230000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 38230000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38230000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 38230000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34945.155393 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34945.155393 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34945.155393 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072906 # number of replacements -system.cpu.dcache.tagsinuse 4073.029614 # Cycle average of tags in use -system.cpu.dcache.total_refs 77489413 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2077002 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.308300 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 23588256000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4073.029614 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994392 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994392 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 46135653 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 46135653 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31353751 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31353751 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 77489404 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 77489404 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 77489404 # number of overall hits -system.cpu.dcache.overall_hits::total 77489404 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2289012 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2289012 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 86000 # 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number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15268016288 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 48424665 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 48424665 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2072116 # number of replacements +system.cpu.dcache.tagsinuse 4072.716490 # Cycle average of tags in use +system.cpu.dcache.total_refs 75611002 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076212 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 36.417766 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 22583642000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.716490 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994316 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994316 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 44257159 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 44257159 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31353834 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31353834 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 75610993 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 75610993 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 75610993 # number of overall hits +system.cpu.dcache.overall_hits::total 75610993 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2289224 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2289224 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 85917 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 85917 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2375141 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2375141 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2375141 # number of overall misses +system.cpu.dcache.overall_misses::total 2375141 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13801326000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13801326000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1502330294 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1502330294 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15303656294 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15303656294 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15303656294 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15303656294 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 46546383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 46546383 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 79864416 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 79864416 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 79864416 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 79864416 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047270 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002735 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.029738 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.029738 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6014.285203 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17456.340558 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 6428.605956 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 6428.605956 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 77986134 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77986134 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77986134 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77986134 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049182 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002733 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.030456 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.030456 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6028.822867 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17485.832769 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 6443.262229 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 6443.262229 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -417,121 +417,121 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1880780 # number of writebacks -system.cpu.dcache.writebacks::total 1880780 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 294089 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 294089 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3918 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3918 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 298007 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 298007 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 298007 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 298007 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994923 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994923 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82082 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82082 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2077005 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2077005 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2077005 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2077005 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5565133500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5565133500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1157645788 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1157645788 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6722779288 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6722779288 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6722779288 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6722779288 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041196 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 1879081 # number of writebacks +system.cpu.dcache.writebacks::total 1879081 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295092 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 295092 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3834 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3834 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 298926 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 298926 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 298926 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 298926 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994132 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994132 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82083 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82083 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076215 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076215 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076215 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076215 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5588966000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5588966000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1158785294 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1158785294 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6747751294 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6747751294 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6747751294 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6747751294 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042842 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2789.648272 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14103.528033 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3236.766059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3236.766059 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026623 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026623 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2802.706140 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14117.238576 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3250.025308 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3250.025308 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 243.086422 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 5793.952244 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.394530 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.007418 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.176817 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.578766 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1964440 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1964445 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1880780 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1880780 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 52709 # 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number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82215 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1093 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076214 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077307 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1093 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076214 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077307 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.987191 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.015257 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358943 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995117 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.028818 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995117 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.028818 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34262.512267 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34153.615451 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34093.111510 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34262.512267 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34123.782474 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34262.512267 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34123.782474 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358998 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.987191 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.028868 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.987191 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.028868 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34272.474513 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34159.818552 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34092.613925 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34272.474513 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34126.724728 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34272.474513 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34126.724728 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,50 +540,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 13942 # number of writebacks -system.cpu.l2cache.writebacks::total 13942 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1019 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30342 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 31361 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856136500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1887779500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31643000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856136500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1887779500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.015211 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 915036000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 915036000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33519500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1858773500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1892293000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33519500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1858773500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1892293000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.987191 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.015257 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358943 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028818 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028818 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.993131 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.071188 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358998 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.987191 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028868 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.987191 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028868 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.338276 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31021.546907 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.762376 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.993131 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.550497 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.993131 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.550497 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.405556 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.338276 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31012.121060 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.338276 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31012.121060 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index f2e7dd662..4e6ce5d2a 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:53:02 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:11:33 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 274128411000 because target called exit() +Exiting @ tick 237773144000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index de8607854..12ab99f41 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.274128 # Number of seconds simulated -sim_ticks 274128411000 # Number of ticks simulated -final_tick 274128411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.237773 # Number of seconds simulated +sim_ticks 237773144000 # Number of ticks simulated +final_tick 237773144000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133293 # Simulator instruction rate (inst/s) -host_op_rate 150155 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71792865 # Simulator tick rate (ticks/s) -host_mem_usage 228092 # Number of bytes of host memory used -host_seconds 3818.32 # Real time elapsed on the host -sim_insts 508954626 # Number of instructions simulated -sim_ops 573341187 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 15240192 # Number of bytes read from this memory -system.physmem.bytes_inst_read 229568 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10959680 # Number of bytes written to this memory -system.physmem.num_reads 238128 # Number of read requests responded to by this memory -system.physmem.num_writes 171245 # Number of write requests responded to by this memory +host_inst_rate 146125 # Simulator instruction rate (inst/s) +host_op_rate 164611 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68266787 # Simulator tick rate (ticks/s) +host_mem_usage 228468 # Number of bytes of host memory used +host_seconds 3483.00 # Real time elapsed on the host +sim_insts 508954831 # Number of instructions simulated +sim_ops 573341392 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 15219328 # Number of bytes read from this memory +system.physmem.bytes_inst_read 242816 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10954048 # Number of bytes written to this memory +system.physmem.num_reads 237802 # Number of read requests responded to by this memory +system.physmem.num_writes 171157 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 55595084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 837447 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 39980095 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 95575179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 64007767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1021209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 46069324 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 110077091 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,315 +64,315 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 548256823 # number of cpu cycles simulated +system.cpu.numCycles 475546289 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 224897268 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 178814817 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18282790 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 189563731 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 156236753 # Number of BTB hits +system.cpu.BPredUnit.lookups 201118526 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 157326791 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 13717812 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 115015344 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 100642141 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 11742995 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2591276 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 154191878 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 995397299 # Number of instructions fetch has processed -system.cpu.fetch.Branches 224897268 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 167979748 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 252064252 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 69921430 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 88879876 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 76 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 27589 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 141619226 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4743130 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 544471710 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.119468 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.816244 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 10773560 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2444561 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 139270247 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 897566716 # Number of instructions fetch has processed +system.cpu.fetch.Branches 201118526 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 111415701 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 200565082 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 55484178 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 92468709 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 69 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 57772 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 128673930 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3900313 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 471730156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.235169 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.071802 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 292419737 53.71% 53.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 22605861 4.15% 57.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39604588 7.27% 65.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 38612877 7.09% 72.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 44079940 8.10% 80.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15590470 2.86% 83.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 18445012 3.39% 86.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 13511392 2.48% 89.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 59601833 10.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 271176826 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 15439241 3.27% 60.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22205632 4.71% 65.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 23455924 4.97% 70.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27555464 5.84% 76.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13622297 2.89% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13443686 2.85% 82.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 13465943 2.85% 84.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 71365143 15.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 544471710 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.410204 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.815568 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 173466263 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 84575198 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 232805016 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4404092 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 49221141 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33081437 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 88923 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1069021878 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 219487 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 49221141 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 189418333 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6243189 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 67194010 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 221110320 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 11284717 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 983280870 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1088 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2966299 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5203884 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 24 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1174814245 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4267939396 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4267936218 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3178 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672199336 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 502614909 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6158838 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6158596 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 63324865 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 196341124 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 77971699 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 17887364 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12637820 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 869953710 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7817073 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 735125256 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1650830 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 301557809 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 749773525 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3938874 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 544471710 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.350162 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.594792 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 471730156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.422921 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.887443 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 155306709 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 88053503 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 184585127 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4622182 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 39162635 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 30800384 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 208217 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 978321020 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 232355 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 39162635 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 168791117 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6653114 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 68132598 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 175576746 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13413946 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 897480764 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1345 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2815262 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7531261 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 34 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1053491537 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3898622100 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3898617765 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4335 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672199664 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 381291873 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6229815 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6227679 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 73783257 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 185038415 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 74452080 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 16894922 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11270431 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 807932126 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7506931 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 704469962 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1695866 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 239081434 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 584885650 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3628691 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 471730156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.493375 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.700371 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 241490713 44.35% 44.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 95232425 17.49% 61.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 86360231 15.86% 77.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 58954468 10.83% 88.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 37235413 6.84% 95.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14676941 2.70% 98.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6419263 1.18% 99.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3351018 0.62% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 751238 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 199497504 42.29% 42.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 75863834 16.08% 58.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 72319675 15.33% 73.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 60290914 12.78% 86.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 35341098 7.49% 93.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15480382 3.28% 97.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7623367 1.62% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3919524 0.83% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1393858 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 544471710 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 471730156 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 133047 1.38% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6635057 68.81% 70.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2874860 29.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 439890 4.44% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6794232 68.56% 73.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2675170 27.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 497160573 67.63% 67.63% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 379945 0.05% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 138 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 170682566 23.22% 90.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 66902031 9.10% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 475256545 67.46% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 387188 0.05% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 152 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 163321629 23.18% 90.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 65504445 9.30% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 735125256 # Type of FU issued -system.cpu.iq.rate 1.340841 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9642964 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013117 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2026015704 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1179385447 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 693708754 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 312 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 466 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 704469962 # Type of FU issued +system.cpu.iq.rate 1.481391 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9909292 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014066 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1892274898 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1054577614 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 670769247 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 340 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 736 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 744768062 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 158 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8478103 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 714379082 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9015037 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 69568189 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 50872 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 61447 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 20367843 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 58265439 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 44467 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 61251 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16848183 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 28247 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 358 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 21514 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 311 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 49221141 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2690580 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 121747 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 887104350 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 12434546 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 196341124 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 77971699 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6076746 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 46013 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7579 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 61447 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 18517236 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5450893 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 23968129 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 710591708 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 161345852 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 24533548 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 39162635 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2883414 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 177046 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 825140786 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8538399 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 185038415 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 74452080 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6018162 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 86541 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8726 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 61251 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11204470 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 7715069 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18919539 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 684747739 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 156362538 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19722223 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9333567 # number of nop insts executed -system.cpu.iew.exec_refs 226275553 # number of memory reference insts executed -system.cpu.iew.exec_branches 147479421 # Number of branches executed -system.cpu.iew.exec_stores 64929701 # Number of stores executed -system.cpu.iew.exec_rate 1.296093 # Inst execution rate -system.cpu.iew.wb_sent 699249012 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 693708770 # cumulative count of insts written-back -system.cpu.iew.wb_producers 395011112 # num instructions producing a value -system.cpu.iew.wb_consumers 663436791 # num instructions consuming a value +system.cpu.iew.exec_nop 9701729 # number of nop insts executed +system.cpu.iew.exec_refs 220343005 # number of memory reference insts executed +system.cpu.iew.exec_branches 142216769 # Number of branches executed +system.cpu.iew.exec_stores 63980467 # Number of stores executed +system.cpu.iew.exec_rate 1.439918 # Inst execution rate +system.cpu.iew.wb_sent 675765320 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 670769263 # cumulative count of insts written-back +system.cpu.iew.wb_producers 382570075 # num instructions producing a value +system.cpu.iew.wb_consumers 656640727 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.265299 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.595401 # average fanout of values written-back +system.cpu.iew.wb_rate 1.410524 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.582617 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 510298510 # The number of committed instructions -system.cpu.commit.commitCommittedOps 574685071 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 312438031 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3878199 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 20478103 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 495250570 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.160393 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.863970 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 510298715 # The number of committed instructions +system.cpu.commit.commitCommittedOps 574685276 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 250472455 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3878240 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15860538 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 432567522 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.328545 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.050034 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 259977309 52.49% 52.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116342120 23.49% 75.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 44473265 8.98% 84.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 21252753 4.29% 89.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19820819 4.00% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7387112 1.49% 94.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7391590 1.49% 96.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3775030 0.76% 97.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14830572 2.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 212834429 49.20% 49.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104865988 24.24% 73.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 39942503 9.23% 82.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 19801516 4.58% 87.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17404518 4.02% 91.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7252453 1.68% 92.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7574279 1.75% 94.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3930965 0.91% 95.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 18960871 4.38% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 495250570 # Number of insts commited each cycle -system.cpu.commit.committedInsts 510298510 # Number of instructions committed -system.cpu.commit.committedOps 574685071 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 432567522 # Number of insts commited each cycle +system.cpu.commit.committedInsts 510298715 # Number of instructions committed +system.cpu.commit.committedOps 574685276 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184376791 # Number of memory references committed -system.cpu.commit.loads 126772935 # Number of loads committed +system.cpu.commit.refs 184376873 # Number of memory references committed +system.cpu.commit.loads 126772976 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 120192120 # Number of branches committed +system.cpu.commit.branches 120192161 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473701217 # Number of committed integer instructions. +system.cpu.commit.int_insts 473701381 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14830572 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 18960871 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1367535962 # The number of ROB reads -system.cpu.rob.rob_writes 1823647630 # The number of ROB writes -system.cpu.timesIdled 94158 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3785113 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 508954626 # Number of Instructions Simulated -system.cpu.committedOps 573341187 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 508954626 # Number of Instructions Simulated -system.cpu.cpi 1.077221 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.077221 # CPI: Total CPI of All Threads -system.cpu.ipc 0.928314 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.928314 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3289345591 # number of integer regfile reads -system.cpu.int_regfile_writes 815117578 # number of integer regfile writes +system.cpu.rob.rob_reads 1238757244 # The number of ROB reads +system.cpu.rob.rob_writes 1689633153 # The number of ROB writes +system.cpu.timesIdled 98384 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3816133 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 508954831 # Number of Instructions Simulated +system.cpu.committedOps 573341392 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 508954831 # Number of Instructions Simulated +system.cpu.cpi 0.934359 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.934359 # CPI: Total CPI of All Threads +system.cpu.ipc 1.070253 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.070253 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3178302017 # number of integer regfile reads +system.cpu.int_regfile_writes 781282618 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1230585750 # number of misc regfile reads -system.cpu.misc_regfile_writes 4463842 # number of misc regfile writes -system.cpu.icache.replacements 12883 # number of replacements -system.cpu.icache.tagsinuse 1062.179544 # Cycle average of tags in use -system.cpu.icache.total_refs 141602716 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 14723 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 9617.789581 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 1130957302 # number of misc regfile reads +system.cpu.misc_regfile_writes 4463924 # number of misc regfile writes +system.cpu.icache.replacements 15572 # number of replacements +system.cpu.icache.tagsinuse 1101.255140 # Cycle average of tags in use +system.cpu.icache.total_refs 128654642 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 17427 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7382.489356 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1062.179544 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.518642 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.518642 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 141602717 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 141602717 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 141602717 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 141602717 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 141602717 # number of overall hits -system.cpu.icache.overall_hits::total 141602717 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 16509 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 16509 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 16509 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 16509 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 16509 # number of overall misses -system.cpu.icache.overall_misses::total 16509 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 235489500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 235489500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 235489500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 235489500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 235489500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 235489500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 141619226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 141619226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 141619226 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 141619226 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 141619226 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 141619226 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000117 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000117 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000117 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14264.310376 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14264.310376 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14264.310376 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1101.255140 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.537722 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.537722 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 128654644 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 128654644 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 128654644 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 128654644 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 128654644 # number of overall hits +system.cpu.icache.overall_hits::total 128654644 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19286 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19286 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19286 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19286 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19286 # number of overall misses +system.cpu.icache.overall_misses::total 19286 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 260902000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 260902000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 260902000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 260902000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 260902000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 260902000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 128673930 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 128673930 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 128673930 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 128673930 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 128673930 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 128673930 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000150 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000150 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000150 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13528.051436 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13528.051436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13528.051436 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,226 +381,226 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1646 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1646 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1646 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 154537000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 154537000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 154537000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10397.429859 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10397.429859 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10397.429859 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 2 # number of writebacks +system.cpu.icache.writebacks::total 2 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1714 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1714 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1714 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1714 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1714 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1714 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17572 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 17572 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 17572 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 17572 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 17572 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 17572 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168050000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 168050000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168050000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 168050000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168050000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 168050000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000137 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000137 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000137 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9563.510130 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9563.510130 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9563.510130 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1212291 # number of replacements -system.cpu.dcache.tagsinuse 4058.220860 # Cycle average of tags in use -system.cpu.dcache.total_refs 203801196 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1216387 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.546345 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5623769000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4058.220860 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.990777 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.990777 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 146308743 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146308743 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 52772298 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 52772298 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2488014 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2488014 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 2231920 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 2231920 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 199081041 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 199081041 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 199081041 # number of overall hits -system.cpu.dcache.overall_hits::total 199081041 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1241922 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1241922 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1467008 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1467008 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 55 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 55 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2708930 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2708930 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2708930 # number of overall misses -system.cpu.dcache.overall_misses::total 2708930 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14257023500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14257023500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24962643993 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24962643993 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 523000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 523000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39219667493 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39219667493 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39219667493 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39219667493 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 147550665 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 147550665 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1204759 # number of replacements +system.cpu.dcache.tagsinuse 4053.244205 # Cycle average of tags in use +system.cpu.dcache.total_refs 198410390 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1208855 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 164.130843 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5569662000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4053.244205 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.989562 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.989562 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 141155461 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 141155461 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 52782371 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 52782371 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2240321 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2240321 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 2231961 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 2231961 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 193937832 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 193937832 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 193937832 # number of overall hits +system.cpu.dcache.overall_hits::total 193937832 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1317563 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1317563 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1456935 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1456935 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 75 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 75 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2774498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2774498 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2774498 # number of overall misses +system.cpu.dcache.overall_misses::total 2774498 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15319546000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15319546000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25044558500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25044558500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 722500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 722500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 40364104500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 40364104500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 40364104500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 40364104500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 142473024 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 142473024 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2488069 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2488069 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231920 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 2231920 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201789971 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201789971 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201789971 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201789971 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008417 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027047 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000022 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.013425 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.013425 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11479.805898 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17016.024448 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9509.090909 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14477.918401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14477.918401 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2240396 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2240396 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231961 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 2231961 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 196712330 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 196712330 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 196712330 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 196712330 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009248 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026861 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000033 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014104 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014104 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11627.182913 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17189.894196 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9633.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14548.255036 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14548.255036 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 484000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 563000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 61 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 92 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7934.426230 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 6119.565217 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1079423 # number of writebacks -system.cpu.dcache.writebacks::total 1079423 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365990 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 365990 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1126420 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1126420 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 55 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 55 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1492410 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1492410 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1492410 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1492410 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 875932 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 875932 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 340588 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 340588 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1216520 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1216520 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1216520 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1216520 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6305474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6305474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4364186500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4364186500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10669660500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10669660500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10669660500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10669660500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005936 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006279 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006029 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006029 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7198.588475 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12813.682514 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8770.641255 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8770.641255 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1073285 # number of writebacks +system.cpu.dcache.writebacks::total 1073285 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 449185 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 449185 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1116316 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1116316 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 75 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 75 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1565501 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1565501 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1565501 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1565501 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 868378 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 868378 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 340619 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 340619 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1208997 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1208997 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1208997 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1208997 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6242009000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6242009000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4355675500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4355675500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597684500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10597684500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597684500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10597684500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006095 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006280 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006146 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006146 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7188.124296 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12787.529468 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8765.683041 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8765.683041 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 218982 # number of replacements -system.cpu.l2cache.tagsinuse 21063.326998 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1568375 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 239342 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.552862 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 204310095000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 13543.446906 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 176.680615 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 7343.199477 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.413313 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.005392 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.224097 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.642802 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 11134 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 749402 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 760536 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1079424 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1079424 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 96 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 96 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 232415 # 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number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 108423 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3590 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 234562 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 238152 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3590 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 234562 # number of overall misses -system.cpu.l2cache.overall_misses::total 238152 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 123146500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4314165500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4437312000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 171500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 171500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3713377000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3713377000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 123146500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8027542500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8150689000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 123146500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8027542500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8150689000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 14724 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 875541 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 890265 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1079424 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1079424 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 131 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 131 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 340838 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 340838 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 14724 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1216379 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1231103 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 14724 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1216379 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1231103 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.243820 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.144070 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.267176 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.318107 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.243820 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.192836 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.243820 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.192836 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34302.646240 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34201.678307 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4900 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34248.978538 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34302.646240 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34223.542176 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34302.646240 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34223.542176 # average overall miss latency +system.cpu.l2cache.replacements 218559 # number of replacements +system.cpu.l2cache.tagsinuse 20991.845074 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1557585 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 238962 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.518128 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 174271912000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 13517.987906 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 194.270119 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 7279.587049 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.412536 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.005929 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.222155 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.640620 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 13657 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 742223 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 755880 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1073287 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1073287 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 101 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 101 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 232585 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 232585 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 13657 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 974808 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 988465 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 13657 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 974808 # number of overall hits +system.cpu.l2cache.overall_hits::total 988465 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3799 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 125573 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 129372 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 34 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 34 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 108459 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 108459 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3799 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 234032 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 237831 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3799 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 234032 # number of overall misses +system.cpu.l2cache.overall_misses::total 237831 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 130242500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4294239000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 4424481500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 240000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 240000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3713831000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3713831000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 130242500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8008070000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8138312500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 130242500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8008070000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8138312500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 17456 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 867796 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 885252 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1073287 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1073287 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 135 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 135 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 341044 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 341044 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 17456 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1208840 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1226296 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 17456 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1208840 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1226296 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.217633 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.144703 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.251852 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.318021 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.217633 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.193600 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.217633 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.193600 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34283.364043 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34197.152254 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7058.823529 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34241.796439 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34283.364043 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34217.842005 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34283.364043 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34217.842005 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -609,59 +609,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 171245 # number of writebacks -system.cpu.l2cache.writebacks::total 171245 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 19 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3587 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 126120 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 129707 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 108423 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 108423 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3587 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 234543 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 238130 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3587 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 234543 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 238130 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111526500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3915831000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4027357500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1085000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1085000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3362010000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3362010000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111526500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7277841000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7389367500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111526500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7277841000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7389367500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.144048 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.267176 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.318107 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.192821 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.192821 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31091.859493 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31048.453853 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.273152 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31091.859493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31029.879382 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31091.859493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31029.879382 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 171157 # number of writebacks +system.cpu.l2cache.writebacks::total 171157 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3794 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 125550 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 129344 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 34 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 108459 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 108459 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3794 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 234009 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 237803 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3794 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 234009 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 237803 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117923000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3896803000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4014726000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1054500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1054500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3363156000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3363156000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117923000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7259959000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7377882000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117923000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7259959000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7377882000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.217346 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.144677 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.251852 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.318021 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.217346 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193581 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.217346 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193581 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31081.444386 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31037.857427 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31014.705882 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.547009 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31081.444386 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31024.272571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31081.444386 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31024.272571 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index a99eb01f1..447926c85 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,15 +1,28 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:22:59 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:44:57 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ***********************info: Increasing stack size by one page. -************************** +***************info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +*********** 58924 words stored in 3784810 bytes @@ -21,10 +34,8 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success -info: Increasing stack size by one page. * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -69,4 +80,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 488026375000 because target called exit() +Exiting @ tick 460107924500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index e2e62743e..2a0c6a8f9 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,267 +1,265 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.488026 # Number of seconds simulated -sim_ticks 488026375000 # Number of ticks simulated -final_tick 488026375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.460108 # Number of seconds simulated +sim_ticks 460107924500 # Number of ticks simulated +final_tick 460107924500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101458 # Simulator instruction rate (inst/s) -host_op_rate 187607 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59880945 # Simulator tick rate (ticks/s) -host_mem_usage 257144 # Number of bytes of host memory used -host_seconds 8149.94 # Real time elapsed on the host +host_inst_rate 106471 # Simulator instruction rate (inst/s) +host_op_rate 196876 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59244607 # Simulator tick rate (ticks/s) +host_mem_usage 257468 # Number of bytes of host memory used +host_seconds 7766.24 # Real time elapsed on the host sim_insts 826877144 # Number of instructions simulated sim_ops 1528988756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 37539712 # Number of bytes read from this memory -system.physmem.bytes_inst_read 347136 # Number of instructions bytes read from this memory -system.physmem.bytes_written 26338560 # Number of bytes written to this memory -system.physmem.num_reads 586558 # Number of read requests responded to by this memory -system.physmem.num_writes 411540 # Number of write requests responded to by this memory +system.physmem.bytes_read 37486912 # Number of bytes read from this memory +system.physmem.bytes_inst_read 378624 # Number of instructions bytes read from this memory +system.physmem.bytes_written 26317760 # Number of bytes written to this memory +system.physmem.num_reads 585733 # Number of read requests responded to by this memory +system.physmem.num_writes 411215 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 76921482 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 711306 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 53969542 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 130891024 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 81474172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 822903 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 57199102 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 138673273 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 976052751 # number of cpu cycles simulated +system.cpu.numCycles 920215850 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 244909233 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 244909233 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16551670 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 235577670 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 217623896 # Number of BTB hits +system.cpu.BPredUnit.lookups 225637815 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 225637815 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 14289291 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 160516526 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 155855542 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 203635164 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1335786629 # Number of instructions fetch has processed -system.cpu.fetch.Branches 244909233 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 217623896 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 434745893 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 118311552 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 217882141 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 29891 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 232496 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 193900404 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4295951 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 958022628 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.604337 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.317097 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 191547382 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1262992642 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225637815 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155855542 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 392021264 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 98465808 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 234027765 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 26184 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 270251 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 183405801 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3663632 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 901816172 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.595997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.389419 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 527271952 55.04% 55.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32005205 3.34% 58.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38652146 4.03% 62.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32799855 3.42% 65.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21637734 2.26% 68.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 36320351 3.79% 71.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 49291435 5.15% 77.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 36948107 3.86% 80.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183095843 19.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 514254997 57.02% 57.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25968939 2.88% 59.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 29098594 3.23% 63.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 30321386 3.36% 66.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 19622378 2.18% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25616419 2.84% 71.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 32613002 3.62% 75.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30831455 3.42% 78.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 193489002 21.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 958022628 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.250918 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.368560 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 263275556 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 173167084 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 371540300 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 48542645 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 101497043 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2434504159 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 101497043 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 300930740 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38821666 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14830 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 381234584 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 135523765 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2382098494 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2610 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 23187923 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 93850518 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 43 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2215803805 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5602953970 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5602704256 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 249714 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 901816172 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.245201 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.372496 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 252794809 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 186036258 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 330006285 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49055494 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 83923326 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2290111824 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 83923326 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 289463344 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 42750657 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14592 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 340217218 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 145447035 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2240140505 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3227 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 23735126 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 104491412 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2078098051 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5261736827 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5260872310 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 864517 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 788504778 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1440 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1415 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 315035024 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 575221657 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 225407627 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 224840659 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 66447324 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2274732306 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12754 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1918512611 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1302000 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 743201845 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1165991477 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12201 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 958022628 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.002575 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.809760 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 650799024 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1282 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1271 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 348171673 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 540080847 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 217272434 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 215393524 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 63213343 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2142982647 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 62293 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1846789239 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1603792 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 612307626 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 971971651 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 61740 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 901816172 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.047856 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.805282 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 277706841 28.99% 28.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 160285139 16.73% 45.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161386173 16.85% 62.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 150309706 15.69% 78.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 108022954 11.28% 89.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60994203 6.37% 95.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 28856033 3.01% 98.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9365653 0.98% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1095926 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 246447632 27.33% 27.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 157137359 17.42% 44.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 150782303 16.72% 61.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 147402025 16.35% 77.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 103278327 11.45% 89.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58944184 6.54% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 27765839 3.08% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9016087 1.00% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1042416 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 958022628 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 901816172 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2261253 14.71% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 10108961 65.75% 80.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3003496 19.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2649753 16.80% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9923154 62.91% 79.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3201078 20.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2434143 0.13% 0.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1271908482 66.30% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 462991606 24.13% 90.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 181178380 9.44% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2725633 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1219452054 66.03% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 447143707 24.21% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 177467845 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1918512611 # Type of FU issued -system.cpu.iq.rate 1.965583 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15373710 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008013 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4811718392 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3018136915 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1871298739 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5168 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82228 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 119 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1931450456 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1722 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 171083363 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1846789239 # Type of FU issued +system.cpu.iq.rate 2.006909 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15773985 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008541 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4612764501 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2755319104 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1806286815 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 7926 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 295108 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 254 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1859834785 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2806 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 168142861 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 191119497 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 436651 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 282394 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 76247769 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 155978687 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 426493 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 273307 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 68112538 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6215 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 6604 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 101497043 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7669372 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1230820 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2274745060 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1222472 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 575221657 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 225407954 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6105 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 878634 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17249 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 282394 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15676996 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2334571 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18011567 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1885150488 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 454035777 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 33362123 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 83923326 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7067341 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1165909 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2143044940 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2779083 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 540080847 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 217272723 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5880 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 921481 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15876 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 273307 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10083404 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5246002 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 15329406 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1818781271 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 438673892 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 28007968 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 627868559 # number of memory reference insts executed -system.cpu.iew.exec_branches 176458351 # Number of branches executed -system.cpu.iew.exec_stores 173832782 # Number of stores executed -system.cpu.iew.exec_rate 1.931402 # Inst execution rate -system.cpu.iew.wb_sent 1879040223 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1871298858 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1436941600 # num instructions producing a value -system.cpu.iew.wb_consumers 2126368380 # num instructions consuming a value +system.cpu.iew.exec_refs 610552632 # number of memory reference insts executed +system.cpu.iew.exec_branches 170822936 # Number of branches executed +system.cpu.iew.exec_stores 171878740 # Number of stores executed +system.cpu.iew.exec_rate 1.976472 # Inst execution rate +system.cpu.iew.wb_sent 1813583044 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1806287069 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1379599827 # num instructions producing a value +system.cpu.iew.wb_consumers 2050187147 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.917211 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675773 # average fanout of values written-back +system.cpu.iew.wb_rate 1.962895 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.672914 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 745779287 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 614080092 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16577287 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 856525585 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.785106 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.285139 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14315856 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 817892846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.869424 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.327438 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 331592690 38.71% 38.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 211839945 24.73% 63.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 76804588 8.97% 72.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92775414 10.83% 83.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 33678704 3.93% 87.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28505123 3.33% 90.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15688691 1.83% 92.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11282624 1.32% 93.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 54357806 6.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 301647537 36.88% 36.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 204220955 24.97% 61.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73668560 9.01% 70.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 95020529 11.62% 82.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30882746 3.78% 86.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28791442 3.52% 89.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16321974 2.00% 91.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11763768 1.44% 93.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 55575335 6.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 856525585 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 817892846 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877144 # Number of instructions committed system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -272,62 +270,63 @@ system.cpu.commit.branches 149758588 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 54357806 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 55575335 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3076935822 # The number of ROB reads -system.cpu.rob.rob_writes 4651204201 # The number of ROB writes -system.cpu.timesIdled 418807 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18030123 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2905386359 # The number of ROB reads +system.cpu.rob.rob_writes 4370176424 # The number of ROB writes +system.cpu.timesIdled 410524 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18399678 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877144 # Number of Instructions Simulated system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated -system.cpu.cpi 1.180408 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.180408 # CPI: Total CPI of All Threads -system.cpu.ipc 0.847164 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.847164 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3175693593 # number of integer regfile reads -system.cpu.int_regfile_writes 1742205758 # number of integer regfile writes -system.cpu.fp_regfile_reads 120 # number of floating regfile reads -system.cpu.misc_regfile_reads 1036377940 # number of misc regfile reads -system.cpu.icache.replacements 10111 # number of replacements -system.cpu.icache.tagsinuse 973.820201 # Cycle average of tags in use -system.cpu.icache.total_refs 193659156 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11601 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 16693.315749 # Average number of references to valid blocks. +system.cpu.cpi 1.112881 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.112881 # CPI: Total CPI of All Threads +system.cpu.ipc 0.898569 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.898569 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3086863683 # number of integer regfile reads +system.cpu.int_regfile_writes 1679046201 # number of integer regfile writes +system.cpu.fp_regfile_reads 253 # number of floating regfile reads +system.cpu.fp_regfile_writes 1 # number of floating regfile writes +system.cpu.misc_regfile_reads 1001956200 # number of misc regfile reads +system.cpu.icache.replacements 10582 # number of replacements +system.cpu.icache.tagsinuse 994.041407 # Cycle average of tags in use +system.cpu.icache.total_refs 183174422 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12099 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 15139.633193 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 973.820201 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.475498 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.475498 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 193665655 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 193665655 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 193665655 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 193665655 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 193665655 # number of overall hits -system.cpu.icache.overall_hits::total 193665655 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 234749 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 234749 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 234749 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 234749 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 234749 # number of overall misses -system.cpu.icache.overall_misses::total 234749 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1699920500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1699920500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1699920500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1699920500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1699920500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1699920500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 193900404 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 193900404 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 193900404 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 193900404 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 193900404 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 193900404 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001211 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001211 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001211 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7241.438728 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 7241.438728 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 7241.438728 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 994.041407 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.485372 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.485372 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 183181303 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 183181303 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 183181303 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 183181303 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 183181303 # number of overall hits +system.cpu.icache.overall_hits::total 183181303 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 224498 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 224498 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 224498 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 224498 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 224498 # number of overall misses +system.cpu.icache.overall_misses::total 224498 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1640944500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1640944500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1640944500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1640944500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1640944500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1640944500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 183405801 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 183405801 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 183405801 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 183405801 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 183405801 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 183405801 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001224 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001224 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001224 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7309.394738 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 7309.394738 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 7309.394738 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 268891771 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 430713271 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 430713271 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 430713271 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 430713271 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009468 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006691 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008507 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008507 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14812.321776 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20626.473382 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16396.081689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16396.081689 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 418051972 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418051972 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418051972 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418051972 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009917 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006631 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008745 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008745 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14621.249822 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20362.005500 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16174.550219 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16174.550219 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -420,126 +419,126 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # 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number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 991591 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 991591 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2754480 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2754480 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2754480 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2754480 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14966916500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 14966916500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17535799000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17535799000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32502715500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 32502715500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32502715500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 32502715500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006261 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006648 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006395 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006395 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8489.993698 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17684.508028 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11799.946088 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11799.946088 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2228961 # number of writebacks +system.cpu.dcache.writebacks::total 2228961 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 905583 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 905583 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9205 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9205 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 914788 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 914788 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 914788 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 914788 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1760957 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1760957 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 979925 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 979925 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2740882 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2740882 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2740882 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2740882 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14913752500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14913752500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17128067500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17128067500 # 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number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 208530 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 247038 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 247038 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5916 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 579854 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 585770 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5916 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 579854 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 585770 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183580000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10325106000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10508686000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6464792000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6464792000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7658792000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7658792000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183580000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17983898000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18167478000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183580000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17983898000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18167478000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.492180 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189117 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993781 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320366 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.492180 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229105 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.492180 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229105 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31031.102096 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.466420 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.735961 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.485448 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31031.102096 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.527795 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31031.102096 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.527795 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout index b600ef537..371dd4693 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:10:43 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:34:00 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second @@ -11,4 +11,4 @@ info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.133333 -Exiting @ tick 139995113500 because target called exit() +Exiting @ tick 141175129500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 58ea20ddf..6b6e927bf 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.139995 # Number of seconds simulated -sim_ticks 139995113500 # Number of ticks simulated -final_tick 139995113500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.141175 # Number of seconds simulated +sim_ticks 141175129500 # Number of ticks simulated +final_tick 141175129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 154307 # Simulator instruction rate (inst/s) -host_op_rate 154307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54186341 # Simulator tick rate (ticks/s) -host_mem_usage 215920 # Number of bytes of host memory used -host_seconds 2583.59 # Real time elapsed on the host +host_inst_rate 157275 # Simulator instruction rate (inst/s) +host_op_rate 157275 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55694402 # Simulator tick rate (ticks/s) +host_mem_usage 215928 # Number of bytes of host memory used +host_seconds 2534.82 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 469184 # Number of bytes read from this memory -system.physmem.bytes_inst_read 214784 # Number of instructions bytes read from this memory +system.physmem.bytes_read 468992 # Number of bytes read from this memory +system.physmem.bytes_inst_read 214592 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 7331 # Number of read requests responded to by this memory +system.physmem.num_reads 7328 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3351431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1534225 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 3351431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 3322058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1520041 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 3322058 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -36,10 +36,10 @@ system.cpu.dtb.data_hits 168277058 # DT system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 168277114 # DTB accesses -system.cpu.itb.fetch_hits 48859849 # ITB hits -system.cpu.itb.fetch_misses 44521 # ITB misses +system.cpu.itb.fetch_hits 49111850 # ITB hits +system.cpu.itb.fetch_misses 88782 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48904370 # ITB accesses +system.cpu.itb.fetch_accesses 49200632 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,16 +53,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 279990228 # number of cpu cycles simulated +system.cpu.numCycles 282350260 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 279561038 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 281921224 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 6809 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13513618 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266476610 # Number of cycles cpu stages are processed. -system.cpu.activity 95.173539 # Percentage of cycles cpu is active +system.cpu.timesIdled 6799 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13475974 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 268874286 # Number of cycles cpu stages are processed. +system.cpu.activity 95.227214 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -74,92 +74,92 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.702320 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.708240 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.702320 # CPI: Total CPI of All Threads -system.cpu.ipc 1.423852 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.708240 # CPI: Total CPI of All Threads +system.cpu.ipc 1.411951 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.423852 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 53456377 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 30648707 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 15206922 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 35068414 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 15659516 # Number of BTB hits +system.cpu.ipc_total 1.411951 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 53870351 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 30921654 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 33426940 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 15653987 # Number of BTB hits system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 20 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 44.654189 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 29689183 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 23767194 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280275252 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 18 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 46.830452 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 29683846 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 24186505 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280818442 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 439611111 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119572386 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 440154301 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119907697 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 219768867 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100597400 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 168369236 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 14604498 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 601765 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 15206263 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 29381288 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 34.104279 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 205417549 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 2124324 # Number of Multipy Operations Executed +system.cpu.regfile_manager.floatRegFileAccesses 220104178 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100457644 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 168700458 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 14475221 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 1561329 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 16036550 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 28551001 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.966429 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 205750873 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 78021134 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 201969094 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.134337 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107567321 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 172422907 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.581759 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 102759298 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177230930 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.298970 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 181219893 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98770335 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.276351 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90498113 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189492115 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.678117 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 1970 # number of replacements -system.cpu.icache.tagsinuse 1829.847469 # Cycle average of tags in use -system.cpu.icache.total_refs 48855472 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3897 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12536.687708 # Average number of references to valid blocks. +system.cpu.stage0.idleCycles 78536322 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 203813938 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.184788 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 108863639 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 173486621 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.443762 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 104640873 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177709387 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.939339 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 183568799 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98781461 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 34.985433 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 92657665 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189692595 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.183432 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 1974 # number of replacements +system.cpu.icache.tagsinuse 1829.918694 # Cycle average of tags in use +system.cpu.icache.total_refs 49107469 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12588.430915 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1829.847469 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.893480 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.893480 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 48855472 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 48855472 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 48855472 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 48855472 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 48855472 # number of overall hits -system.cpu.icache.overall_hits::total 48855472 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4376 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4376 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4376 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4376 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4376 # number of overall misses -system.cpu.icache.overall_misses::total 4376 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 214318500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 214318500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 214318500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 214318500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 214318500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 214318500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 48859848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 48859848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 48859848 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 48859848 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 48859848 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 48859848 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000090 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000090 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000090 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48975.891225 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48975.891225 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48975.891225 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1829.918694 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.893515 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.893515 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 49107469 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49107469 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 49107469 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49107469 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 49107469 # number of overall hits +system.cpu.icache.overall_hits::total 49107469 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4380 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4380 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4380 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4380 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4380 # number of overall misses +system.cpu.icache.overall_misses::total 4380 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 214309000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 214309000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 214309000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 214309000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 214309000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 214309000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 49111849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 49111849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 49111849 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 49111849 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 49111849 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 49111849 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48928.995434 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48928.995434 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48928.995434 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -174,34 +174,34 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 479 system.cpu.icache.demand_mshr_hits::total 479 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 479 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 479 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3897 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 3897 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 3897 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 3897 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 3897 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 3897 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185285000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 185285000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185285000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 185285000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185285000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 185285000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47545.547857 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47545.547857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47545.547857 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3901 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3901 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 3901 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3901 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 3901 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3901 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185222000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 185222000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185222000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 185222000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185222000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 185222000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47480.645988 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47480.645988 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47480.645988 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3284.892021 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3284.843893 # Cycle average of tags in use system.cpu.dcache.total_refs 168261959 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40525.519990 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3284.892021 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.801976 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.801976 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 3284.843893 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.801964 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.801964 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753265 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753265 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73508694 # number of WriteReq hits @@ -218,14 +218,14 @@ system.cpu.dcache.demand_misses::cpu.data 13259 # n system.cpu.dcache.demand_misses::total 13259 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 13259 # number of overall misses system.cpu.dcache.overall_misses::total 13259 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63830500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63830500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 626731500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 626731500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 690562000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 690562000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 690562000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 690562000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63819000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63819000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 626556000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 626556000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 690375000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 690375000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 690375000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 690375000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -238,16 +238,16 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000164 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000079 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000079 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52149.101307 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52075.737432 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52082.509993 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52082.509993 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52139.705882 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52061.154965 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 82468500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 82410500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1848 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # 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Cycle average of tags in use +system.cpu.l2cache.total_refs 736 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.156031 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.532609 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2905.642885 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 623.829454 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.088673 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019038 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.119019 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 541 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 370.518693 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2902.345937 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 623.820537 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011307 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.088573 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019037 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.118917 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 548 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 117 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 658 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 665 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 541 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 548 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 177 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 718 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 541 # number of overall hits +system.cpu.l2cache.demand_hits::total 725 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 548 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 177 # number of overall hits -system.cpu.l2cache.overall_hits::total 718 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3356 # number of ReadReq misses +system.cpu.l2cache.overall_hits::total 725 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3353 # 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number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 3897 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8049 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 3897 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8053 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8049 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.861175 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 8053 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859523 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876452 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.861175 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859523 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.861175 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.682956 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52563.855422 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52453.418124 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.682956 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.477987 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.682956 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.477987 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52322.696093 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52557.228916 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52454.848967 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.226415 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.226415 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -368,42 +368,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3356 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3353 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 830 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4186 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4183 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3145 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3145 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3356 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3353 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 3975 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7331 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3356 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7328 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3975 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7331 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134709500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33517000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 168226500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126764000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126764000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134709500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160281000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 294990500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134709500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160281000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 294990500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134591000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33517500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 168108500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126757500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126757500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134591000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160275000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 294866000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134591000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160275000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 294866000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876452 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40139.898689 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40381.927711 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40306.518283 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40139.898689 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40322.264151 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40139.898689 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40322.264151 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.471220 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40382.530120 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40304.451510 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index d3938f090..39c5315c7 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:10:45 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:34:05 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -10,5 +10,5 @@ info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. -OO-style eon Time= 0.083333 -Exiting @ tick 89480174500 because target called exit() +OO-style eon Time= 0.066667 +Exiting @ tick 80257421500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index e5ff3033e..54f4ab1b0 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.089480 # Number of seconds simulated -sim_ticks 89480174500 # Number of ticks simulated -final_tick 89480174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.080257 # Number of seconds simulated +sim_ticks 80257421500 # Number of ticks simulated +final_tick 80257421500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 246728 # Simulator instruction rate (inst/s) -host_op_rate 246728 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58782597 # Simulator tick rate (ticks/s) -host_mem_usage 216860 # Number of bytes of host memory used -host_seconds 1522.22 # Real time elapsed on the host -sim_insts 375574794 # Number of instructions simulated -sim_ops 375574794 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 475840 # Number of bytes read from this memory -system.physmem.bytes_inst_read 219968 # Number of instructions bytes read from this memory +host_inst_rate 261701 # Simulator instruction rate (inst/s) +host_op_rate 261701 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55923550 # Simulator tick rate (ticks/s) +host_mem_usage 217092 # Number of bytes of host memory used +host_seconds 1435.13 # Real time elapsed on the host +sim_insts 375574808 # Number of instructions simulated +sim_ops 375574808 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 478528 # Number of bytes read from this memory +system.physmem.bytes_inst_read 222720 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 7435 # Number of read requests responded to by this memory +system.physmem.num_reads 7477 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 5317826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2458288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 5317826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 5962414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 2775070 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 5962414 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 105444914 # DTB read hits -system.cpu.dtb.read_misses 94699 # DTB read misses -system.cpu.dtb.read_acv 48617 # DTB read access violations -system.cpu.dtb.read_accesses 105539613 # DTB read accesses -system.cpu.dtb.write_hits 79763652 # DTB write hits -system.cpu.dtb.write_misses 1536 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 79765188 # DTB write accesses -system.cpu.dtb.data_hits 185208566 # DTB hits -system.cpu.dtb.data_misses 96235 # DTB misses -system.cpu.dtb.data_acv 48618 # DTB access violations -system.cpu.dtb.data_accesses 185304801 # DTB accesses -system.cpu.itb.fetch_hits 57904086 # ITB hits -system.cpu.itb.fetch_misses 346 # ITB misses +system.cpu.dtb.read_hits 103368572 # DTB read hits +system.cpu.dtb.read_misses 88956 # DTB read misses +system.cpu.dtb.read_acv 48603 # DTB read access violations +system.cpu.dtb.read_accesses 103457528 # DTB read accesses +system.cpu.dtb.write_hits 78975243 # DTB write hits +system.cpu.dtb.write_misses 1664 # DTB write misses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_accesses 78976907 # DTB write accesses +system.cpu.dtb.data_hits 182343815 # DTB hits +system.cpu.dtb.data_misses 90620 # DTB misses +system.cpu.dtb.data_acv 48606 # DTB access violations +system.cpu.dtb.data_accesses 182434435 # DTB accesses +system.cpu.itb.fetch_hits 52487109 # ITB hits +system.cpu.itb.fetch_misses 461 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 57904432 # ITB accesses +system.cpu.itb.fetch_accesses 52487570 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,315 +53,315 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 178960351 # number of cpu cycles simulated +system.cpu.numCycles 160514845 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 56765606 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 33143039 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3552012 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 40427205 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 32022628 # Number of BTB hits +system.cpu.BPredUnit.lookups 52017212 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 30261257 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1593315 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 28494887 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 24272738 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 10686505 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1330 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 59866357 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 502938652 # Number of instructions fetch has processed -system.cpu.fetch.Branches 56765606 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42709133 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 93526616 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12701088 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 16326839 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7643 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 57904086 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1110763 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 178838548 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.812250 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.245901 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 9355488 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 4145 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 53524792 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 462212886 # Number of instructions fetch has processed +system.cpu.fetch.Branches 52017212 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33628226 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 81457148 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7754706 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19283001 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 185 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7777 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 52487109 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 628108 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 160395311 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.881711 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.314748 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 85311932 47.70% 47.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8035871 4.49% 52.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9868460 5.52% 57.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6372149 3.56% 61.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13508487 7.55% 68.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9517347 5.32% 74.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5905302 3.30% 77.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3555081 1.99% 79.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36763919 20.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 78938163 49.21% 49.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4375676 2.73% 51.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7263628 4.53% 56.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5613511 3.50% 59.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12408314 7.74% 67.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8080182 5.04% 72.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5692573 3.55% 76.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1906295 1.19% 77.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36116969 22.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 178838548 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317197 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.810336 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 65738845 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12641259 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 87702735 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3649079 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9106630 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 10252982 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4580 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 491283130 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12139 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9106630 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 70077435 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4396073 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 392991 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 87026850 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 7838569 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 478183111 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 34338 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 6474620 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 310467420 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 626927534 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 331115388 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 295812146 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 50935101 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38371 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 296 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21811876 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 110641644 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 85552281 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8662202 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5906832 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 433013718 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 258 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 418626838 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2003473 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 56038444 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 32198216 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 178838548 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.340809 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.008173 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 160395311 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324065 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.879565 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 59060129 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 14738019 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76660368 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3818816 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6117979 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9735972 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4512 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 456714619 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12671 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6117979 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 62341788 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4786215 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 392111 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 77312738 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9444480 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 451064099 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26210 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7820126 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 294805500 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 593185508 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 313931497 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 279254011 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 35273171 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38670 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 424 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27284397 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106956708 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81779793 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8927292 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6395845 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 416292628 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 359 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 407676624 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1078526 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 40464590 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 19834312 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 144 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 160395311 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.541699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.006909 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 44336411 24.79% 24.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 29007268 16.22% 41.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 27775406 15.53% 56.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 26238037 14.67% 71.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 22251353 12.44% 83.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15664112 8.76% 92.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8263195 4.62% 97.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3972623 2.22% 99.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1330143 0.74% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 31984575 19.94% 19.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 26488225 16.51% 36.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 26058764 16.25% 52.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24758572 15.44% 68.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21531957 13.42% 81.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15472386 9.65% 91.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8703569 5.43% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4094121 2.55% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1303142 0.81% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 178838548 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 160395311 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 135690 1.14% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 41926 0.35% 1.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 2442 0.02% 1.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 8992 0.08% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1877041 15.76% 17.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1762283 14.79% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5120089 42.98% 75.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2964035 24.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35479 0.30% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 74583 0.63% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5020 0.04% 0.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3238 0.03% 1.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1852472 15.62% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1780365 15.01% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5090382 42.92% 74.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3018331 25.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 164031789 39.18% 39.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126165 0.51% 39.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33716465 8.05% 47.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7893369 1.89% 49.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2899949 0.69% 50.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16711518 3.99% 54.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1573138 0.38% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 108174365 25.84% 80.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 81466499 19.46% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 157965890 38.75% 38.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126519 0.52% 39.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33457651 8.21% 47.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7841942 1.92% 49.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2840834 0.70% 50.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16563363 4.06% 54.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1591033 0.39% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105252822 25.82% 80.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 80002989 19.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 418626838 # Type of FU issued -system.cpu.iq.rate 2.339216 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11912498 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028456 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 681277012 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 289109429 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 241633599 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 348731183 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 199993522 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 164553982 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 252486483 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 178019272 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 13980098 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 407676624 # Type of FU issued +system.cpu.iq.rate 2.539806 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11859870 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029091 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 647408174 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 269506276 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237627844 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 341278781 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187302066 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 162920489 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 245219921 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 174282992 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 14797631 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 15887158 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 143607 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 50570 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12031553 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12202221 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 124163 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 50788 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8259064 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 233419 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260903 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9106630 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2382208 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 372749 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 458676643 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2278358 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 110641644 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 85552281 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 258 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 129 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 50570 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3441219 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 544657 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3985876 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 409944817 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 105588265 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 8682021 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6117979 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2500869 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 370633 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 441236152 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 174981 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106956708 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81779793 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 359 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 125 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 50788 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1245732 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 559417 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1805149 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403162552 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103506235 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4514072 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 25662667 # number of nop insts executed -system.cpu.iew.exec_refs 185353481 # number of memory reference insts executed -system.cpu.iew.exec_branches 48120403 # Number of branches executed -system.cpu.iew.exec_stores 79765216 # Number of stores executed -system.cpu.iew.exec_rate 2.290702 # Inst execution rate -system.cpu.iew.wb_sent 407421919 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 406187581 # cumulative count of insts written-back -system.cpu.iew.wb_producers 197894075 # num instructions producing a value -system.cpu.iew.wb_consumers 277422150 # num instructions consuming a value +system.cpu.iew.exec_nop 24943165 # number of nop insts executed +system.cpu.iew.exec_refs 182483180 # number of memory reference insts executed +system.cpu.iew.exec_branches 47188511 # Number of branches executed +system.cpu.iew.exec_stores 78976945 # Number of stores executed +system.cpu.iew.exec_rate 2.511684 # Inst execution rate +system.cpu.iew.wb_sent 401387937 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400548333 # cumulative count of insts written-back +system.cpu.iew.wb_producers 195210305 # num instructions producing a value +system.cpu.iew.wb_consumers 273275997 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.269707 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.713332 # average fanout of values written-back +system.cpu.iew.wb_rate 2.495397 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.714334 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 398664569 # The number of committed instructions -system.cpu.commit.commitCommittedOps 398664569 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 60016815 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 398664583 # The number of committed instructions +system.cpu.commit.commitCommittedOps 398664583 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 42606114 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3547729 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 169731918 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.348790 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.858024 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1588886 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 154277332 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.584078 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.967872 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 70140218 41.32% 41.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 25651558 15.11% 56.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14667534 8.64% 65.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12267165 7.23% 72.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 9098146 5.36% 77.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 6161287 3.63% 81.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5543706 3.27% 84.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3203239 1.89% 86.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22999065 13.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58795294 38.11% 38.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 23338616 15.13% 53.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13263185 8.60% 61.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11678899 7.57% 69.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8438473 5.47% 74.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5481478 3.55% 78.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5137622 3.33% 81.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3374234 2.19% 83.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 24769531 16.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 169731918 # Number of insts commited each cycle -system.cpu.commit.committedInsts 398664569 # Number of instructions committed -system.cpu.commit.committedOps 398664569 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 154277332 # Number of insts commited each cycle +system.cpu.commit.committedInsts 398664583 # Number of instructions committed +system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 168275214 # Number of memory references committed -system.cpu.commit.loads 94754486 # Number of loads committed +system.cpu.commit.refs 168275216 # Number of memory references committed +system.cpu.commit.loads 94754487 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 44587530 # Number of branches committed +system.cpu.commit.branches 44587533 # Number of branches committed system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. -system.cpu.commit.int_insts 316365825 # Number of committed integer instructions. +system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22999065 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 24769531 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 605411260 # The number of ROB reads -system.cpu.rob.rob_writes 926487800 # The number of ROB writes -system.cpu.timesIdled 2712 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 121803 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 375574794 # Number of Instructions Simulated -system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated -system.cpu.cpi 0.476497 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.476497 # CPI: Total CPI of All Threads -system.cpu.ipc 2.098648 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.098648 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 409675274 # number of integer regfile reads -system.cpu.int_regfile_writes 175727060 # number of integer regfile writes -system.cpu.fp_regfile_reads 159328411 # number of floating regfile reads -system.cpu.fp_regfile_writes 105866122 # number of floating regfile writes +system.cpu.rob.rob_reads 570775521 # The number of ROB reads +system.cpu.rob.rob_writes 888672842 # The number of ROB writes +system.cpu.timesIdled 2679 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 119534 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 375574808 # Number of Instructions Simulated +system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated +system.cpu.cpi 0.427384 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.427384 # CPI: Total CPI of All Threads +system.cpu.ipc 2.339814 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.339814 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 402674037 # number of integer regfile reads +system.cpu.int_regfile_writes 172514061 # number of integer regfile writes +system.cpu.fp_regfile_reads 158318736 # number of floating regfile reads +system.cpu.fp_regfile_writes 105208261 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2110 # number of replacements -system.cpu.icache.tagsinuse 1834.326922 # Cycle average of tags in use -system.cpu.icache.total_refs 57898804 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4037 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14342.037156 # Average number of references to valid blocks. +system.cpu.icache.replacements 2234 # number of replacements +system.cpu.icache.tagsinuse 1837.389415 # Cycle average of tags in use +system.cpu.icache.total_refs 52481453 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4164 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12603.615034 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1834.326922 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.895667 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.895667 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 57898804 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 57898804 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 57898804 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 57898804 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 57898804 # number of overall hits -system.cpu.icache.overall_hits::total 57898804 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5282 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5282 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5282 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5282 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5282 # number of overall misses -system.cpu.icache.overall_misses::total 5282 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 167914000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 167914000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 167914000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 167914000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 167914000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 167914000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57904086 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57904086 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 57904086 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 57904086 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 57904086 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 57904086 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000091 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000091 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000091 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31789.852329 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 31789.852329 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31789.852329 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1837.389415 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.897163 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.897163 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 52481453 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 52481453 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 52481453 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 52481453 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 52481453 # number of overall hits +system.cpu.icache.overall_hits::total 52481453 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5656 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5656 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5656 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5656 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5656 # number of overall misses +system.cpu.icache.overall_misses::total 5656 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 175405000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 175405000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 175405000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 175405000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 175405000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 175405000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 52487109 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 52487109 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 52487109 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 52487109 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 52487109 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 52487109 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000108 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000108 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000108 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31012.199434 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31012.199434 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31012.199434 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -370,202 +370,202 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1245 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1245 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1245 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1245 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1245 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1245 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4037 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4037 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4037 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4037 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4037 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4037 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 123459000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 123459000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 123459000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 123459000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 123459000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 123459000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30581.867724 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30581.867724 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30581.867724 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1492 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1492 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1492 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1492 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1492 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1492 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4164 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4164 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4164 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4164 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4164 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4164 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125153000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 125153000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125153000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 125153000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125153000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 125153000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30055.955812 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30055.955812 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30055.955812 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 793 # number of replacements -system.cpu.dcache.tagsinuse 3296.196945 # Cycle average of tags in use -system.cpu.dcache.total_refs 164730953 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4193 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 39287.134033 # Average number of references to valid blocks. +system.cpu.dcache.replacements 804 # number of replacements +system.cpu.dcache.tagsinuse 3297.800145 # Cycle average of tags in use +system.cpu.dcache.total_refs 161809566 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4205 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38480.277289 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3296.196945 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.804736 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.804736 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 91229707 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 91229707 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501239 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501239 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 164730946 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 164730946 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 164730946 # number of overall hits -system.cpu.dcache.overall_hits::total 164730946 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1678 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1678 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19489 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19489 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21167 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21167 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21167 # number of overall misses -system.cpu.dcache.overall_misses::total 21167 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55919500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55919500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 568883000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 568883000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 624802500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 624802500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 624802500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 624802500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 91231385 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 91231385 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 73520728 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 73520728 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 164752113 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 164752113 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 164752113 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 164752113 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000018 # miss rate for ReadReq accesses +system.cpu.dcache.occ_blocks::cpu.data 3297.800145 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.805127 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.805127 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88308332 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88308332 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501218 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501218 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 16 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 16 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 161809550 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161809550 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 161809550 # number of overall hits +system.cpu.dcache.overall_hits::total 161809550 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1689 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1689 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19511 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19511 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21200 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21200 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21200 # number of overall misses +system.cpu.dcache.overall_misses::total 21200 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 56020500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 56020500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 567228500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 567228500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 623249000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 623249000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 623249000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 623249000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88310021 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88310021 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 161830750 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 161830750 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 161830750 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 161830750 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000128 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33325.089392 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29189.953307 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29517.763500 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29517.763500 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13000 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000131 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000131 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33167.850799 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29072.241300 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29398.537736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29398.537736 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2600 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 671 # number of writebacks -system.cpu.dcache.writebacks::total 671 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 680 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16294 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16294 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16974 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16974 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16974 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16974 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 998 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 998 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3195 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4193 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4193 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4193 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4193 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31703500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 31703500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 113133500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 113133500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 144837000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 144837000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 144837000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 144837000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 682 # number of writebacks +system.cpu.dcache.writebacks::total 682 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 686 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 686 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16309 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16309 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16995 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16995 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16995 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16995 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1003 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1003 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4205 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4205 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4205 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4205 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31754500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 31754500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 113124000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 113124000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 144878500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 144878500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 144878500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 144878500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31767.034068 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35409.546166 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34542.570952 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34542.570952 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31659.521436 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35329.169269 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34453.864447 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34453.864447 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 10 # number of replacements -system.cpu.l2cache.tagsinuse 4007.455925 # Cycle average of tags in use -system.cpu.l2cache.total_refs 810 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4847 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.167114 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 11 # number of replacements +system.cpu.l2cache.tagsinuse 4039.301940 # Cycle average of tags in use +system.cpu.l2cache.total_refs 903 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4887 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.184776 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 377.670641 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2971.084033 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 658.701251 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011526 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.090670 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020102 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.122298 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 600 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 130 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 730 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 671 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 671 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 65 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 65 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 600 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 195 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 795 # 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Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020226 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.123270 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 684 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 133 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 817 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 682 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 682 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 75 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 75 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 684 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 208 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 892 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 684 # 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number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4205 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8369 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.835735 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.867398 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.976577 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.835735 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.950535 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.835735 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.950535 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34383.045977 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34584.482759 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34647.105852 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34383.045977 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34633.475106 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34383.045977 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34633.475106 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -574,42 +574,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3437 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 868 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4305 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3130 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3437 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3998 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7435 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3437 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3998 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7435 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 107040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27274000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 134314000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98534000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98534000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 107040000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125808000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 232848000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 107040000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125808000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 232848000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869739 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.979656 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953494 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.953494 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31143.439046 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31421.658986 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31480.511182 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31143.439046 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31467.733867 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31143.439046 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31467.733867 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3480 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 870 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4350 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3127 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3127 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3480 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3997 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7477 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3480 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3997 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7477 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 108421000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27340000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 135761000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98470000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98470000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 108421000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125810000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 234231000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 108421000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125810000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 234231000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867398 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.976577 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.950535 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.950535 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31155.459770 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31425.287356 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31490.246242 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31155.459770 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31476.107080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31155.459770 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31476.107080 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 347d30ac0..6a43cd1d6 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:57:28 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:20:40 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -13,4 +13,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.100000 -Exiting @ tick 104492506500 because target called exit() +Exiting @ tick 106128099500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 242cca723..47e84b8b4 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.104493 # Number of seconds simulated -sim_ticks 104492506500 # Number of ticks simulated -final_tick 104492506500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.106128 # Number of seconds simulated +sim_ticks 106128099500 # Number of ticks simulated +final_tick 106128099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158423 # Simulator instruction rate (inst/s) -host_op_rate 202536 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60628822 # Simulator tick rate (ticks/s) -host_mem_usage 231676 # Number of bytes of host memory used -host_seconds 1723.48 # Real time elapsed on the host -sim_insts 273038258 # Number of instructions simulated -sim_ops 349066034 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 464000 # Number of bytes read from this memory -system.physmem.bytes_inst_read 192512 # Number of instructions bytes read from this memory +host_inst_rate 157297 # Simulator instruction rate (inst/s) +host_op_rate 201096 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61140107 # Simulator tick rate (ticks/s) +host_mem_usage 232128 # Number of bytes of host memory used +host_seconds 1735.82 # Real time elapsed on the host +sim_insts 273038358 # Number of instructions simulated +sim_ops 349066134 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 467776 # Number of bytes read from this memory +system.physmem.bytes_inst_read 196608 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 7250 # Number of read requests responded to by this memory +system.physmem.num_reads 7309 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 4440510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1842352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 4440510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 4407655 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1852554 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 4407655 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -63,105 +63,105 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 208985014 # number of cpu cycles simulated +system.cpu.numCycles 212256200 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 38314474 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21092938 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3256966 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 27298627 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 21213565 # Number of BTB hits +system.cpu.BPredUnit.lookups 38600701 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20829729 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3463171 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 24539034 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 19977747 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 7683795 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 61136 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 43642080 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 338343690 # Number of instructions fetch has processed -system.cpu.fetch.Branches 38314474 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 28897360 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78995706 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 10989579 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 78549841 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 41237520 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 904571 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 208872334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.119807 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.192773 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 7676103 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 50709 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 45583571 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349929862 # Number of instructions fetch has processed +system.cpu.fetch.Branches 38600701 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 27653850 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 79742933 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11999643 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 78327340 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 3689 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 43047745 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 991560 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 212145839 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.131606 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.210594 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130527843 62.49% 62.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 9429667 4.51% 67.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6020154 2.88% 69.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6750748 3.23% 73.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5430125 2.60% 75.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4858478 2.33% 78.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3783272 1.81% 79.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4242115 2.03% 81.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 37829932 18.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 133058921 62.72% 62.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 9120644 4.30% 67.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5867847 2.77% 69.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6815573 3.21% 73.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5485208 2.59% 75.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4655113 2.19% 77.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3623686 1.71% 79.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4201022 1.98% 81.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39317825 18.53% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 208872334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.183336 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.618985 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 51215510 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73658589 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 72565491 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3819053 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7613691 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7463255 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 71181 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 431647720 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 198442 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 7613691 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 58863443 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1188654 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 57607169 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68932187 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14667190 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 416637973 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 21102 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8032684 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 88 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 455385433 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2446563589 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1351891912 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1094671677 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384568599 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 70816834 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3986585 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4043449 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48232782 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 108804127 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93109820 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3374999 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2307513 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 394258042 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3864226 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 379117437 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1806866 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 46393196 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 143558304 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 308585 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 208872334 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.815068 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.996247 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 212145839 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.181859 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.648620 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 53244552 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73538238 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 73218017 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3725881 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8419151 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7680933 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69313 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 439362017 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 203984 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8419151 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 60748190 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1237136 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 57632287 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 69638027 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14471048 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 424701352 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 42052 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7943055 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 65 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 460812549 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2479929544 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1407452570 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1072476974 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384568759 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 76243790 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3964610 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4028744 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48494722 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 109274429 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 96208348 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3462613 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2507488 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 400084611 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3851975 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 382840510 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1563616 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 52114616 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 153570381 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 296314 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 212145839 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.804610 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.994995 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 82047947 39.28% 39.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 34785806 16.65% 55.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24508634 11.73% 67.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18508923 8.86% 76.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21724585 10.40% 86.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15318663 7.33% 94.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8418302 4.03% 98.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2689665 1.29% 99.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 869809 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 84176099 39.68% 39.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 34982222 16.49% 56.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24755932 11.67% 67.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18634598 8.78% 76.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 22073169 10.40% 87.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15324157 7.22% 94.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8735583 4.12% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2596961 1.22% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 867118 0.41% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 208872334 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 212145839 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2261 0.01% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2806 0.02% 0.02% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 5043 0.03% 0.04% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available @@ -181,197 +181,197 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.04% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 10246 0.06% 0.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 2469 0.01% 0.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 378 0.00% 0.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 64552 0.37% 0.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 790 0.00% 0.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 177361 1.02% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9662090 55.64% 57.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7440153 42.84% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 40388 0.23% 0.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 3425 0.02% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 360 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 70580 0.40% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 658 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 165111 0.94% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9772061 55.35% 56.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7595169 43.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 129612173 34.19% 34.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2147283 0.57% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 15 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6745842 1.78% 36.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8678031 2.29% 38.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3497767 0.92% 39.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1584514 0.42% 40.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21146877 5.58% 45.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7187357 1.90% 47.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7146686 1.89% 49.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103748568 27.37% 76.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 87447038 23.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 132056726 34.49% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2147658 0.56% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6773802 1.77% 36.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8676385 2.27% 39.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3409492 0.89% 39.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1588042 0.41% 40.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21173468 5.53% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7175134 1.87% 47.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7113298 1.86% 49.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175289 0.05% 49.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 104144752 27.20% 76.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88406462 23.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 379117437 # Type of FU issued -system.cpu.iq.rate 1.814089 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17365346 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.045805 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 735356252 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 310675933 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 251537712 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 250923168 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 133847541 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118277096 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 267613476 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128869307 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7295740 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 382840510 # Type of FU issued +system.cpu.iq.rate 1.803672 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17655604 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.046117 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 748490100 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 326330004 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 254739452 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 248555979 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 129729375 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118008670 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 272729101 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 127767013 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7377796 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14155127 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 112471 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 8340 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10733989 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14625409 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 156782 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 8434 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 13832497 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 274 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 161 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7613691 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 19337 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 437 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 398169516 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2638152 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 108804127 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93109820 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3853005 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 205 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 8340 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3192687 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 308539 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3501226 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 373035381 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 102118243 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6082056 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8419151 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18839 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 495 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 403985333 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2312327 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 109274429 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 96208348 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3840849 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 111 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 202 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 8434 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3230502 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 526451 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3756953 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 375755558 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 102316904 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7084952 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 47248 # number of nop insts executed -system.cpu.iew.exec_refs 188073317 # number of memory reference insts executed -system.cpu.iew.exec_branches 32214551 # Number of branches executed -system.cpu.iew.exec_stores 85955074 # Number of stores executed -system.cpu.iew.exec_rate 1.784986 # Inst execution rate -system.cpu.iew.wb_sent 370819014 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 369814808 # cumulative count of insts written-back -system.cpu.iew.wb_producers 175635069 # num instructions producing a value -system.cpu.iew.wb_consumers 345639533 # num instructions consuming a value +system.cpu.iew.exec_nop 48747 # number of nop insts executed +system.cpu.iew.exec_refs 188828362 # number of memory reference insts executed +system.cpu.iew.exec_branches 32585670 # Number of branches executed +system.cpu.iew.exec_stores 86511458 # Number of stores executed +system.cpu.iew.exec_rate 1.770292 # Inst execution rate +system.cpu.iew.wb_sent 373866507 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 372748122 # cumulative count of insts written-back +system.cpu.iew.wb_producers 177468543 # num instructions producing a value +system.cpu.iew.wb_consumers 349211993 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.769576 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.508145 # average fanout of values written-back +system.cpu.iew.wb_rate 1.756124 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.508197 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 273038870 # The number of committed instructions -system.cpu.commit.commitCommittedOps 349066646 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 49103053 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3555641 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3227876 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 201258644 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.734418 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.321139 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 273038970 # The number of committed instructions +system.cpu.commit.commitCommittedOps 349066746 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 54918764 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3555661 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 3435880 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 203726689 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.713407 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.315617 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 89876372 44.66% 44.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 39560210 19.66% 64.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 17969648 8.93% 73.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13168483 6.54% 79.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14551255 7.23% 87.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7589820 3.77% 90.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3505620 1.74% 92.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3424037 1.70% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11613199 5.77% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 92152533 45.23% 45.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 39786932 19.53% 64.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 18046593 8.86% 73.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13175994 6.47% 80.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14586259 7.16% 87.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7495826 3.68% 90.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3332635 1.64% 92.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3360666 1.65% 94.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11789251 5.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 201258644 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273038870 # Number of instructions committed -system.cpu.commit.committedOps 349066646 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 203726689 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273038970 # Number of instructions committed +system.cpu.commit.committedOps 349066746 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177024831 # Number of memory references committed -system.cpu.commit.loads 94649000 # Number of loads committed +system.cpu.commit.refs 177024871 # Number of memory references committed +system.cpu.commit.loads 94649020 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30521879 # Number of branches committed +system.cpu.commit.branches 30521899 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279585929 # Number of committed integer instructions. +system.cpu.commit.int_insts 279586009 # Number of committed integer instructions. system.cpu.commit.function_calls 6225114 # Number of function calls committed. -system.cpu.commit.bw_lim_events 11613199 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 11789251 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 587812621 # The number of ROB reads -system.cpu.rob.rob_writes 803956224 # The number of ROB writes -system.cpu.timesIdled 2582 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 112680 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273038258 # Number of Instructions Simulated -system.cpu.committedOps 349066034 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 273038258 # Number of Instructions Simulated -system.cpu.cpi 0.765406 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.765406 # CPI: Total CPI of All Threads -system.cpu.ipc 1.306497 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.306497 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1781918480 # number of integer regfile reads -system.cpu.int_regfile_writes 235832393 # number of integer regfile writes -system.cpu.fp_regfile_reads 188783884 # number of floating regfile reads -system.cpu.fp_regfile_writes 133870920 # number of floating regfile writes -system.cpu.misc_regfile_reads 1003409978 # number of misc regfile reads -system.cpu.misc_regfile_writes 34422193 # number of misc regfile writes -system.cpu.icache.replacements 14108 # number of replacements -system.cpu.icache.tagsinuse 1842.733120 # Cycle average of tags in use -system.cpu.icache.total_refs 41220872 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15988 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2578.238179 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 595920425 # The number of ROB reads +system.cpu.rob.rob_writes 816392505 # The number of ROB writes +system.cpu.timesIdled 2445 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 110361 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273038358 # Number of Instructions Simulated +system.cpu.committedOps 349066134 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 273038358 # Number of Instructions Simulated +system.cpu.cpi 0.777386 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.777386 # CPI: Total CPI of All Threads +system.cpu.ipc 1.286362 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.286362 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1793972904 # number of integer regfile reads +system.cpu.int_regfile_writes 239970573 # number of integer regfile writes +system.cpu.fp_regfile_reads 188856116 # number of floating regfile reads +system.cpu.fp_regfile_writes 132824047 # number of floating regfile writes +system.cpu.misc_regfile_reads 1016778379 # number of misc regfile reads +system.cpu.misc_regfile_writes 34422233 # number of misc regfile writes +system.cpu.icache.replacements 14013 # number of replacements +system.cpu.icache.tagsinuse 1856.982815 # Cycle average of tags in use +system.cpu.icache.total_refs 43030970 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15905 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2705.499528 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1842.733120 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.899772 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.899772 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 41220872 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41220872 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 41220872 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41220872 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 41220872 # number of overall hits -system.cpu.icache.overall_hits::total 41220872 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 16648 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 16648 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 16648 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 16648 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 16648 # number of overall misses -system.cpu.icache.overall_misses::total 16648 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 201025000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 201025000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 201025000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 201025000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 201025000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 201025000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 41237520 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41237520 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 41237520 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41237520 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 41237520 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41237520 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000404 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000404 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000404 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12075.024027 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12075.024027 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12075.024027 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1856.982815 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.906730 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.906730 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 43030972 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 43030972 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 43030972 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 43030972 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 43030972 # number of overall hits +system.cpu.icache.overall_hits::total 43030972 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 16773 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 16773 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 16773 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 16773 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 16773 # number of overall misses +system.cpu.icache.overall_misses::total 16773 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 207159500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 207159500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 207159500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 207159500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 207159500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 207159500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 43047745 # 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number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1633 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16622 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16622 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1039 # number of writebacks +system.cpu.dcache.writebacks::total 1039 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1604 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1604 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16269 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16269 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 18255 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 18255 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132767000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 226240500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.188141 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.809605 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3072 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1417 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4489 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 24 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 24 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2820 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2820 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3072 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4237 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7309 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3072 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4237 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7309 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 95429000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44339500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 139768500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 744000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 744000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 88163500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 88163500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 95429000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132503000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 227932000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 95429000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132503000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 227932000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.193135 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807868 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993322 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188141 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923378 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188141 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923378 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31074.966755 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31319.915254 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992259 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.193135 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921889 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.193135 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921889 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31064.127604 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31291.107975 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31287.331918 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31074.966755 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31298.208392 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31074.966755 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31298.208392 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31263.652482 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31064.127604 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31272.834553 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31064.127604 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31272.834553 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index af8dce3f0..df01c27da 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:12:28 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:35:37 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 643030478500 because target called exit() +Exiting @ tick 645508416000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 4c98d6289..119153a53 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.643030 # Number of seconds simulated -sim_ticks 643030478500 # Number of ticks simulated -final_tick 643030478500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.645508 # Number of seconds simulated +sim_ticks 645508416000 # Number of ticks simulated +final_tick 645508416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 198283 # Simulator instruction rate (inst/s) -host_op_rate 198283 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69939236 # Simulator tick rate (ticks/s) -host_mem_usage 217424 # Number of bytes of host memory used -host_seconds 9194.13 # Real time elapsed on the host +host_inst_rate 197220 # Simulator instruction rate (inst/s) +host_op_rate 197220 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69832178 # Simulator tick rate (ticks/s) +host_mem_usage 217536 # Number of bytes of host memory used +host_seconds 9243.71 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 94779264 # Number of bytes read from this memory -system.physmem.bytes_inst_read 185664 # Number of instructions bytes read from this memory +system.physmem.bytes_read 94795136 # Number of bytes read from this memory +system.physmem.bytes_inst_read 192384 # Number of instructions bytes read from this memory system.physmem.bytes_written 4281472 # Number of bytes written to this memory -system.physmem.num_reads 1480926 # Number of read requests responded to by this memory +system.physmem.num_reads 1481174 # Number of read requests responded to by this memory system.physmem.num_writes 66898 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 147394668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 288733 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 6658272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 154052940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 146853447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 298035 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 6632713 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 153486160 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 520282071 # DTB read hits -system.cpu.dtb.read_misses 658976 # DTB read misses +system.cpu.dtb.read_hits 526109598 # DTB read hits +system.cpu.dtb.read_misses 625347 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 520941047 # DTB read accesses -system.cpu.dtb.write_hits 283837075 # DTB write hits -system.cpu.dtb.write_misses 53680 # DTB write misses +system.cpu.dtb.read_accesses 526734945 # DTB read accesses +system.cpu.dtb.write_hits 292167921 # DTB write hits +system.cpu.dtb.write_misses 53946 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 283890755 # DTB write accesses -system.cpu.dtb.data_hits 804119146 # DTB hits -system.cpu.dtb.data_misses 712656 # DTB misses +system.cpu.dtb.write_accesses 292221867 # DTB write accesses +system.cpu.dtb.data_hits 818277519 # DTB hits +system.cpu.dtb.data_misses 679293 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 804831802 # DTB accesses -system.cpu.itb.fetch_hits 398310361 # ITB hits -system.cpu.itb.fetch_misses 225 # ITB misses +system.cpu.dtb.data_accesses 818956812 # DTB accesses +system.cpu.itb.fetch_hits 402604817 # ITB hits +system.cpu.itb.fetch_misses 847 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 398310586 # ITB accesses +system.cpu.itb.fetch_accesses 402605664 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,247 +54,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1286060958 # number of cpu cycles simulated +system.cpu.numCycles 1291016833 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 402586298 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 267183275 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 28898117 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 333702913 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 271687015 # Number of BTB hits +system.cpu.BPredUnit.lookups 393573728 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 256530657 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 27586844 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 324820294 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 261991971 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 60998120 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7269 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 415096525 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3352093116 # Number of instructions fetch has processed -system.cpu.fetch.Branches 402586298 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 332685135 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 645195661 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 165271358 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 89752324 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 146 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 4176 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 398310361 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11197226 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1285935042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.606736 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.132660 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 57786471 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 8197 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 421176645 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3321335108 # Number of instructions fetch has processed +system.cpu.fetch.Branches 393573728 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 319778442 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 638257970 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 162812665 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 96711303 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 158 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8593 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 402604817 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 9565592 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1290891849 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.572900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.136734 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 640739381 49.83% 49.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57260959 4.45% 54.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 45174683 3.51% 57.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 73956325 5.75% 63.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 134643957 10.47% 74.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 43704830 3.40% 77.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 44948525 3.50% 80.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8228368 0.64% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 237278014 18.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 652633879 50.56% 50.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 59721794 4.63% 55.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43804545 3.39% 58.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 72624877 5.63% 64.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 127484332 9.88% 74.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46855386 3.63% 77.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41599950 3.22% 80.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7021053 0.54% 81.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 239146033 18.53% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1285935042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.313038 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.606481 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 451176980 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 71498937 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 618592802 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8792068 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 135874255 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 30910962 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12070 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3252787569 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 45959 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 135874255 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 481268394 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 29024257 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 25510 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 595950971 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43791655 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3151351284 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 355 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 750555 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 36590752 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2105050619 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3698513195 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3586317765 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 112195430 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1290891849 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.304856 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.572651 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 453921580 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 79454568 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 612779431 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10011349 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 134724921 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33550717 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12520 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3227083732 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46784 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 134724921 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 483920973 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 32457268 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 25980 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 591448832 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 48313875 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3136668879 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 405 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 8064 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 42516144 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2086288186 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3648925200 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3531562512 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 117362688 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 720081549 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4177 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 82 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 124172087 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 732020123 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 345520616 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 66357929 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8901879 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2642218507 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 75 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2155449111 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17941201 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 818701684 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 780988431 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 36 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1285935042 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.676173 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.767949 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 701319116 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4353 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 267 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 142890931 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 736649308 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 360329563 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68950696 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9282518 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2642275746 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 205 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2193056773 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17946555 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 819111732 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 708893207 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 166 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1290891849 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.698869 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.804017 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 465245543 36.18% 36.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 229606292 17.86% 54.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 242969112 18.89% 72.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 129449912 10.07% 83.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 105111994 8.17% 91.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 71454382 5.56% 96.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 23774402 1.85% 98.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15398679 1.20% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2924726 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 470876253 36.48% 36.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 218068463 16.89% 53.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 252707156 19.58% 72.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 121463164 9.41% 82.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 106308054 8.24% 90.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 77452334 6.00% 96.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 21076392 1.63% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17287996 1.34% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5652037 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1285935042 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1290891849 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 19151 0.06% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 21356146 65.69% 65.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11134345 34.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1141130 3.16% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 24070571 66.71% 69.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10868345 30.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1238361266 57.45% 57.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 16703 0.00% 57.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27850917 1.29% 58.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254688 0.38% 59.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204646 0.33% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 584304865 27.11% 86.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 289453270 13.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1255545244 57.25% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 16688 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 29218260 1.33% 58.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204651 0.33% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 589185884 26.87% 86.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 303628594 13.84% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2155449111 # Type of FU issued -system.cpu.iq.rate 1.676009 # Inst issue rate -system.cpu.iq.fu_busy_cnt 32509642 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015083 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5498808910 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3382020905 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1990959088 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 148475197 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 78969876 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 72622847 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2112315501 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 75640500 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67702370 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2193056773 # Type of FU issued +system.cpu.iq.rate 1.698705 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36080046 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016452 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5576578817 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3377639693 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2021595592 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 154453179 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 83821528 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 75359015 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2150081181 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 79052886 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 67169273 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 220950097 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 171000 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 71734 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 134725720 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 225579282 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 22953 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76359 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 149534667 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4434 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4418 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 135874255 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3818188 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 203306 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3005431260 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2750522 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 732020123 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 345520616 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 75 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 131111 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4921 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 71734 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 30723187 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 903682 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 31626869 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2066254472 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 520941220 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 89194639 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 134724921 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3817892 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 203271 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3000868514 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2715875 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 736649308 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 360329563 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 205 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 131040 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4909 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76359 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 27588382 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 31906 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 27620288 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2101232365 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 526735105 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 91824408 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363212678 # number of nop insts executed -system.cpu.iew.exec_refs 804832688 # number of memory reference insts executed -system.cpu.iew.exec_branches 279771397 # Number of branches executed -system.cpu.iew.exec_stores 283891468 # Number of stores executed -system.cpu.iew.exec_rate 1.606654 # Inst execution rate -system.cpu.iew.wb_sent 2065581707 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2063581935 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1176945723 # num instructions producing a value -system.cpu.iew.wb_consumers 1742555439 # num instructions consuming a value +system.cpu.iew.exec_nop 358592563 # number of nop insts executed +system.cpu.iew.exec_refs 818957488 # number of memory reference insts executed +system.cpu.iew.exec_branches 281208298 # Number of branches executed +system.cpu.iew.exec_stores 292222383 # Number of stores executed +system.cpu.iew.exec_rate 1.627579 # Inst execution rate +system.cpu.iew.wb_sent 2099740429 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2096954607 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1185148628 # num instructions producing a value +system.cpu.iew.wb_consumers 1754528061 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.604576 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675414 # average fanout of values written-back +system.cpu.iew.wb_rate 1.624266 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675480 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions system.cpu.commit.commitCommittedOps 2008987604 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 979738658 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 975184756 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 28886163 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1150060787 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.746853 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.513737 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 27574586 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1156166928 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.737628 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.495396 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 543040951 47.22% 47.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 216685952 18.84% 66.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119778809 10.41% 76.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 61132291 5.32% 81.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 44136002 3.84% 85.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24968433 2.17% 87.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19265020 1.68% 89.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 16055764 1.40% 90.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 104997565 9.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 540094894 46.71% 46.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 227413285 19.67% 66.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119190896 10.31% 76.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 56737431 4.91% 81.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50997203 4.41% 86.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24159454 2.09% 88.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18394192 1.59% 89.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 15607584 1.35% 91.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 103571989 8.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1150060787 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1156166928 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -305,64 +305,64 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 104997565 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 103571989 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4028153074 # The number of ROB reads -system.cpu.rob.rob_writes 6113513811 # The number of ROB writes -system.cpu.timesIdled 3507 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 125916 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 4031130889 # The number of ROB reads +system.cpu.rob.rob_writes 6103072592 # The number of ROB writes +system.cpu.timesIdled 3457 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 124984 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.705447 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.705447 # CPI: Total CPI of All Threads -system.cpu.ipc 1.417540 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.417540 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2630724063 # number of integer regfile reads -system.cpu.int_regfile_writes 1493026464 # number of integer regfile writes -system.cpu.fp_regfile_reads 77824314 # number of floating regfile reads -system.cpu.fp_regfile_writes 52830391 # number of floating regfile writes +system.cpu.cpi 0.708166 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.708166 # CPI: Total CPI of All Threads +system.cpu.ipc 1.412099 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.412099 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2678294251 # number of integer regfile reads +system.cpu.int_regfile_writes 1517633044 # number of integer regfile writes +system.cpu.fp_regfile_reads 81926245 # number of floating regfile reads +system.cpu.fp_regfile_writes 54028832 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8239 # number of replacements -system.cpu.icache.tagsinuse 1650.873085 # Cycle average of tags in use -system.cpu.icache.total_refs 398299261 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9946 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 40046.175447 # Average number of references to valid blocks. +system.cpu.icache.replacements 8444 # number of replacements +system.cpu.icache.tagsinuse 1673.037469 # Cycle average of tags in use +system.cpu.icache.total_refs 402593289 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10171 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 39582.468685 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1650.873085 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.806090 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.806090 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 398299261 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 398299261 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 398299261 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 398299261 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 398299261 # number of overall hits -system.cpu.icache.overall_hits::total 398299261 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11100 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11100 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11100 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11100 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11100 # number of overall misses -system.cpu.icache.overall_misses::total 11100 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 182477500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 182477500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 182477500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 182477500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 182477500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 182477500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 398310361 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 398310361 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 398310361 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 398310361 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 398310361 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 398310361 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000028 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000028 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000028 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16439.414414 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16439.414414 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16439.414414 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1673.037469 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.816913 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.816913 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 402593289 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 402593289 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 402593289 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 402593289 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 402593289 # number of overall hits +system.cpu.icache.overall_hits::total 402593289 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11528 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11528 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11528 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11528 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11528 # number of overall misses +system.cpu.icache.overall_misses::total 11528 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 191663000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 191663000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 191663000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 191663000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 191663000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 191663000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 402604817 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 402604817 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 402604817 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 402604817 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 402604817 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 402604817 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16625.867453 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16625.867453 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16625.867453 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -371,262 +371,262 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1153 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1153 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1153 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1153 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1153 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1153 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9947 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9947 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9947 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 9947 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 9947 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 9947 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 119555000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 119555000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 119555000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 119555000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 119555000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 119555000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1356 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1356 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1356 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1356 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1356 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1356 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10172 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10172 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10172 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10172 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10172 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10172 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 123488000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 123488000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 123488000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 123488000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 123488000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 123488000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12019.201769 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12019.201769 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12019.201769 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12139.992135 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12139.992135 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12139.992135 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1527592 # number of replacements -system.cpu.dcache.tagsinuse 4095.113983 # Cycle average of tags in use -system.cpu.dcache.total_refs 660890207 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1531688 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 431.478347 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 255376000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.113983 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999784 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999784 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 450646939 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 450646939 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 210243259 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 210243259 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 660890198 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 660890198 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 660890198 # number of overall hits -system.cpu.dcache.overall_hits::total 660890198 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1928305 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1928305 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 551637 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 551637 # number of WriteReq misses +system.cpu.dcache.replacements 1528059 # number of replacements +system.cpu.dcache.tagsinuse 4095.059846 # Cycle average of tags in use +system.cpu.dcache.total_refs 667250429 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1532155 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 435.497994 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 267049000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.059846 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999770 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999770 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 457007415 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 457007415 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 210242966 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 210242966 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 48 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 48 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 667250381 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 667250381 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 667250381 # number of overall hits +system.cpu.dcache.overall_hits::total 667250381 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1928420 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1928420 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 551930 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 551930 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2479942 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2479942 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2479942 # number of overall misses -system.cpu.dcache.overall_misses::total 2479942 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 71444429000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 71444429000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20878144491 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20878144491 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 59000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 59000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92322573491 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92322573491 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92322573491 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92322573491 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 452575244 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 452575244 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2480350 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2480350 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2480350 # number of overall misses +system.cpu.dcache.overall_misses::total 2480350 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 71491683500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 71491683500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20877271991 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20877271991 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 58500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 58500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92368955491 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92368955491 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92368955491 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92368955491 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 458935835 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 458935835 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 663370140 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 663370140 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 663370140 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 663370140 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004261 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002617 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003738 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003738 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37050.377923 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37847.614448 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37227.714798 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37227.714798 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 79500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 20500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 50 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 50 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 669730731 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 669730731 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 669730731 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 669730731 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004202 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002618 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.040000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003704 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003704 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37072.672706 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37825.941679 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37240.290883 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37240.290883 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 99000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 23000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5678.571429 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6187.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 23000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107326 # number of writebacks -system.cpu.dcache.writebacks::total 107326 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 468223 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 468223 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 480032 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 480032 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 107245 # number of writebacks +system.cpu.dcache.writebacks::total 107245 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467870 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 467870 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 480326 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 480326 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 948255 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 948255 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 948255 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 948255 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460082 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460082 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71605 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71605 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 948196 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 948196 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 948196 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 948196 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460550 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460550 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71604 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71604 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531687 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531687 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531687 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531687 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49942277500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 49942277500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2493130000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2493130000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1532154 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1532154 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1532154 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1532154 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49990545000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 49990545000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2492898500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2492898500 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52435407500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 52435407500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52435407500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 52435407500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003226 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52483443500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 52483443500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52483443500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 52483443500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003182 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.090909 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002309 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002309 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34205.118274 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34817.819985 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.020000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34227.205505 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34815.073180 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34233.761532 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34233.761532 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34254.679034 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34254.679034 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480630 # number of replacements -system.cpu.l2cache.tagsinuse 31935.913288 # Cycle average of tags in use -system.cpu.l2cache.total_refs 63583 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1513317 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.042016 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480784 # number of replacements +system.cpu.l2cache.tagsinuse 31940.343129 # Cycle average of tags in use +system.cpu.l2cache.total_refs 64039 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1513473 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.042313 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3059.437870 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 43.056925 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28833.418493 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.093367 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001314 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.879926 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.974607 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7046 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 48913 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 55959 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 107326 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 107326 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4750 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4750 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7046 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 53663 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 60709 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7046 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 53663 # number of overall hits -system.cpu.l2cache.overall_hits::total 60709 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2901 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1411170 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1414071 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66855 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66855 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2901 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1478025 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1480926 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2901 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1478025 # number of overall misses -system.cpu.l2cache.overall_misses::total 1480926 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 99564500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48413945500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 48513510000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2349021500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2349021500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 99564500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 50762967000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 50862531500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 99564500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 50762967000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 50862531500 # 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number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1531688 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1541635 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.291646 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.966500 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933664 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.291646 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.964965 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.291646 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.964965 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34320.751465 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34307.663499 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 35136.063122 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.751465 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34345.134216 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.751465 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34345.134216 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::writebacks 3040.164037 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 45.228004 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28854.951088 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.092778 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001380 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.880583 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.974742 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7166 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 49233 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 56399 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 107245 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 107245 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4754 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4754 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7166 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 53987 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 61153 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7166 # 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number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 10172 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1460551 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1470723 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 107245 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 107245 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 71604 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 71604 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 10172 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1532155 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1542327 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10172 # 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average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 35134.764398 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34318.196939 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34374.532529 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34318.196939 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34374.532529 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 40500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7500 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3681.818182 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks system.cpu.l2cache.writebacks::total 66898 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2901 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1411170 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1414071 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66855 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66855 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2901 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1478025 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1480926 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2901 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1478025 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1480926 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 90197000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43747183500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43837380500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2147695000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2147695000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 90197000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45894878500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 45985075500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 90197000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45894878500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 45985075500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.291646 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.966500 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933664 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.291646 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964965 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.291646 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964965 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31091.692520 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31000.647335 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32124.672799 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31091.692520 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31051.489995 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31091.692520 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31051.489995 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3006 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1411318 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1414324 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66850 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66850 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3006 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1478168 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1481174 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3006 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1478168 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1481174 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 93472000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43751757500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43845229500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2147444000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2147444000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 93472000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45899201500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 45992673500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 93472000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45899201500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 45992673500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.295517 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.966291 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933607 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.295517 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964764 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.295517 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964764 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31095.143047 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31000.637348 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32123.320868 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31095.143047 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31051.410597 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31095.143047 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31051.410597 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 96ddf0fe4..47a0b85a1 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:06:03 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:29:25 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 708285420500 because target called exit() +Exiting @ tick 733277720500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index b8fd6e344..ed14e8975 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.708285 # Number of seconds simulated -sim_ticks 708285420500 # Number of ticks simulated -final_tick 708285420500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.733278 # Number of seconds simulated +sim_ticks 733277720500 # Number of ticks simulated +final_tick 733277720500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110657 # Simulator instruction rate (inst/s) -host_op_rate 150700 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56615274 # Simulator tick rate (ticks/s) -host_mem_usage 229476 # Number of bytes of host memory used -host_seconds 12510.50 # Real time elapsed on the host -sim_insts 1384379033 # Number of instructions simulated -sim_ops 1885333786 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 94806144 # Number of bytes read from this memory -system.physmem.bytes_inst_read 201024 # Number of instructions bytes read from this memory +host_inst_rate 105807 # Simulator instruction rate (inst/s) +host_op_rate 144094 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56043664 # Simulator tick rate (ticks/s) +host_mem_usage 229440 # Number of bytes of host memory used +host_seconds 13084.04 # Real time elapsed on the host +sim_insts 1384379038 # Number of instructions simulated +sim_ops 1885333791 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 94834048 # Number of bytes read from this memory +system.physmem.bytes_inst_read 211584 # Number of instructions bytes read from this memory system.physmem.bytes_written 4230336 # Number of bytes written to this memory -system.physmem.num_reads 1481346 # Number of read requests responded to by this memory +system.physmem.num_reads 1481782 # Number of read requests responded to by this memory system.physmem.num_writes 66099 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 133853022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 283818 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5972643 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 139825665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 129328964 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 288546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 5769078 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 135098042 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,315 +64,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1416570842 # number of cpu cycles simulated +system.cpu.numCycles 1466555442 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 502965792 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 388083906 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 32892883 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 402994214 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 282903329 # Number of BTB hits +system.cpu.BPredUnit.lookups 521605883 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 398295805 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 35472641 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 324070281 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 281628461 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 59754999 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2839304 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 410473974 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2542481038 # Number of instructions fetch has processed -system.cpu.fetch.Branches 502965792 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 342658328 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 682850611 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 204993234 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 105359667 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2118 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 34717 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 384198016 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 12176398 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1365244569 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.589439 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.160393 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 60884201 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2837075 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 442389760 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2602751444 # Number of instructions fetch has processed +system.cpu.fetch.Branches 521605883 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 342512662 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 710958340 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 222650773 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 102112433 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2045 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 27281 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 413558926 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12436668 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1437090852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.547593 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.158778 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 682433791 49.99% 49.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48186597 3.53% 53.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 108652804 7.96% 61.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 62364195 4.57% 66.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 89334703 6.54% 72.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 54302238 3.98% 76.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35506449 2.60% 79.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 34966658 2.56% 81.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 249497134 18.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 726180548 50.53% 50.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 55293209 3.85% 54.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 113089207 7.87% 62.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71780914 4.99% 67.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 85098858 5.92% 73.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 53585663 3.73% 76.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 33501630 2.33% 79.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33512244 2.33% 81.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 265048579 18.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1365244569 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.355059 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.794814 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 455297388 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 85147033 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 647142661 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 11145809 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 166511678 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 68705297 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11995 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3424572913 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 23770 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 166511678 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 496865002 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 29032521 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3717307 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 615240410 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53877651 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3297959575 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 31 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4556255 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42355939 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 3260022737 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 15624313135 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 14988978570 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 635334565 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993153599 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1266869138 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 309495 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 305230 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 155871874 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1045378245 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 527599628 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 35911477 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 45240488 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 3077735106 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 301755 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2619169948 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18682763 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1192120154 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2900187573 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 90425 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1365244569 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.918462 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.900067 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1437090852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.355667 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.774738 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 490749730 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 81942012 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 671828843 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10983114 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 181587153 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 78430944 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 14399 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3525428920 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31224 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 181587153 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 528591839 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 29769579 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3592366 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 643071064 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50478851 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3416214159 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 111 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4185905 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 40940283 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 71 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3334777668 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16188662039 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 15531956325 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 656705714 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993153607 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1341624061 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 276669 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 271964 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 142813939 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1064118913 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 569792794 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 34207890 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 39464438 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 3183095569 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 272489 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2713070131 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 26125821 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1297647909 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3029004541 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 61158 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1437090852 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.887890 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.908228 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 480555764 35.20% 35.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 182601458 13.37% 48.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 216587645 15.86% 64.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 179670065 13.16% 77.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 151134600 11.07% 88.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 89532476 6.56% 95.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 48791102 3.57% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11536059 0.84% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4835400 0.35% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 520966392 36.25% 36.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 196978260 13.71% 49.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 217896132 15.16% 65.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 179000352 12.46% 77.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 155500191 10.82% 88.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 101390463 7.06% 95.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 48751651 3.39% 98.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11023722 0.77% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5583689 0.39% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1365244569 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1437090852 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2042243 2.25% 2.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23945 0.03% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55656078 61.41% 63.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 32910645 36.31% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1973852 2.08% 2.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 23832 0.03% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 56484939 59.46% 61.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 36512276 38.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1200490200 45.83% 45.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11234425 0.43% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876478 0.26% 46.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5505051 0.21% 46.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 24362738 0.93% 47.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 896045352 34.21% 81.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 473280415 18.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1254030566 46.22% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11231291 0.41% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876617 0.25% 46.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5503438 0.20% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 51 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23339517 0.86% 48.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 904708245 33.35% 81.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 506005116 18.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2619169948 # Type of FU issued -system.cpu.iq.rate 1.848951 # Inst issue rate -system.cpu.iq.fu_busy_cnt 90632911 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.034604 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6584397091 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4170852442 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2409395411 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 128503048 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 99357739 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 57077748 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2644176123 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 65626736 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 71999032 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2713070131 # Type of FU issued +system.cpu.iq.rate 1.849961 # Inst issue rate +system.cpu.iq.fu_busy_cnt 94994899 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.035014 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6850643246 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4377903008 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2485399987 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 133708588 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 103168081 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 59868624 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2739540927 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 68524103 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 73975735 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 413989376 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 268082 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1389984 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 250602644 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 432730043 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 290479 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1327592 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 292795809 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 86 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 77 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 166511678 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16376007 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1473970 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3078105405 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 12712072 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1045378245 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 527599628 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 290278 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1470963 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 212 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1389984 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 34573717 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8788062 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 43361779 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2534356508 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 842568807 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 84813440 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 181587153 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16026457 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1578003 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3183438661 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7039132 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1064118913 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 569792794 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 261469 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1577202 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 221 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1327592 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 36771149 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9229244 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 46000393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2613620752 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 848933154 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 99449379 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 68544 # number of nop insts executed -system.cpu.iew.exec_refs 1294694969 # number of memory reference insts executed -system.cpu.iew.exec_branches 344427498 # Number of branches executed -system.cpu.iew.exec_stores 452126162 # Number of stores executed -system.cpu.iew.exec_rate 1.789079 # Inst execution rate -system.cpu.iew.wb_sent 2495474043 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2466473159 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1448284961 # num instructions producing a value -system.cpu.iew.wb_consumers 2707735412 # num instructions consuming a value +system.cpu.iew.exec_nop 70603 # number of nop insts executed +system.cpu.iew.exec_refs 1326104884 # number of memory reference insts executed +system.cpu.iew.exec_branches 359304869 # Number of branches executed +system.cpu.iew.exec_stores 477171730 # Number of stores executed +system.cpu.iew.exec_rate 1.782149 # Inst execution rate +system.cpu.iew.wb_sent 2573682929 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2545268611 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1471406784 # num instructions producing a value +system.cpu.iew.wb_consumers 2751379282 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.741158 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.534869 # average fanout of values written-back +system.cpu.iew.wb_rate 1.735542 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.534789 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1384390049 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1885344802 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 1192760864 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 211330 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 38418907 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1198732893 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.572781 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.256860 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1384390054 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1885344807 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 1298094205 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 211331 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 40996327 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1255503701 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.501664 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.213150 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 532007294 44.38% 44.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 299056293 24.95% 69.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 106726660 8.90% 78.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 77517857 6.47% 84.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 53371752 4.45% 89.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23357463 1.95% 91.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 17108647 1.43% 92.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9340003 0.78% 93.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 80246924 6.69% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 576634792 45.93% 45.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 315329042 25.12% 71.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 102673368 8.18% 79.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 78981369 6.29% 85.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 52937200 4.22% 89.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24029706 1.91% 91.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 17032250 1.36% 93.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9453700 0.75% 93.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78432274 6.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1198732893 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384390049 # Number of instructions committed -system.cpu.commit.committedOps 1885344802 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1255503701 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384390054 # Number of instructions committed +system.cpu.commit.committedOps 1885344807 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908385853 # Number of memory references committed -system.cpu.commit.loads 631388869 # Number of loads committed +system.cpu.commit.refs 908385855 # Number of memory references committed +system.cpu.commit.loads 631388870 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 291350232 # Number of branches committed +system.cpu.commit.branches 291350233 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653705623 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653705627 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 80246924 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 78432274 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4196573290 # The number of ROB reads -system.cpu.rob.rob_writes 6322749564 # The number of ROB writes -system.cpu.timesIdled 1340847 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 51326273 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384379033 # Number of Instructions Simulated -system.cpu.committedOps 1885333786 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384379033 # Number of Instructions Simulated -system.cpu.cpi 1.023254 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.023254 # CPI: Total CPI of All Threads -system.cpu.ipc 0.977275 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.977275 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12567200244 # number of integer regfile reads -system.cpu.int_regfile_writes 2359430733 # number of integer regfile writes -system.cpu.fp_regfile_reads 68800397 # number of floating regfile reads -system.cpu.fp_regfile_writes 50191784 # number of floating regfile writes -system.cpu.misc_regfile_reads 3980708505 # number of misc regfile reads -system.cpu.misc_regfile_writes 13776276 # number of misc regfile writes -system.cpu.icache.replacements 27241 # number of replacements -system.cpu.icache.tagsinuse 1638.335274 # Cycle average of tags in use -system.cpu.icache.total_refs 384162744 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 28920 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13283.635685 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 4360492094 # The number of ROB reads +system.cpu.rob.rob_writes 6548474997 # The number of ROB writes +system.cpu.timesIdled 1306597 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29464590 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384379038 # Number of Instructions Simulated +system.cpu.committedOps 1885333791 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384379038 # Number of Instructions Simulated +system.cpu.cpi 1.059360 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.059360 # CPI: Total CPI of All Threads +system.cpu.ipc 0.943966 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.943966 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12901082944 # number of integer regfile reads +system.cpu.int_regfile_writes 2417885668 # number of integer regfile writes +system.cpu.fp_regfile_reads 70910494 # number of floating regfile reads +system.cpu.fp_regfile_writes 51358984 # number of floating regfile writes +system.cpu.misc_regfile_reads 4077651963 # number of misc regfile reads +system.cpu.misc_regfile_writes 13776278 # number of misc regfile writes +system.cpu.icache.replacements 29135 # number of replacements +system.cpu.icache.tagsinuse 1664.054518 # Cycle average of tags in use +system.cpu.icache.total_refs 413522379 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 30834 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13411.246643 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1638.335274 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.799968 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.799968 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 384163979 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 384163979 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 384163979 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 384163979 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 384163979 # number of overall hits -system.cpu.icache.overall_hits::total 384163979 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34037 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34037 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34037 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34037 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34037 # number of overall misses -system.cpu.icache.overall_misses::total 34037 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 300707500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 300707500 # 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miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8834.723977 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8834.723977 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8834.723977 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1664.054518 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.812527 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.812527 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 413522385 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 413522385 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 413522385 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 413522385 # 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miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8747.256506 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8747.256506 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8747.256506 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,221 +382,221 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 775 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 775 # 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average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 817 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 817 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 817 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 817 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 817 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 817 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 35724 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 35724 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 35724 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 35724 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 35724 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 35724 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191012000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 191012000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191012000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 191012000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191012000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 191012000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5346.881648 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5346.881648 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5346.881648 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1531781 # number of replacements -system.cpu.dcache.tagsinuse 4094.791758 # Cycle average of tags in use -system.cpu.dcache.total_refs 1029515809 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1535877 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 670.311365 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 305571000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.791758 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999705 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999705 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 753356755 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 753356755 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276118556 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276118556 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15246 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15246 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11672 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11672 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1029475311 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1029475311 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1029475311 # number of overall hits -system.cpu.dcache.overall_hits::total 1029475311 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1938073 # 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number of overall misses +system.cpu.dcache.overall_misses::total 3292603 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 82130752000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 82130752000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 28580919500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 28580919500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 112500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 112500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 110711671500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 110711671500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 110711671500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 110711671500 # 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average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12928 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 12928 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11673 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11673 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1036681490 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1036681490 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1036681490 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1036681490 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003254 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002964 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000232 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003176 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003176 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33226.215337 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34823.481213 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33624.360878 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33624.360878 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 62000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 83500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # 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number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 106628 # number of writebacks +system.cpu.dcache.writebacks::total 106628 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1008030 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1008030 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743137 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 743137 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1214975 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1214975 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1214975 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1214975 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1463176 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1463176 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77044 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 77044 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1540220 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1540220 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1540220 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1540220 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50021914000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50021914000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2483063000 # 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number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # 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number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1478205 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1481346 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97624500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43873380000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43971004500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 134478000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 134478000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048597500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048597500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97624500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45921977500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46019602000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97624500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45921977500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46019602000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108606 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.965108 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999079 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908943 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108606 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962449 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108606 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962449 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31080.706781 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31069.092423 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3306 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1412396 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1415702 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4885 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4885 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66080 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66080 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3306 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1478476 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1481782 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3306 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1478476 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1481782 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 102729500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43881583500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43984313000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 151435000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 151435000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048541500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048541500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 102729500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45930125000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46032854500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 102729500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45930125000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46032854500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.107212 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964859 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999182 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908803 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.107212 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962207 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.107212 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962207 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31073.653962 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.895338 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.839866 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31080.706781 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31066.041246 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31080.706781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31066.041246 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.930690 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31073.653962 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.857680 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31073.653962 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.857680 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout index 8786d03ec..a906c40f3 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:15:15 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:38:51 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 46914279500 because target called exit() +Exiting @ tick 47232621500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 22fcb32bd..447e68abd 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.046914 # Number of seconds simulated -sim_ticks 46914279500 # Number of ticks simulated -final_tick 46914279500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.047233 # Number of seconds simulated +sim_ticks 47232621500 # Number of ticks simulated +final_tick 47232621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145791 # Simulator instruction rate (inst/s) -host_op_rate 145791 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 77424105 # Simulator tick rate (ticks/s) -host_mem_usage 218104 # Number of bytes of host memory used -host_seconds 605.94 # Real time elapsed on the host +host_inst_rate 142426 # Simulator instruction rate (inst/s) +host_op_rate 142426 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76149893 # Simulator tick rate (ticks/s) +host_mem_usage 218108 # Number of bytes of host memory used +host_seconds 620.26 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 11164096 # Number of bytes read from this memory -system.physmem.bytes_inst_read 599296 # Number of instructions bytes read from this memory -system.physmem.bytes_written 7712960 # Number of bytes written to this memory -system.physmem.num_reads 174439 # Number of read requests responded to by this memory -system.physmem.num_writes 120515 # Number of write requests responded to by this memory +system.physmem.bytes_read 11167232 # Number of bytes read from this memory +system.physmem.bytes_inst_read 602240 # Number of instructions bytes read from this memory +system.physmem.bytes_written 7713024 # Number of bytes written to this memory +system.physmem.num_reads 174488 # Number of read requests responded to by this memory +system.physmem.num_writes 120516 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 237967973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 12774277 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 164405381 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 402373354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 236430493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 12750510 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 163298664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 399729158 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277222 # DTB read hits +system.cpu.dtb.read_hits 20277221 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367370 # DTB read accesses +system.cpu.dtb.read_accesses 20367369 # DTB read accesses system.cpu.dtb.write_hits 14736811 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 14744063 # DTB write accesses -system.cpu.dtb.data_hits 35014033 # DTB hits +system.cpu.dtb.data_hits 35014032 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35111433 # DTB accesses -system.cpu.itb.fetch_hits 12380499 # ITB hits -system.cpu.itb.fetch_misses 10576 # ITB misses +system.cpu.dtb.data_accesses 35111432 # DTB accesses +system.cpu.itb.fetch_hits 12477897 # ITB hits +system.cpu.itb.fetch_misses 13095 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12391075 # ITB accesses +system.cpu.itb.fetch_accesses 12490992 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,16 +54,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 93828560 # number of cpu cycles simulated +system.cpu.numCycles 94465244 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77431415 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 78066794 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 305691 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24228941 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69599619 # Number of cycles cpu stages are processed. -system.cpu.activity 74.177435 # Percentage of cycles cpu is active +system.cpu.timesIdled 305627 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24182755 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 70282489 # Number of cycles cpu stages are processed. +system.cpu.activity 74.400368 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -75,158 +75,158 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 1.062122 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.069329 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 1.062122 # CPI: Total CPI of All Threads -system.cpu.ipc 0.941512 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.069329 # CPI: Total CPI of All Threads +system.cpu.ipc 0.935166 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.941512 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 18761151 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 12342012 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4785453 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 15763185 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 4708455 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 1660959 # Number of times the RAS was used to get a target. +system.cpu.ipc_total 0.935166 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 18828991 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12440560 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 5024685 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 16222590 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 5048183 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1660950 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 1029 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 29.869947 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 8112975 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10648176 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74148043 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 31.118231 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8476014 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10352977 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74323677 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126467293 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 65874 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126642927 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 65289 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 293504 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14179622 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35053135 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4496417 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 178536 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4674953 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 9097544 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 33.944121 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44764178 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 292919 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14127497 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35064147 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4680877 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 233308 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4914185 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 8858001 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.681953 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44775654 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 41142190 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52686370 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 56.151741 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 51376338 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42452222 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.244456 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 50789796 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43038764 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 45.869577 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 71702339 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22126221 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 23.581542 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 47784207 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46044353 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 49.072855 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 83610 # number of replacements -system.cpu.icache.tagsinuse 1886.858130 # Cycle average of tags in use -system.cpu.icache.total_refs 12263478 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 85656 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 143.171266 # Average number of references to valid blocks. +system.cpu.stage0.idleCycles 41039233 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53426011 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 56.556262 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 51809989 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42655255 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.154443 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 51339314 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43125930 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 45.652695 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 72336276 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22128968 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 23.425513 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 48368266 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46096978 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 48.797818 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 85310 # number of replacements +system.cpu.icache.tagsinuse 1887.040544 # Cycle average of tags in use +system.cpu.icache.total_refs 12359577 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 87356 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 141.485153 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1886.858130 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.921317 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.921317 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12263478 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12263478 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12263478 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12263478 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12263478 # number of overall hits -system.cpu.icache.overall_hits::total 12263478 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 116984 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 116984 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 116984 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 116984 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 116984 # number of overall misses -system.cpu.icache.overall_misses::total 116984 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2068004000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2068004000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2068004000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2068004000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2068004000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2068004000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12380462 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12380462 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12380462 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12380462 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12380462 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12380462 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009449 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009449 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009449 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17677.665322 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17677.665322 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17677.665322 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1887.040544 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.921407 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.921407 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12359577 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12359577 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12359577 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12359577 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12359577 # number of overall hits +system.cpu.icache.overall_hits::total 12359577 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 118263 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 118263 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 118263 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 118263 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 118263 # number of overall misses +system.cpu.icache.overall_misses::total 118263 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2089534000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2089534000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2089534000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2089534000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2089534000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2089534000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12477840 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12477840 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12477840 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12477840 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12477840 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12477840 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009478 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009478 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009478 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17668.535383 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17668.535383 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17668.535383 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1596000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1485500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 172 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 122 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 9279.069767 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 12176.229508 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 31328 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 31328 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 31328 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 31328 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 31328 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 31328 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 85656 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 85656 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 85656 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 85656 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 85656 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 85656 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1345401500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1345401500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1345401500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1345401500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1345401500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1345401500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006919 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006919 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006919 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15707.031615 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15707.031615 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15707.031615 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30907 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30907 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30907 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30907 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30907 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30907 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87356 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 87356 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 87356 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 87356 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 87356 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 87356 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1366128500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1366128500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1366128500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1366128500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1366128500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1366128500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15638.633866 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15638.633866 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15638.633866 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4073.105766 # Cycle average of tags in use -system.cpu.dcache.total_refs 34126014 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4073.126583 # Cycle average of tags in use +system.cpu.dcache.total_refs 34125996 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.000318 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 486265000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4073.105766 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994411 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994411 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180445 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180445 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13945569 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13945569 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34126014 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34126014 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34126014 # number of overall hits -system.cpu.dcache.overall_hits::total 34126014 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96193 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96193 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 667808 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 667808 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 764001 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 764001 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 764001 # number of overall misses -system.cpu.dcache.overall_misses::total 764001 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4158649000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4158649000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 35332073000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 35332073000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39490722000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39490722000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39490722000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39490722000 # number of overall miss cycles +system.cpu.dcache.avg_refs 167.000230 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 487962000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4073.126583 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994416 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994416 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180455 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180455 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13945541 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13945541 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34125996 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34125996 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34125996 # number of overall hits +system.cpu.dcache.overall_hits::total 34125996 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96183 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96183 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 667836 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 667836 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 764019 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 764019 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 764019 # number of overall misses +system.cpu.dcache.overall_misses::total 764019 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4158611000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4158611000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 35328865500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 35328865500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39487476500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39487476500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39487476500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39487476500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -236,31 +236,31 @@ system.cpu.dcache.demand_accesses::total 34890015 # nu system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004744 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045698 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021897 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43232.345389 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52907.531806 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51689.359045 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51689.359045 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045700 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021898 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021898 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43236.445110 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52900.510754 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51683.893332 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51683.893332 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6330522500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6329431500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 124112 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 124110 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51006.530392 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50998.561760 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 161216 # number of writebacks -system.cpu.dcache.writebacks::total 161216 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35426 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35426 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524228 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 524228 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 559654 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 559654 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 559654 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 559654 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 161215 # number of writebacks +system.cpu.dcache.writebacks::total 161215 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35416 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35416 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524256 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 524256 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 165078 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 174488 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 9410 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 165078 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 174488 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 377128500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343464000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1720592500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5262752500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5262752500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 377128500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6606216500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6983345000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 377128500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6606216500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6983345000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.554303 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.914655 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807817 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807817 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40076.783426 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40010.409531 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40020.615970 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40076.783426 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40018.540058 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40076.783426 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40018.540058 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807832 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807832 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40077.417641 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40010.244803 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40020.931559 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40077.417641 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40018.757799 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40077.417641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40018.757799 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index 8276bb368..4f0567259 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:19:29 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:42:57 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 21259532000 because target called exit() +Exiting @ tick 21302882000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index a0babad48..3e4315992 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021260 # Number of seconds simulated -sim_ticks 21259532000 # Number of ticks simulated -final_tick 21259532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021303 # Number of seconds simulated +sim_ticks 21302882000 # Number of ticks simulated +final_tick 21302882000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 240617 # Simulator instruction rate (inst/s) -host_op_rate 240617 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64270421 # Simulator tick rate (ticks/s) -host_mem_usage 219780 # Number of bytes of host memory used -host_seconds 330.78 # Real time elapsed on the host +host_inst_rate 238426 # Simulator instruction rate (inst/s) +host_op_rate 238426 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63815052 # Simulator tick rate (ticks/s) +host_mem_usage 219800 # Number of bytes of host memory used +host_seconds 333.82 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 11229312 # Number of bytes read from this memory -system.physmem.bytes_inst_read 642688 # Number of instructions bytes read from this memory -system.physmem.bytes_written 7713344 # Number of bytes written to this memory -system.physmem.num_reads 175458 # Number of read requests responded to by this memory -system.physmem.num_writes 120521 # Number of write requests responded to by this memory +system.physmem.bytes_read 11250368 # Number of bytes read from this memory +system.physmem.bytes_inst_read 658624 # Number of instructions bytes read from this memory +system.physmem.bytes_written 7713792 # Number of bytes written to this memory +system.physmem.num_reads 175787 # Number of read requests responded to by this memory +system.physmem.num_writes 120528 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 528201279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 30230581 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 362818147 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 891019426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 528114834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 30917131 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 362100865 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 890215699 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22309038 # DTB read hits -system.cpu.dtb.read_misses 216523 # DTB read misses -system.cpu.dtb.read_acv 41 # DTB read access violations -system.cpu.dtb.read_accesses 22525561 # DTB read accesses -system.cpu.dtb.write_hits 15629688 # DTB write hits -system.cpu.dtb.write_misses 39366 # DTB write misses -system.cpu.dtb.write_acv 9 # DTB write access violations -system.cpu.dtb.write_accesses 15669054 # DTB write accesses -system.cpu.dtb.data_hits 37938726 # DTB hits -system.cpu.dtb.data_misses 255889 # DTB misses -system.cpu.dtb.data_acv 50 # DTB access violations -system.cpu.dtb.data_accesses 38194615 # DTB accesses -system.cpu.itb.fetch_hits 13877051 # ITB hits -system.cpu.itb.fetch_misses 28133 # ITB misses +system.cpu.dtb.read_hits 22551743 # DTB read hits +system.cpu.dtb.read_misses 221888 # DTB read misses +system.cpu.dtb.read_acv 31 # DTB read access violations +system.cpu.dtb.read_accesses 22773631 # DTB read accesses +system.cpu.dtb.write_hits 15815895 # DTB write hits +system.cpu.dtb.write_misses 41880 # DTB write misses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_accesses 15857775 # DTB write accesses +system.cpu.dtb.data_hits 38367638 # DTB hits +system.cpu.dtb.data_misses 263768 # DTB misses +system.cpu.dtb.data_acv 34 # DTB access violations +system.cpu.dtb.data_accesses 38631406 # DTB accesses +system.cpu.itb.fetch_hits 14242802 # ITB hits +system.cpu.itb.fetch_misses 40881 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13905184 # ITB accesses +system.cpu.itb.fetch_accesses 14283683 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,247 +54,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 42519067 # number of cpu cycles simulated +system.cpu.numCycles 42605767 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16615602 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10784809 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 464390 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 14543138 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8570194 # Number of BTB hits +system.cpu.BPredUnit.lookups 16836861 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10841966 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 504890 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12277416 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7519870 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1986002 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 35485 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14905140 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105779121 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16615602 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 10556196 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20616414 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2026173 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 4867777 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 5763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 282637 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 13877051 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 219292 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 42124503 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.511107 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.106328 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 2023035 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 69381 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15349105 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 107382964 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16836861 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9542905 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19934365 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2235712 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 4959568 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 8744 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 326008 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14242802 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 231176 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 42192824 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.545053 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.166401 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21508089 51.06% 51.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2128231 5.05% 56.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1654689 3.93% 60.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2031982 4.82% 64.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3913911 9.29% 74.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1970832 4.68% 78.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 733979 1.74% 80.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1130432 2.68% 83.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7052358 16.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22258459 52.75% 52.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1558399 3.69% 56.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1415455 3.35% 59.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1535754 3.64% 63.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4212607 9.98% 73.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1888173 4.48% 77.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 696328 1.65% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1104060 2.62% 82.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7523589 17.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 42124503 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.390780 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.487804 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15964361 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4443062 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19692488 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 675645 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1348947 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3728678 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 99733 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103933078 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 280329 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1348947 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16452599 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2364451 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 84031 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19835916 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2038559 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102562493 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 192 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2676 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1925408 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61709040 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123636906 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123159992 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 476914 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 42192824 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.395178 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.520386 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16468277 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4517812 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18984446 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 716137 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1506152 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3833098 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 111400 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 105432186 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 305241 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1506152 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16967340 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2377848 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 83482 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19155996 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2102006 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103893842 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 209 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2243 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1985062 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 62645887 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 125253216 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 124792086 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 461130 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9162159 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5463 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5460 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4149992 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23138107 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16243401 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1017520 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 376699 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90712605 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5415 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88293060 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 101013 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10834162 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4923026 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 832 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 42124503 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.096002 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.077334 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 10099006 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6339 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6334 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4415607 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23483376 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16437713 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1109953 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 422268 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91768592 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5634 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89301611 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 133191 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11574502 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5080166 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1051 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 42192824 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.116512 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.120688 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13300851 31.58% 31.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7326403 17.39% 48.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5817137 13.81% 62.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4863957 11.55% 74.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4880067 11.58% 85.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2467879 5.86% 91.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1850711 4.39% 96.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1163401 2.76% 98.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 454097 1.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13823160 32.76% 32.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6872678 16.29% 49.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5530993 13.11% 62.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4799446 11.38% 73.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4794506 11.36% 84.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2657744 6.30% 91.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1943834 4.61% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1324843 3.14% 98.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 445620 1.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 42124503 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 42192824 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 99927 5.41% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 762620 41.31% 46.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 983690 53.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 129735 6.85% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 797111 42.11% 48.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 966009 51.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49334128 55.88% 55.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 44107 0.05% 55.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 126794 0.14% 56.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 90 0.00% 56.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 127284 0.14% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38913 0.04% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22763265 25.78% 82.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15858425 17.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49865595 55.84% 55.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43886 0.05% 55.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121283 0.14% 56.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121847 0.14% 56.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38973 0.04% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23075616 25.84% 82.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16034269 17.96% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88293060 # Type of FU issued -system.cpu.iq.rate 2.076552 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1846238 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020910 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 220034609 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101108296 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86316001 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 623265 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 459484 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 302223 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 89827554 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 311744 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1421900 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89301611 # Type of FU issued +system.cpu.iq.rate 2.095998 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1892856 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021196 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222206616 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102943544 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87154270 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 615477 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 421862 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 299078 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90886504 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 307963 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1459837 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2861469 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4255 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 15998 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1630024 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3206738 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5121 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17710 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1824336 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1270 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2474 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1348947 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1395228 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 60292 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100209488 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 330917 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23138107 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16243401 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5415 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 42613 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 717 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 15998 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 305754 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 116766 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 422520 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87324044 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22528336 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 969016 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1506152 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1422947 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 61908 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 101335985 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 260919 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23483376 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16437713 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5634 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 42556 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 655 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 17710 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 285901 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 175983 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 461884 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88268407 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22778571 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1033204 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9491468 # number of nop insts executed -system.cpu.iew.exec_refs 38197877 # number of memory reference insts executed -system.cpu.iew.exec_branches 15069707 # Number of branches executed -system.cpu.iew.exec_stores 15669541 # Number of stores executed -system.cpu.iew.exec_rate 2.053762 # Inst execution rate -system.cpu.iew.wb_sent 87015038 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86618224 # cumulative count of insts written-back -system.cpu.iew.wb_producers 32981280 # num instructions producing a value -system.cpu.iew.wb_consumers 42978824 # num instructions consuming a value +system.cpu.iew.exec_nop 9561759 # number of nop insts executed +system.cpu.iew.exec_refs 38636897 # number of memory reference insts executed +system.cpu.iew.exec_branches 15172966 # Number of branches executed +system.cpu.iew.exec_stores 15858326 # Number of stores executed +system.cpu.iew.exec_rate 2.071748 # Inst execution rate +system.cpu.iew.wb_sent 87882567 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87453348 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33493281 # num instructions producing a value +system.cpu.iew.wb_consumers 43663372 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.037162 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767384 # average fanout of values written-back +system.cpu.iew.wb_rate 2.052618 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767080 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitCommittedOps 88340672 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 8835054 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9892654 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 366565 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 40775556 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.166511 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.804904 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 396008 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 40686672 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.171243 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.822339 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17645835 43.28% 43.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7080138 17.36% 60.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3592753 8.81% 69.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2169640 5.32% 74.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2013725 4.94% 79.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1230420 3.02% 82.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1128970 2.77% 85.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 727312 1.78% 87.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5186763 12.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17747243 43.62% 43.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7065292 17.37% 60.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3424426 8.42% 69.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2111790 5.19% 74.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2029147 4.99% 79.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1183341 2.91% 82.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1120057 2.75% 85.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 705485 1.73% 86.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5299891 13.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 40775556 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 40686672 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -305,64 +305,64 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5186763 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5299891 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 131447177 # The number of ROB reads -system.cpu.rob.rob_writes 195703293 # The number of ROB writes -system.cpu.timesIdled 15923 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 394564 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132302765 # The number of ROB reads +system.cpu.rob.rob_writes 197976180 # The number of ROB writes +system.cpu.timesIdled 17931 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 412943 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.534214 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.534214 # CPI: Total CPI of All Threads -system.cpu.ipc 1.871907 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.871907 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115518864 # number of integer regfile reads -system.cpu.int_regfile_writes 57354047 # number of integer regfile writes -system.cpu.fp_regfile_reads 252314 # number of floating regfile reads -system.cpu.fp_regfile_writes 251108 # number of floating regfile writes -system.cpu.misc_regfile_reads 38108 # number of misc regfile reads +system.cpu.cpi 0.535304 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.535304 # CPI: Total CPI of All Threads +system.cpu.ipc 1.868098 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.868098 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116852046 # number of integer regfile reads +system.cpu.int_regfile_writes 57987678 # number of integer regfile writes +system.cpu.fp_regfile_reads 254259 # number of floating regfile reads +system.cpu.fp_regfile_writes 241396 # number of floating regfile writes +system.cpu.misc_regfile_reads 38319 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 88378 # number of replacements -system.cpu.icache.tagsinuse 1927.638696 # Cycle average of tags in use -system.cpu.icache.total_refs 13782143 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 90426 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 152.413498 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 17839872000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1927.638696 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.941230 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.941230 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13782143 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13782143 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13782143 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13782143 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13782143 # number of overall hits -system.cpu.icache.overall_hits::total 13782143 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 94908 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 94908 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 94908 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 94908 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 94908 # number of overall misses -system.cpu.icache.overall_misses::total 94908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 914028500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 914028500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 914028500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 914028500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 914028500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 914028500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13877051 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13877051 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13877051 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13877051 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13877051 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13877051 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006839 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.006839 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.006839 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9630.679184 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 9630.679184 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 9630.679184 # average overall miss latency +system.cpu.icache.replacements 94879 # number of replacements +system.cpu.icache.tagsinuse 1931.404224 # Cycle average of tags in use +system.cpu.icache.total_refs 14141018 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 96927 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 145.893487 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 17852736000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1931.404224 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.943068 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.943068 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14141018 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14141018 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14141018 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14141018 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14141018 # number of overall hits +system.cpu.icache.overall_hits::total 14141018 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 101784 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 101784 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 101784 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 101784 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 101784 # number of overall misses +system.cpu.icache.overall_misses::total 101784 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 964559500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 964559500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 964559500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 964559500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 964559500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 964559500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14242802 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14242802 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14242802 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14242802 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14242802 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14242802 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007146 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007146 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007146 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9476.533640 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 9476.533640 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 9476.533640 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -371,248 +371,248 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4481 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4481 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4481 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4481 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4481 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4481 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 90427 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 90427 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 90427 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 90427 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 90427 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 90427 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 542589500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 542589500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 542589500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 542589500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 542589500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 542589500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006516 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006516 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006516 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6000.304113 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6000.304113 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6000.304113 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4856 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4856 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4856 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4856 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4856 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4856 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 96928 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 96928 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 96928 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 96928 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 96928 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 96928 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 566036000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 566036000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 566036000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 566036000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 566036000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 566036000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006805 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006805 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006805 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5839.757346 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5839.757346 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5839.757346 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201340 # number of replacements -system.cpu.dcache.tagsinuse 4076.154176 # Cycle average of tags in use -system.cpu.dcache.total_refs 34207250 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205436 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.510495 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 157430000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.154176 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995155 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995155 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20628725 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20628725 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13578476 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13578476 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 49 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 49 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34207201 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34207201 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34207201 # number of overall hits -system.cpu.dcache.overall_hits::total 34207201 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 257071 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 257071 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1034901 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1034901 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1291972 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1291972 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1291972 # number of overall misses -system.cpu.dcache.overall_misses::total 1291972 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8273144500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8273144500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33900181500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33900181500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42173326000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42173326000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42173326000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42173326000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20885796 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20885796 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 201683 # number of replacements +system.cpu.dcache.tagsinuse 4076.258401 # Cycle average of tags in use +system.cpu.dcache.total_refs 34409774 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205779 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 167.217131 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 158059000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.258401 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995180 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995180 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20831540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20831540 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13578164 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13578164 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 70 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 70 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34409704 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34409704 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34409704 # number of overall hits +system.cpu.dcache.overall_hits::total 34409704 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 257782 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 257782 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1035213 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1035213 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1292995 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1292995 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1292995 # number of overall misses +system.cpu.dcache.overall_misses::total 1292995 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8279025500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8279025500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 34022399498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 34022399498 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 42301424998 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 42301424998 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 42301424998 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 42301424998 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21089322 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21089322 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 49 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 49 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35499173 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35499173 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35499173 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35499173 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012308 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070819 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036394 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036394 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32182.332896 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32756.931822 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32642.600614 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32642.600614 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 53500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2675 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 70 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 70 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35702699 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35702699 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35702699 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35702699 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012223 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070840 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036216 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036216 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32116.383223 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32865.120027 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32715.845767 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32715.845767 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 96500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6433.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 161613 # number of writebacks -system.cpu.dcache.writebacks::total 161613 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 195029 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 195029 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891507 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 891507 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1086536 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1086536 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1086536 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1086536 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62042 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62042 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143394 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143394 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205436 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205436 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205436 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205436 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1278233000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1278233000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4733826000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4733826000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6012059000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6012059000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6012059000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6012059000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002971 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005787 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005787 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20602.704619 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33012.720197 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29264.875679 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29264.875679 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 161705 # number of writebacks +system.cpu.dcache.writebacks::total 161705 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 195431 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 195431 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891785 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 891785 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1087216 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1087216 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1087216 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1087216 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62351 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62351 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143428 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143428 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205779 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205779 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205779 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205779 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1281958000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1281958000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4735775500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4735775500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6017733500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6017733500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6017733500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6017733500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002957 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005764 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005764 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20560.343860 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33018.486627 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29243.671609 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29243.671609 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 149119 # number of replacements -system.cpu.l2cache.tagsinuse 18923.797261 # Cycle average of tags in use -system.cpu.l2cache.total_refs 136861 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 174485 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.784371 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 149461 # number of replacements +system.cpu.l2cache.tagsinuse 18973.137542 # Cycle average of tags in use +system.cpu.l2cache.total_refs 143447 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 174828 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.820504 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15723.499493 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1497.146716 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1703.151052 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.479843 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.045689 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.051976 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.577508 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 80385 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 28006 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 108391 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 161613 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 161613 # 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number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12036 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12036 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 86637 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 40283 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 126920 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 86637 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 40283 # number of overall hits +system.cpu.l2cache.overall_hits::total 126920 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 10291 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 34099 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 44390 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 131397 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 131397 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 10291 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 165496 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 175787 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 10291 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 165496 # number of overall misses +system.cpu.l2cache.overall_misses::total 175787 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 353191500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1174547500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1527739000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4525137500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4525137500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 353191500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5699685000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6052876500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 353191500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5699685000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6052876500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 96928 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 62346 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 159274 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 161705 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 161705 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143433 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143433 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 96928 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205779 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 302707 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 96928 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205779 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 302707 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.106172 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.546932 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.916086 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.106172 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.804241 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.106172 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.804241 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34320.425615 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34445.218335 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34438.666788 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.425615 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.016677 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.425615 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.016677 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 29000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2636.363636 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 120521 # number of writebacks -system.cpu.l2cache.writebacks::total 120521 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10042 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 34008 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 44050 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131408 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 131408 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10042 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 165416 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 175458 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10042 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 165416 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 175458 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 312130500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1055457000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1367587500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4118168500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4118168500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 312130500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5173625500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5485756000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 312130500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5173625500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5485756000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.111051 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.548392 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.916233 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.111051 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.805195 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.111051 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.805195 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31082.503485 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31035.550459 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31338.795964 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31082.503485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31276.451492 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31082.503485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31276.451492 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 120528 # number of writebacks +system.cpu.l2cache.writebacks::total 120528 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10291 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 34099 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 44390 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131397 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131397 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10291 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 165496 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 175787 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10291 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 165496 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 175787 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 319907000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1058267500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1378174500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4118158500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4118158500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 319907000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5176426000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5496333000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 319907000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5176426000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5496333000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.106172 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.546932 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.916086 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.106172 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.804241 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.106172 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.804241 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31086.094646 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31035.147658 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31341.343410 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31086.094646 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31278.254459 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31086.094646 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31278.254459 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index e2d26e372..2abcbcd2a 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:25:27 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:47:12 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 31189496500 because target called exit() +Exiting @ tick 30746529500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 228286404..a9b05e877 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.031189 # Number of seconds simulated -sim_ticks 31189496500 # Number of ticks simulated -final_tick 31189496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.030747 # Number of seconds simulated +sim_ticks 30746529500 # Number of ticks simulated +final_tick 30746529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 144507 # Simulator instruction rate (inst/s) -host_op_rate 205068 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63556485 # Simulator tick rate (ticks/s) -host_mem_usage 231932 # Number of bytes of host memory used -host_seconds 490.74 # Real time elapsed on the host -sim_insts 70914922 # Number of instructions simulated -sim_ops 100634170 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 8651712 # Number of bytes read from this memory -system.physmem.bytes_inst_read 350080 # Number of instructions bytes read from this memory -system.physmem.bytes_written 5661248 # Number of bytes written to this memory -system.physmem.num_reads 135183 # Number of read requests responded to by this memory -system.physmem.num_writes 88457 # Number of write requests responded to by this memory +host_inst_rate 146131 # Simulator instruction rate (inst/s) +host_op_rate 207370 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63356016 # Simulator tick rate (ticks/s) +host_mem_usage 232084 # Number of bytes of host memory used +host_seconds 485.30 # Real time elapsed on the host +sim_insts 70917047 # Number of instructions simulated +sim_ops 100636295 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 8680064 # Number of bytes read from this memory +system.physmem.bytes_inst_read 363776 # Number of instructions bytes read from this memory +system.physmem.bytes_written 5661120 # Number of bytes written to this memory +system.physmem.num_reads 135626 # Number of read requests responded to by this memory +system.physmem.num_writes 88455 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 277391846 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 11224291 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 181511362 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 458903208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 282310366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 11831449 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 184122244 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 466432610 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,316 +64,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 62378994 # number of cpu cycles simulated +system.cpu.numCycles 61493060 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 17633191 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11526968 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 822695 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15043788 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 9743985 # Number of BTB hits +system.cpu.BPredUnit.lookups 17207683 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11124675 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 739996 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12413226 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8258713 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1887457 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 176874 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12969342 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88531281 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17633191 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11631442 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22985471 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2899094 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 23117489 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 528 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12209631 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 231060 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 61072156 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.021104 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.077628 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1860363 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 182681 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 13006035 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87629176 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17207683 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 10119076 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21952285 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2766047 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 23185818 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2820 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12232999 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 233597 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 60095316 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.044969 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.137732 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 38102442 62.39% 62.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2437370 3.99% 66.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2604913 4.27% 70.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2468790 4.04% 74.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1717886 2.81% 77.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1703957 2.79% 80.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1004465 1.64% 81.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1297144 2.12% 84.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9735189 15.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 38160956 63.50% 63.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2271093 3.78% 67.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1990023 3.31% 70.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2119724 3.53% 74.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1647401 2.74% 76.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1441763 2.40% 79.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1000150 1.66% 80.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1230223 2.05% 82.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10233983 17.03% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 61072156 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.282678 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.419248 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14874533 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 21847562 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 21380234 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1066852 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1902975 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3467400 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 97940 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 120324997 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 332105 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1902975 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16806585 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2006065 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15518837 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20487124 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4350570 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 117025506 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3620 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3001536 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 62 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 118973415 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 538271633 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 538269997 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1636 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99144341 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 19829074 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 778296 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 778691 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12144889 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29749506 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22307130 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2475389 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3455641 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111742619 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 774376 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107620542 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 306039 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11663320 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29339036 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 71343 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 61072156 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.762187 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.902803 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 60095316 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.279831 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.425025 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14817180 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 21950690 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20398412 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1086428 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1842606 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3463605 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 108661 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 119794628 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 354485 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1842606 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16634867 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1966833 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15615217 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19642472 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4393321 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 116600703 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4194 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3033361 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 70 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 116869923 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536821347 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 536814358 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6989 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99147741 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 17722182 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 787670 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 786973 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12493394 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29971388 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22471181 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2503550 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3551864 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111668104 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 780017 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107789312 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 331076 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11606029 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 28797672 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 76559 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 60095316 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.793639 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.921516 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 22164835 36.29% 36.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11626045 19.04% 55.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8572984 14.04% 69.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7394656 12.11% 81.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4788181 7.84% 89.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3517678 5.76% 95.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1664983 2.73% 97.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 808803 1.32% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 533991 0.87% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21617080 35.97% 35.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11242625 18.71% 54.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8368043 13.92% 68.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7334755 12.21% 80.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4853612 8.08% 88.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3598814 5.99% 94.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1699571 2.83% 97.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 846136 1.41% 99.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 534680 0.89% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 61072156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 60095316 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 87531 3.32% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1485029 56.34% 59.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1063128 40.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 104237 3.89% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 1 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1507488 56.31% 60.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1065632 39.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57005331 52.97% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 87377 0.08% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 40 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28993103 26.94% 79.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21534684 20.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56897133 52.79% 52.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 88643 0.08% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 206 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29161823 27.05% 79.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21641500 20.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107620542 # Type of FU issued -system.cpu.iq.rate 1.725269 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2635688 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024491 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 279254757 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 124195436 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105415832 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 210 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 218 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110256122 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 108 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1866930 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107789312 # Type of FU issued +system.cpu.iq.rate 1.752870 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2677358 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024839 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 278681648 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 124068735 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105618069 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 726 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1184 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 180 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110466305 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 365 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1905391 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2440940 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3458 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 15970 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1749935 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2662397 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4708 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 16942 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1913561 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 51 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 52 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 60 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1902975 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 953135 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 28579 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 112593446 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 617881 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29749506 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22307130 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 757118 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1133 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1194 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 15970 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 682654 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 198883 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 881537 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106278016 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28622846 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1342526 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1842606 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 954066 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 28419 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 112530590 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 448477 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29971388 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22471181 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 763809 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1185 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1150 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 16942 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 525308 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 249263 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 774571 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106544172 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28789537 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1245140 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 76451 # number of nop insts executed -system.cpu.iew.exec_refs 49854993 # number of memory reference insts executed -system.cpu.iew.exec_branches 14601868 # Number of branches executed -system.cpu.iew.exec_stores 21232147 # Number of stores executed -system.cpu.iew.exec_rate 1.703747 # Inst execution rate -system.cpu.iew.wb_sent 105729046 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105415908 # cumulative count of insts written-back -system.cpu.iew.wb_producers 52516965 # num instructions producing a value -system.cpu.iew.wb_consumers 101175097 # num instructions consuming a value +system.cpu.iew.exec_nop 82469 # number of nop insts executed +system.cpu.iew.exec_refs 50119660 # number of memory reference insts executed +system.cpu.iew.exec_branches 14611553 # Number of branches executed +system.cpu.iew.exec_stores 21330123 # Number of stores executed +system.cpu.iew.exec_rate 1.732621 # Inst execution rate +system.cpu.iew.wb_sent 105962456 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105618249 # cumulative count of insts written-back +system.cpu.iew.wb_producers 52610922 # num instructions producing a value +system.cpu.iew.wb_consumers 101691142 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.689926 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.519070 # average fanout of values written-back +system.cpu.iew.wb_rate 1.717564 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.517360 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 70920474 # The number of committed instructions -system.cpu.commit.commitCommittedOps 100639722 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 11954174 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 703033 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 788567 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 59169182 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.700881 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.430495 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 70922599 # The number of committed instructions +system.cpu.commit.commitCommittedOps 100641847 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 11889102 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 703458 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 696794 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 58252711 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.727677 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.445395 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 26246833 44.36% 44.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14645427 24.75% 69.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4228470 7.15% 76.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3643076 6.16% 82.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2266929 3.83% 86.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1888235 3.19% 89.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 703093 1.19% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 496274 0.84% 91.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5050845 8.54% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 25477544 43.74% 43.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14542293 24.96% 68.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4151131 7.13% 75.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3607676 6.19% 82.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2313094 3.97% 85.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1905802 3.27% 89.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 675667 1.16% 90.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 497156 0.85% 91.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5082348 8.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 59169182 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70920474 # Number of instructions committed -system.cpu.commit.committedOps 100639722 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 58252711 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70922599 # Number of instructions committed +system.cpu.commit.committedOps 100641847 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47865761 # Number of memory references committed -system.cpu.commit.loads 27308566 # Number of loads committed +system.cpu.commit.refs 47866611 # Number of memory references committed +system.cpu.commit.loads 27308991 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13670085 # Number of branches committed +system.cpu.commit.branches 13670510 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91478615 # Number of committed integer instructions. +system.cpu.commit.int_insts 91480315 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5050845 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5082348 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 166686934 # The number of ROB reads -system.cpu.rob.rob_writes 227096473 # The number of ROB writes -system.cpu.timesIdled 61617 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1306838 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70914922 # Number of Instructions Simulated -system.cpu.committedOps 100634170 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70914922 # Number of Instructions Simulated -system.cpu.cpi 0.879631 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.879631 # CPI: Total CPI of All Threads -system.cpu.ipc 1.136840 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.136840 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511674990 # number of integer regfile reads -system.cpu.int_regfile_writes 103897673 # number of integer regfile writes -system.cpu.fp_regfile_reads 166 # number of floating regfile reads -system.cpu.fp_regfile_writes 126 # number of floating regfile writes -system.cpu.misc_regfile_reads 146219619 # number of misc regfile reads -system.cpu.misc_regfile_writes 34754 # number of misc regfile writes -system.cpu.icache.replacements 26131 # number of replacements -system.cpu.icache.tagsinuse 1805.600642 # Cycle average of tags in use -system.cpu.icache.total_refs 12180358 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 28166 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 432.448981 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 165676013 # The number of ROB reads +system.cpu.rob.rob_writes 226913156 # The number of ROB writes +system.cpu.timesIdled 61654 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1397744 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70917047 # Number of Instructions Simulated +system.cpu.committedOps 100636295 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70917047 # Number of Instructions Simulated +system.cpu.cpi 0.867113 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.867113 # CPI: Total CPI of All Threads +system.cpu.ipc 1.153253 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.153253 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 512941825 # number of integer regfile reads +system.cpu.int_regfile_writes 103506893 # number of integer regfile writes +system.cpu.fp_regfile_reads 822 # number of floating regfile reads +system.cpu.fp_regfile_writes 678 # number of floating regfile writes +system.cpu.misc_regfile_reads 145707136 # number of misc regfile reads +system.cpu.misc_regfile_writes 35604 # number of misc regfile writes +system.cpu.icache.replacements 30139 # number of replacements +system.cpu.icache.tagsinuse 1825.169858 # Cycle average of tags in use +system.cpu.icache.total_refs 12199552 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 32178 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 379.127105 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1805.600642 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.881641 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.881641 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12180359 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12180359 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12180359 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12180359 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12180359 # number of overall hits -system.cpu.icache.overall_hits::total 12180359 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 29272 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 29272 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 29272 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 29272 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 29272 # number of overall misses -system.cpu.icache.overall_misses::total 29272 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 357988500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 357988500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 357988500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 357988500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 357988500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 357988500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12209631 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12209631 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12209631 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12209631 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12209631 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12209631 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002397 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002397 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002397 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12229.724652 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12229.724652 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12229.724652 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1825.169858 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.891196 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.891196 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12199556 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12199556 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12199556 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12199556 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12199556 # number of overall hits +system.cpu.icache.overall_hits::total 12199556 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 33443 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 33443 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 33443 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 33443 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 33443 # number of overall misses +system.cpu.icache.overall_misses::total 33443 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 390329000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 390329000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 390329000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 390329000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 390329000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 390329000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12232999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12232999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12232999 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12232999 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12232999 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12232999 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002734 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002734 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002734 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11671.470861 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11671.470861 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11671.470861 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,223 +382,224 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1063 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1063 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1063 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1063 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1063 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1063 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28209 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 28209 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 28209 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 28209 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 28209 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 28209 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 247071500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 247071500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 247071500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 247071500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 247071500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 247071500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002310 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002310 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002310 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8758.605410 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8758.605410 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8758.605410 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1227 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1227 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1227 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1227 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1227 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1227 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32216 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 32216 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 32216 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 32216 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 32216 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 32216 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262568000 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8150.235908 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157892 # number of replacements -system.cpu.dcache.tagsinuse 4072.334227 # Cycle average of tags in use -system.cpu.dcache.total_refs 44746410 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 161988 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 276.232869 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 306594000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.334227 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994222 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994222 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26399659 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26399659 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18310286 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18310286 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 18924 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 18924 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 17376 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 17376 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44709945 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44709945 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44709945 # number of overall hits -system.cpu.dcache.overall_hits::total 44709945 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 108879 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 108879 # 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number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 349000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 349000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 54702406000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 54702406000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 54702406000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 54702406000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26508538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26508538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 158787 # number of replacements +system.cpu.dcache.tagsinuse 4071.855025 # Cycle average of tags in use +system.cpu.dcache.total_refs 44862936 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162883 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 275.430438 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 309114000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4071.855025 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994105 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994105 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26515454 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26515454 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18310363 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18310363 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 19173 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 19173 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 17801 # 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number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1650108 # number of overall misses +system.cpu.dcache.overall_misses::total 1650108 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2444111000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2444111000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 52524497000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 52524497000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 460000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 460000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54968608000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54968608000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54968608000 # 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average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33183.260600 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 19208 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 19208 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 17801 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 17801 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46475925 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46475925 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46475925 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46475925 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004153 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077559 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001822 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.035505 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.035505 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22104.648639 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34117.051349 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13142.857143 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33312.127449 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33312.127449 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 190500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 210500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19050 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19136.363636 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 123473 # number of writebacks -system.cpu.dcache.writebacks::total 123473 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53766 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 53766 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1432695 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1432695 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 26 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 26 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1486461 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1486461 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1486461 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1486461 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55113 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55113 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106920 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 106920 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162033 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162033 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162033 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162033 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1035745500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1035745500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3662420000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3662420000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4698165500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4698165500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4698165500 # 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number of writebacks +system.cpu.dcache.writebacks::total 123777 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54544 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 54544 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1432641 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1432641 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 35 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 35 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1487185 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1487185 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1487185 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1487185 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56026 # 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mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.722121 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31084.415105 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31033.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31169.473766 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.722121 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31151.692583 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.722121 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31151.692583 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 88455 # number of writebacks +system.cpu.l2cache.writebacks::total 88455 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 23 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 64 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 64 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 87 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5684 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27361 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33045 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 29 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 29 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102581 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102581 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5684 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 129942 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 135626 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5684 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 129942 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 135626 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176568000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 850424500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1026992500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 901000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 901000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3193612500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3193612500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176568000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4044037000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4220605000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176568000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4044037000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4220605000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.176664 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.488677 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.725000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959661 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.176664 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.797763 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.176664 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.797763 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31064.039409 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31081.630788 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31068.965517 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31132.592780 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31064.039409 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31121.862062 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31064.039409 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31121.862062 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout index d36129661..b48111dc2 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:25:39 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:49:22 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1009857089500 because target called exit() +Exiting @ tick 1009998808500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index d5a78ee76..b53980a02 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.009857 # Number of seconds simulated -sim_ticks 1009857089500 # Number of ticks simulated -final_tick 1009857089500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.009999 # Number of seconds simulated +sim_ticks 1009998808500 # Number of ticks simulated +final_tick 1009998808500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137029 # Simulator instruction rate (inst/s) -host_op_rate 137029 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76042102 # Simulator tick rate (ticks/s) -host_mem_usage 209964 # Number of bytes of host memory used -host_seconds 13280.24 # Real time elapsed on the host +host_inst_rate 135204 # Simulator instruction rate (inst/s) +host_op_rate 135204 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75039783 # Simulator tick rate (ticks/s) +host_mem_usage 209960 # Number of bytes of host memory used +host_seconds 13459.51 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 172617984 # Number of bytes read from this memory -system.physmem.bytes_inst_read 54912 # Number of instructions bytes read from this memory +system.physmem.bytes_read 172618048 # Number of bytes read from this memory +system.physmem.bytes_inst_read 54976 # Number of instructions bytes read from this memory system.physmem.bytes_written 74938304 # Number of bytes written to this memory -system.physmem.num_reads 2697156 # Number of read requests responded to by this memory +system.physmem.num_reads 2697157 # Number of read requests responded to by this memory system.physmem.num_writes 1170911 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 170933081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 54376 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 74206841 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 245139922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 170909160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 54432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 74196428 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 245105588 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444614420 # DTB read hits +system.cpu.dtb.read_hits 444614444 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449511498 # DTB read accesses -system.cpu.dtb.write_hits 160920903 # DTB write hits +system.cpu.dtb.read_accesses 449511522 # DTB read accesses +system.cpu.dtb.write_hits 160920906 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162622207 # DTB write accesses -system.cpu.dtb.data_hits 605535323 # DTB hits +system.cpu.dtb.write_accesses 162622210 # DTB write accesses +system.cpu.dtb.data_hits 605535350 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612133705 # DTB accesses -system.cpu.itb.fetch_hits 233080732 # ITB hits +system.cpu.dtb.data_accesses 612133732 # DTB accesses +system.cpu.itb.fetch_hits 231980230 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 233080754 # ITB accesses +system.cpu.itb.fetch_accesses 231980252 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,16 +54,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2019714180 # number of cpu cycles simulated +system.cpu.numCycles 2019997618 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1746235830 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1746428176 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7533712 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 442869413 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1576844767 # Number of cycles cpu stages are processed. -system.cpu.activity 78.072669 # Percentage of cycles cpu is active +system.cpu.timesIdled 7533729 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 443112454 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1576885164 # Number of cycles cpu stages are processed. +system.cpu.activity 78.063714 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -75,158 +75,158 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.109867 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.110023 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 1.109867 # CPI: Total CPI of All Threads -system.cpu.ipc 0.901009 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.110023 # CPI: Total CPI of All Threads +system.cpu.ipc 0.900882 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.901009 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 330376347 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 257464252 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 140461747 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 220099806 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 142435401 # Number of BTB hits +system.cpu.ipc_total 0.900882 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 328891112 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 253883187 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 140042357 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 232477361 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 138151285 # Number of BTB hits system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 64.714006 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 178933469 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 151442878 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1665721133 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 59.425694 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 175108073 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 153783039 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1669728742 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3041923750 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3045931359 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 235 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 654640669 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617252269 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 126684712 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 7178577 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 133863289 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 81336473 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.204199 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1137868323 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 580 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651109695 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617989652 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 121368305 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 12075594 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 133443899 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 81756170 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 62.009227 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139611303 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 827214176 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1192500004 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 59.043008 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1086300254 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933413926 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.215149 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1046559994 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 973154186 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.182767 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1609984436 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409729744 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.286521 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 997434545 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022279635 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 50.615065 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 829317091 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1190680527 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 58.944650 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1087591326 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 932406292 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.158782 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1046003601 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 973994017 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.217582 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1610294122 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409703496 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.282375 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 997062989 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1022934629 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 50.640388 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 664.479191 # Cycle average of tags in use -system.cpu.icache.total_refs 233079667 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 858 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 271654.623543 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 666.311000 # Cycle average of tags in use +system.cpu.icache.total_refs 231979155 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 270057.223516 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 664.479191 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.324453 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.324453 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 233079667 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 233079667 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 233079667 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 233079667 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 233079667 # number of overall hits -system.cpu.icache.overall_hits::total 233079667 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1062 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1062 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1062 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1062 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1062 # number of overall misses -system.cpu.icache.overall_misses::total 1062 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58337000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58337000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 58337000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58337000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 58337000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58337000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 233080729 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 233080729 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 233080729 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 233080729 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 233080729 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 233080729 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 666.311000 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325347 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325347 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 231979155 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 231979155 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 231979155 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 231979155 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 231979155 # number of overall hits +system.cpu.icache.overall_hits::total 231979155 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1072 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1072 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1072 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1072 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1072 # number of overall misses +system.cpu.icache.overall_misses::total 1072 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58539000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58539000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58539000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58539000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58539000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58539000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 231980227 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 231980227 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 231980227 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 231980227 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 231980227 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 231980227 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54931.261770 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54931.261770 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54931.261770 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54607.276119 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 83500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 125500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 27833.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 31375 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 204 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 204 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 204 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 204 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 204 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 204 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 858 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 858 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 858 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 858 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 858 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 858 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45872500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45872500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45872500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45872500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45872500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45872500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 213 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 213 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 213 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45929000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45929000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45929000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45929000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45929000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45929000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53464.452214 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53464.452214 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53464.452214 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53467.986030 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107352 # number of replacements -system.cpu.dcache.tagsinuse 4082.611665 # Cycle average of tags in use -system.cpu.dcache.total_refs 595070081 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4082.536815 # Cycle average of tags in use +system.cpu.dcache.total_refs 595069970 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.310155 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12612838000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.611665 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996731 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996731 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437271428 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437271428 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 157798653 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 157798653 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 595070081 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 595070081 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 595070081 # number of overall hits -system.cpu.dcache.overall_hits::total 595070081 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7324235 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7324235 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2929849 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2929849 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 10254084 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10254084 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10254084 # number of overall misses -system.cpu.dcache.overall_misses::total 10254084 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 180892053500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 180892053500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 110288339500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 110288339500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 291180393000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 291180393000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 291180393000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 291180393000 # number of overall miss cycles +system.cpu.dcache.avg_refs 65.310143 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12672189000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.536815 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996713 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996713 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437271423 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437271423 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 157798547 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 157798547 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 595069970 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 595069970 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 595069970 # number of overall hits +system.cpu.dcache.overall_hits::total 595069970 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7324240 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7324240 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2929955 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2929955 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 10254195 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10254195 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10254195 # number of overall misses +system.cpu.dcache.overall_misses::total 10254195 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 180897499500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 180897499500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 110294932000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 110294932000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 291192431500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 291192431500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 291192431500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 291192431500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -239,28 +239,28 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018229 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.016940 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016940 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24697.740242 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37643.011466 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28396.528934 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28396.528934 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10999000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8091026500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2761 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 208994 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3983.701557 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 38714.156866 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24698.466940 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37643.899650 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11000000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8092150500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2762 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 209020 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3982.621289 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 38714.718687 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3058572 # number of writebacks system.cpu.dcache.writebacks::total 3058572 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101953 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 101953 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1040683 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1040683 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1142636 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1142636 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1142636 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1142636 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101958 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 101958 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1040789 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1040789 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1142747 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1142747 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1142747 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1142747 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222282 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222282 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889166 # number of WriteReq MSHR misses @@ -269,36 +269,36 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111448 system.cpu.dcache.demand_mshr_misses::total 9111448 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111448 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111448 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156087671000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 156087671000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59191835500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 59191835500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215279506500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 215279506500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215279506500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 215279506500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156091594000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 156091594000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59191446500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 59191446500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215283040500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 215283040500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215283040500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 215283040500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21611.960181 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31332.257462 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23627.364882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23627.364882 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21612.503361 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31332.051551 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23627.752746 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23627.752746 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2686299 # number of replacements -system.cpu.l2cache.tagsinuse 26355.239368 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7564573 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2710943 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.790384 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 223979031000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 10843.964569 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 26.537327 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15484.737472 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.330932 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000810 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.472557 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.804298 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 2686301 # number of replacements +system.cpu.l2cache.tagsinuse 26348.804807 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7564571 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2710944 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.790383 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 224336260000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 10843.214494 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 26.756246 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15478.834067 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.330909 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000817 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.472377 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.804102 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 5414817 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5414817 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3058572 # number of Writeback hits @@ -309,41 +309,41 @@ system.cpu.l2cache.demand_hits::cpu.data 6415150 # nu system.cpu.l2cache.demand_hits::total 6415150 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.data 6415150 # number of overall hits system.cpu.l2cache.overall_hits::total 6415150 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 858 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 1807023 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1807881 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1807882 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 889275 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 889275 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 858 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 2696298 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2697156 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 858 # number of overall misses +system.cpu.l2cache.demand_misses::total 2697157 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2696298 # number of overall misses -system.cpu.l2cache.overall_misses::total 2697156 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44903500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94408605500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 94453509000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46507390000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 46507390000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 44903500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 140915995500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 140960899000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 44903500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 140915995500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 140960899000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 858 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 2697157 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44955000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94411778000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 94456733000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46506892000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 46506892000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 44955000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 140918670000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 140963625000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 44955000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 140918670000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 140963625000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7221840 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7222698 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7222699 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 3058572 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 3058572 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889608 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889608 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 858 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 9111448 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112306 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 858 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112307 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 9111448 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112306 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112307 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250216 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.470613 # miss rate for ReadExReq accesses @@ -351,13 +351,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 1 system.cpu.l2cache.demand_miss_rate::cpu.data 0.295924 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.295924 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52335.081585 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52245.381215 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52298.096764 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52335.081585 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52262.767506 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52335.081585 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52262.767506 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52334.109430 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52247.136865 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52297.536757 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52334.109430 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52263.759421 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52334.109430 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52263.759421 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked @@ -368,28 +368,28 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1170911 # number of writebacks system.cpu.l2cache.writebacks::total 1170911 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 858 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1807023 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1807881 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1807882 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889275 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 889275 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 858 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2696298 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2697156 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 858 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2697157 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2696298 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2697156 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34440500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72319858000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72354298500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35671113500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35671113500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34440500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107990971500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 108025412000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34440500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107990971500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 108025412000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 2697157 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34480500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72319844500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72354325000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35671150000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35671150000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34480500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107990994500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 108025475000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34480500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107990994500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 108025475000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250216 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470613 # mshr miss rate for ReadExReq accesses @@ -397,13 +397,13 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.442890 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.548149 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.578786 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.442890 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.571265 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.442890 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.571265 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.279395 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.540678 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.619831 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index 17636478e..6f27fa680 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:26:22 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:50:00 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 615292058500 because target called exit() +Exiting @ tick 614317285000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index a211c592b..2f0a96bc0 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.615292 # Number of seconds simulated -sim_ticks 615292058500 # Number of ticks simulated -final_tick 615292058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.614317 # Number of seconds simulated +sim_ticks 614317285000 # Number of ticks simulated +final_tick 614317285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 195644 # Simulator instruction rate (inst/s) -host_op_rate 195644 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69340417 # Simulator tick rate (ticks/s) -host_mem_usage 211040 # Number of bytes of host memory used -host_seconds 8873.50 # Real time elapsed on the host +host_inst_rate 195309 # Simulator instruction rate (inst/s) +host_op_rate 195309 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69112237 # Simulator tick rate (ticks/s) +host_mem_usage 211096 # Number of bytes of host memory used +host_seconds 8888.69 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 173080384 # Number of bytes read from this memory -system.physmem.bytes_inst_read 60288 # Number of instructions bytes read from this memory -system.physmem.bytes_written 74996480 # Number of bytes written to this memory -system.physmem.num_reads 2704381 # Number of read requests responded to by this memory -system.physmem.num_writes 1171820 # Number of write requests responded to by this memory +system.physmem.bytes_read 173249728 # Number of bytes read from this memory +system.physmem.bytes_inst_read 62784 # Number of instructions bytes read from this memory +system.physmem.bytes_written 75020608 # Number of bytes written to this memory +system.physmem.num_reads 2707027 # Number of read requests responded to by this memory +system.physmem.num_writes 1172197 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 281297933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 97983 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 121887612 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 403185545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 282019947 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 102201 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 122120295 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 404140242 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 602552271 # DTB read hits -system.cpu.dtb.read_misses 10614048 # DTB read misses +system.cpu.dtb.read_hits 613430411 # DTB read hits +system.cpu.dtb.read_misses 10984160 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 613166319 # DTB read accesses -system.cpu.dtb.write_hits 207913538 # DTB write hits -system.cpu.dtb.write_misses 6806894 # DTB write misses +system.cpu.dtb.read_accesses 624414571 # DTB read accesses +system.cpu.dtb.write_hits 208466528 # DTB write hits +system.cpu.dtb.write_misses 6835381 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 214720432 # DTB write accesses -system.cpu.dtb.data_hits 810465809 # DTB hits -system.cpu.dtb.data_misses 17420942 # DTB misses +system.cpu.dtb.write_accesses 215301909 # DTB write accesses +system.cpu.dtb.data_hits 821896939 # DTB hits +system.cpu.dtb.data_misses 17819541 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 827886751 # DTB accesses -system.cpu.itb.fetch_hits 385401096 # ITB hits -system.cpu.itb.fetch_misses 38 # ITB misses +system.cpu.dtb.data_accesses 839716480 # DTB accesses +system.cpu.itb.fetch_hits 401793450 # ITB hits +system.cpu.itb.fetch_misses 51 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 385401134 # ITB accesses +system.cpu.itb.fetch_accesses 401793501 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,247 +54,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1230584118 # number of cpu cycles simulated +system.cpu.numCycles 1228634571 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 368788427 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 284655595 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 19443984 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 335810201 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 329206676 # Number of BTB hits +system.cpu.BPredUnit.lookups 381761173 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 293769294 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18987814 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 267293652 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 262906896 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 24336435 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1745 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 397544739 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3103801885 # Number of instructions fetch has processed -system.cpu.fetch.Branches 368788427 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 353543111 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 607804339 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 131920976 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 113986099 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 951 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 385401096 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9585477 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1225061020 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.533590 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.019465 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 25187123 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6338 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 413237757 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3162516337 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381761173 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 288094019 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 577364277 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 136217023 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 121997880 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1099 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 401793450 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10461001 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1223060627 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.585740 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.163188 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 617256681 50.39% 50.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 52795543 4.31% 54.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 34983733 2.86% 57.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 53721044 4.39% 61.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 135046011 11.02% 72.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 74719502 6.10% 79.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 51323378 4.19% 83.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 43567102 3.56% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 161648026 13.20% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 645696350 52.79% 52.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 43491890 3.56% 56.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22343235 1.83% 58.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 40947227 3.35% 61.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 127434510 10.42% 71.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 63845944 5.22% 77.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40777509 3.33% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30328214 2.48% 82.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 208195748 17.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1225061020 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.299686 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.522218 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 426009855 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101612047 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 578250802 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13464213 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 105724103 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 57118243 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 889 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3023280149 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1933 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 105724103 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 448226724 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 58166398 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3444 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 568166155 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 44774196 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2937967281 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 510732 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1525332 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 40266143 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2197783940 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3797275773 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3796267426 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1008347 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1223060627 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310720 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.574009 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 442798352 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 107558051 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 546235232 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16010373 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 110458619 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 60401844 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1104 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3083471433 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2212 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 110458619 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 464144259 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 59142722 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6290 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 539650759 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 49657978 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3001214428 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 543640 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1796675 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 45123611 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2245055787 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3876991628 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3875592361 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1399267 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 821580977 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 180 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 178 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 93606956 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 663953354 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 248514283 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 54484359 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 31450059 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2647456890 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 154 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2459087861 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1981205 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 899874302 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 377613541 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1225061020 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.007319 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.938295 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 868852824 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 246 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 246 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 105587598 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 677972013 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 251679590 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 61268278 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 33927488 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2695905085 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 208 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2494910980 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3371495 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 947658243 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 400911726 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 179 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1223060627 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.039892 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.968690 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 390052689 31.84% 31.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 197664545 16.14% 47.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 194534552 15.88% 63.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 152397104 12.44% 76.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 138172730 11.28% 87.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 75830053 6.19% 93.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 56958095 4.65% 98.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14036871 1.15% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5414381 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 388423198 31.76% 31.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 198296660 16.21% 47.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 183821950 15.03% 63.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153332369 12.54% 75.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 135876340 11.11% 86.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79653803 6.51% 93.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 63718799 5.21% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14613920 1.19% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5323588 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1225061020 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1223060627 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1870870 11.50% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11042349 67.89% 79.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3352440 20.61% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2019639 10.76% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12227310 65.14% 75.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4524424 24.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1607157901 65.36% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 88 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 251 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 20 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 149 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 19 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 631365239 25.67% 91.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 220564170 8.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1630534588 65.35% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 292 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 176 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 34 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 642000765 25.73% 91.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 222374992 8.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2459087861 # Type of FU issued -system.cpu.iq.rate 1.998309 # Inst issue rate -system.cpu.iq.fu_busy_cnt 16265659 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006615 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6159722029 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3546409355 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2357254024 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1761577 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1006663 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 825129 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2474476437 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 877083 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54564037 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2494910980 # Type of FU issued +system.cpu.iq.rate 2.030637 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18771373 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007524 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6233033546 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3642313752 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2391820907 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1991909 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1355027 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 871735 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2512703438 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 978915 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57347014 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 219357691 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 276764 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 87944 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 87785781 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 233376350 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 247116 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 107150 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 90951088 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 71 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 162830 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 227 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 162717 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 105724103 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22305472 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1113476 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2788688851 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 12944530 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 663953354 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 248514283 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 154 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 231462 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18115 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 87944 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 20335960 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2039327 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 22375287 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2405013673 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 613166540 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 54074188 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 110458619 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22362549 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1121439 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2838563958 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 17898504 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 677972013 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 251679590 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 208 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 216005 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15651 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 107150 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 13325619 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8884381 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22210000 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2442758638 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 624415478 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 52152342 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 141231807 # number of nop insts executed -system.cpu.iew.exec_refs 827886992 # number of memory reference insts executed -system.cpu.iew.exec_branches 294323253 # Number of branches executed -system.cpu.iew.exec_stores 214720452 # Number of stores executed -system.cpu.iew.exec_rate 1.954368 # Inst execution rate -system.cpu.iew.wb_sent 2384887539 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2358079153 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1347433304 # num instructions producing a value -system.cpu.iew.wb_consumers 1703552370 # num instructions consuming a value +system.cpu.iew.exec_nop 142658665 # number of nop insts executed +system.cpu.iew.exec_refs 839717432 # number of memory reference insts executed +system.cpu.iew.exec_branches 299305457 # Number of branches executed +system.cpu.iew.exec_stores 215301954 # Number of stores executed +system.cpu.iew.exec_rate 1.988190 # Inst execution rate +system.cpu.iew.wb_sent 2421432535 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2392692642 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1370537618 # num instructions producing a value +system.cpu.iew.wb_consumers 1736169101 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.916228 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.790955 # average fanout of values written-back +system.cpu.iew.wb_rate 1.947440 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.789403 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitCommittedOps 1819780126 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 736139047 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 782630603 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 19443221 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1119336917 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.625766 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.487685 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 18986848 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1112602008 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.635607 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.507788 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 586822597 52.43% 52.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 186310200 16.64% 69.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95274520 8.51% 77.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53747896 4.80% 82.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 37177452 3.32% 85.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26985316 2.41% 88.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21737766 1.94% 90.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22635146 2.02% 92.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 88646024 7.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 589258835 52.96% 52.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 179628091 16.14% 69.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 90469983 8.13% 77.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53793341 4.83% 82.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36407733 3.27% 85.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27937238 2.51% 87.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22627047 2.03% 89.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23085278 2.07% 91.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 89394462 8.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1119336917 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1112602008 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -305,64 +305,64 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 88646024 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 89394462 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3500830866 # The number of ROB reads -system.cpu.rob.rob_writes 5217723058 # The number of ROB writes -system.cpu.timesIdled 398057 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5523098 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3539839075 # The number of ROB reads +system.cpu.rob.rob_writes 5315403238 # The number of ROB writes +system.cpu.timesIdled 405378 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5573944 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.708844 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.708844 # CPI: Total CPI of All Threads -system.cpu.ipc 1.410748 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.410748 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3237009112 # number of integer regfile reads -system.cpu.int_regfile_writes 1887111006 # number of integer regfile writes -system.cpu.fp_regfile_reads 12550 # number of floating regfile reads -system.cpu.fp_regfile_writes 508 # number of floating regfile writes +system.cpu.cpi 0.707721 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.707721 # CPI: Total CPI of All Threads +system.cpu.ipc 1.412986 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.412986 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3284485483 # number of integer regfile reads +system.cpu.int_regfile_writes 1919152187 # number of integer regfile writes +system.cpu.fp_regfile_reads 52475 # number of floating regfile reads +system.cpu.fp_regfile_writes 577 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 746.155324 # Cycle average of tags in use -system.cpu.icache.total_refs 385399748 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 942 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 409129.244161 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 800.240430 # Cycle average of tags in use +system.cpu.icache.total_refs 401791975 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 981 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 409573.878695 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 746.155324 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.364334 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.364334 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 385399748 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 385399748 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 385399748 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 385399748 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 385399748 # number of overall hits -system.cpu.icache.overall_hits::total 385399748 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1348 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1348 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1348 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1348 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1348 # number of overall misses -system.cpu.icache.overall_misses::total 1348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 47398000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 47398000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 47398000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 47398000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 47398000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 47398000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 385401096 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 385401096 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 385401096 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 385401096 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 385401096 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 385401096 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # 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average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20285.420171 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20285.420171 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 118562765 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2148382500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 37554 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65117 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3157.127470 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 32992.651688 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3077535 # number of writebacks -system.cpu.dcache.writebacks::total 3077535 # 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number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3083289 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883743 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1883743 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 981 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9180725 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9181706 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 981 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9180725 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9181706 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250026 # 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average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34347.664544 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34379.387329 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34347.664544 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34379.387329 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 17570000 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.294753 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34371.049949 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34338.518024 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34465.947843 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34371.049949 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34380.041027 # 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number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2703439 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2704381 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29342500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56708410500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56737753000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 27632234500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 27632234500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29342500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 84340645000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 84369987500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29342500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 84340645000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 84369987500 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1172197 # number of writebacks +system.cpu.l2cache.writebacks::total 1172197 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 981 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1824281 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1825262 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 881765 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 881765 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 981 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2706046 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2707027 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 981 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2706046 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2707027 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 30568000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56848109000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56878677000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 27575743000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 27575743000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30568000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 84423852000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 84454420000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30568000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 84423852000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 84454420000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250026 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.468704 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250005 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.468092 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295009 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.294753 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295009 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31149.150743 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31160.008187 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31274.847232 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31149.150743 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31197.539504 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31149.150743 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31197.539504 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.294753 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31160.040775 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31161.925712 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31273.347207 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31160.040775 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31198.232403 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31160.040775 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31198.232403 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 4a2c04206..8fb7001b0 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:28:08 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:51:32 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 483300356500 because target called exit() +Exiting @ tick 464073050000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 1d3623ac5..1790c7443 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.483300 # Number of seconds simulated -sim_ticks 483300356500 # Number of ticks simulated -final_tick 483300356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.464073 # Number of seconds simulated +sim_ticks 464073050000 # Number of ticks simulated +final_tick 464073050000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175200 # Simulator instruction rate (inst/s) -host_op_rate 195449 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54820940 # Simulator tick rate (ticks/s) -host_mem_usage 223460 # Number of bytes of host memory used -host_seconds 8815.98 # Real time elapsed on the host -sim_insts 1544563036 # Number of instructions simulated -sim_ops 1723073849 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 188191232 # Number of bytes read from this memory -system.physmem.bytes_inst_read 45952 # Number of instructions bytes read from this memory -system.physmem.bytes_written 77928320 # Number of bytes written to this memory -system.physmem.num_reads 2940488 # Number of read requests responded to by this memory -system.physmem.num_writes 1217630 # Number of write requests responded to by this memory +host_inst_rate 176271 # Simulator instruction rate (inst/s) +host_op_rate 196643 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52961695 # Simulator tick rate (ticks/s) +host_mem_usage 223676 # Number of bytes of host memory used +host_seconds 8762.43 # Real time elapsed on the host +sim_insts 1544563056 # Number of instructions simulated +sim_ops 1723073869 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 189754368 # Number of bytes read from this memory +system.physmem.bytes_inst_read 48448 # Number of instructions bytes read from this memory +system.physmem.bytes_written 78230272 # Number of bytes written to this memory +system.physmem.num_reads 2964912 # Number of read requests responded to by this memory +system.physmem.num_writes 1222348 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 389387737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 95080 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 161242008 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 550629745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 408889006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 104397 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 168573185 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 577462190 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,316 +64,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 966600714 # number of cpu cycles simulated +system.cpu.numCycles 928146101 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 298802813 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 243899992 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18315213 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 264194846 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 238628617 # Number of BTB hits +system.cpu.BPredUnit.lookups 300566019 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 246342426 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16106991 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 172736235 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 156347078 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 17678661 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 3338 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 296004888 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2174228266 # Number of instructions fetch has processed -system.cpu.fetch.Branches 298802813 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 256307278 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 484507329 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 86919023 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 107617273 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 140 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 285078339 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5300000 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 956319158 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.521362 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.026261 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 18335765 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 410 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 292802110 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2158556881 # Number of instructions fetch has processed +system.cpu.fetch.Branches 300566019 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 174682843 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 429264774 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83785432 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 129176492 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 309 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 283792946 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5380579 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 918501449 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.613879 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.238743 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 471811881 49.34% 49.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 35281645 3.69% 53.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 65131283 6.81% 59.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 66854544 6.99% 66.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 46816923 4.90% 71.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 59777101 6.25% 77.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 54237422 5.67% 83.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 17725648 1.85% 85.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 138682711 14.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 489236723 53.26% 53.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23024875 2.51% 55.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38786234 4.22% 59.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 47824320 5.21% 65.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 40756189 4.44% 69.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46964078 5.11% 74.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39095628 4.26% 79.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18144974 1.98% 80.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174668428 19.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 956319158 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.309127 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.249355 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 322991638 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 92138952 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 459388324 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13611363 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 68188881 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46868404 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 664 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2351885426 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2233 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 68188881 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 343108382 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46584354 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 25758 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 451644595 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46767188 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2295012184 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19840 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2699078 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 37731214 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2263685405 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10601312044 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10601310861 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1183 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706319951 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 557365454 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 9613 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 9609 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 98574159 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 618665433 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 221947140 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 73974093 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 60832432 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2187079584 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2062 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018219576 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3314512 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 457863024 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1047846495 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1559 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 956319158 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.110404 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.840875 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 918501449 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.323835 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.325665 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 322112975 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 109206216 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 403275742 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16649458 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 67257058 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46176709 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 759 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2347040926 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2511 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 67257058 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 343744693 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50775772 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 22198 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 397120131 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 59581597 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2290149919 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 23251 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4667919 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 46275027 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2264746735 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10570831770 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10570827064 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4706 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706319983 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 558426752 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5769 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5766 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 136911238 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624866711 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 218769389 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86004799 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 66542105 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2190647855 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1856 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2016093744 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4890618 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 462875235 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1075025866 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1349 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 918501449 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.194982 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.923350 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 261846751 27.38% 27.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 150992981 15.79% 43.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 168342829 17.60% 60.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 136328017 14.26% 75.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 124939866 13.06% 88.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73493141 7.69% 95.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 29213551 3.05% 98.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10245765 1.07% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 916257 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 251234212 27.35% 27.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 138874484 15.12% 42.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158306173 17.24% 59.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 116338081 12.67% 72.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 125703968 13.69% 86.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 75541719 8.22% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 39131512 4.26% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10691268 1.16% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2680032 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 956319158 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 918501449 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 899945 3.67% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 187 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19005921 77.47% 81.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4627423 18.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 823704 3.29% 3.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4653 0.02% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18995164 75.78% 79.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5243478 20.92% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1238740250 61.38% 61.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1017622 0.05% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 6 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 583895352 28.93% 90.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194566336 9.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1234318257 61.22% 61.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 931291 0.05% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 86 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 36 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 19 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587032832 29.12% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193811220 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018219576 # Type of FU issued -system.cpu.iq.rate 2.087956 # Inst issue rate -system.cpu.iq.fu_busy_cnt 24533476 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012156 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5020606045 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2645122896 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1958251270 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 253 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 238 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 108 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2042752922 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 130 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 55694024 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2016093744 # Type of FU issued +system.cpu.iq.rate 2.172173 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25066999 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012433 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4980646050 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2653710289 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1958144552 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 504 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 870 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 197 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2041160488 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 255 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63652463 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 132738662 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 211257 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 180594 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 47100094 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138939936 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 281971 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 189096 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 43922339 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 451914 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 450534 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 68188881 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22161421 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1213363 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2187099355 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7278228 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 618665433 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 221947140 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1999 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219629 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 61218 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 180594 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 18897487 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1819209 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 20716696 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1985947715 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 570245268 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 32271861 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 67257058 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23170910 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1317099 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2190657684 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 5590225 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624866711 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 218769389 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1789 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 207758 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 50528 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 189096 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8640354 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10202609 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18842963 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1986590916 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 572448085 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29502828 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17709 # number of nop insts executed -system.cpu.iew.exec_refs 761448250 # number of memory reference insts executed -system.cpu.iew.exec_branches 238637230 # Number of branches executed -system.cpu.iew.exec_stores 191202982 # Number of stores executed -system.cpu.iew.exec_rate 2.054569 # Inst execution rate -system.cpu.iew.wb_sent 1967185295 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1958251378 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1288041557 # num instructions producing a value -system.cpu.iew.wb_consumers 2036752533 # num instructions consuming a value +system.cpu.iew.exec_nop 7973 # number of nop insts executed +system.cpu.iew.exec_refs 763288309 # number of memory reference insts executed +system.cpu.iew.exec_branches 238204396 # Number of branches executed +system.cpu.iew.exec_stores 190840224 # Number of stores executed +system.cpu.iew.exec_rate 2.140386 # Inst execution rate +system.cpu.iew.wb_sent 1967133110 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1958144749 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296172102 # num instructions producing a value +system.cpu.iew.wb_consumers 2068722659 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.025916 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.632400 # average fanout of values written-back +system.cpu.iew.wb_rate 2.109738 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626557 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1544563054 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1723073867 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 464107908 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 503 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 18315306 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 888130278 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.940114 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.672278 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1544563074 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1723073887 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 467651163 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 507 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 16106465 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 851244392 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.024182 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.756273 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 382955223 43.12% 43.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 200739073 22.60% 65.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 81923550 9.22% 74.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 38679338 4.36% 79.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19675426 2.22% 81.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30976281 3.49% 85.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22277703 2.51% 87.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12029119 1.35% 88.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98874565 11.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 363008407 42.64% 42.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192701589 22.64% 65.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73550522 8.64% 73.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35106838 4.12% 78.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18707332 2.20% 80.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30658705 3.60% 83.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19651115 2.31% 86.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10957875 1.29% 87.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106902009 12.56% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 888130278 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563054 # Number of instructions committed -system.cpu.commit.committedOps 1723073867 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 851244392 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563074 # Number of instructions committed +system.cpu.commit.committedOps 1723073887 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773817 # Number of memory references committed -system.cpu.commit.loads 485926771 # Number of loads committed +system.cpu.commit.refs 660773825 # Number of memory references committed +system.cpu.commit.loads 485926775 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462365 # Number of branches committed +system.cpu.commit.branches 213462369 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941853 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941869 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 98874565 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106902009 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2976436889 # The number of ROB reads -system.cpu.rob.rob_writes 4442782654 # The number of ROB writes -system.cpu.timesIdled 920078 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10281556 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563036 # Number of Instructions Simulated -system.cpu.committedOps 1723073849 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563036 # Number of Instructions Simulated -system.cpu.cpi 0.625809 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.625809 # CPI: Total CPI of All Threads -system.cpu.ipc 1.597933 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.597933 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9941434858 # number of integer regfile reads -system.cpu.int_regfile_writes 1939754373 # number of integer regfile writes -system.cpu.fp_regfile_reads 96 # number of floating regfile reads -system.cpu.fp_regfile_writes 31 # number of floating regfile writes -system.cpu.misc_regfile_reads 2912823996 # number of misc regfile reads -system.cpu.misc_regfile_writes 126 # number of misc regfile writes -system.cpu.icache.replacements 10 # number of replacements -system.cpu.icache.tagsinuse 609.966952 # Cycle average of tags in use -system.cpu.icache.total_refs 285077321 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 746 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 382141.180965 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 2935066834 # The number of ROB reads +system.cpu.rob.rob_writes 4448881416 # The number of ROB writes +system.cpu.timesIdled 899412 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 9644652 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563056 # Number of Instructions Simulated +system.cpu.committedOps 1723073869 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563056 # Number of Instructions Simulated +system.cpu.cpi 0.600912 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.600912 # CPI: Total CPI of All Threads +system.cpu.ipc 1.664138 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.664138 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9951907737 # number of integer regfile reads +system.cpu.int_regfile_writes 1938294940 # number of integer regfile writes +system.cpu.fp_regfile_reads 210 # number of floating regfile reads +system.cpu.fp_regfile_writes 230 # number of floating regfile writes +system.cpu.misc_regfile_reads 2898206993 # number of misc regfile reads +system.cpu.misc_regfile_writes 134 # number of misc regfile writes +system.cpu.icache.replacements 22 # number of replacements +system.cpu.icache.tagsinuse 634.912102 # Cycle average of tags in use +system.cpu.icache.total_refs 283791788 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 786 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 361058.254453 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 609.966952 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.297835 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.297835 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 285077321 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 285077321 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 285077321 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 285077321 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 285077321 # number of overall hits -system.cpu.icache.overall_hits::total 285077321 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1018 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1018 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1018 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1018 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1018 # number of overall misses -system.cpu.icache.overall_misses::total 1018 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 35270500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 35270500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 35270500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 35270500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 35270500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 35270500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 285078339 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 285078339 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 285078339 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 285078339 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 285078339 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 285078339 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 634.912102 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.310016 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.310016 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 283791788 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 283791788 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 283791788 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 283791788 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 283791788 # number of overall hits +system.cpu.icache.overall_hits::total 283791788 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1158 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1158 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1158 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1158 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1158 # number of overall misses +system.cpu.icache.overall_misses::total 1158 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 38624000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 38624000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 38624000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 38624000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 38624000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 38624000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 283792946 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 283792946 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 283792946 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 283792946 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 283792946 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 283792946 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34646.856582 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34646.856582 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34646.856582 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33354.058722 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33354.058722 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33354.058722 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,269 +382,269 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 272 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 272 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 272 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 272 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 272 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 272 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 746 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 746 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 746 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 746 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 746 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 746 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25653000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25653000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25653000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25653000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25653000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25653000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 372 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 372 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 372 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 372 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 372 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 372 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 786 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 786 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 786 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 786 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 786 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 786 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27049500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27049500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27049500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27049500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27049500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27049500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34387.399464 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34387.399464 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34387.399464 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34414.122137 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34414.122137 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34414.122137 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9570609 # number of replacements -system.cpu.dcache.tagsinuse 4087.729265 # Cycle average of tags in use -system.cpu.dcache.total_refs 666885051 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9574705 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 69.650715 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3484295000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.729265 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997981 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997981 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 499489564 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 499489564 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167395365 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167395365 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 60 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 60 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 62 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 62 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 666884929 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 666884929 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 666884929 # number of overall hits -system.cpu.dcache.overall_hits::total 666884929 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10445560 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10445560 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5190682 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5190682 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 15636242 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 15636242 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 15636242 # number of overall misses -system.cpu.dcache.overall_misses::total 15636242 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 184478558500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 184478558500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 128511717246 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 128511717246 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 312990275746 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 312990275746 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 312990275746 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 312990275746 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 509935124 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 509935124 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 9618384 # number of replacements +system.cpu.dcache.tagsinuse 4087.732309 # Cycle average of tags in use +system.cpu.dcache.total_refs 660741585 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9622480 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.666454 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3347848000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.732309 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997982 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997982 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 493363105 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 493363105 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167378321 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167378321 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 93 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 93 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 66 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 66 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 660741426 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 660741426 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 660741426 # number of overall hits +system.cpu.dcache.overall_hits::total 660741426 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10695472 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10695472 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5207726 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5207726 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 15903198 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15903198 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15903198 # number of overall misses +system.cpu.dcache.overall_misses::total 15903198 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 189107739500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 189107739500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129597679387 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129597679387 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 148000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 148000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 318705418887 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 318705418887 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 318705418887 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 318705418887 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 504058577 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 504058577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 62 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 62 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 682521171 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 682521171 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 682521171 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 682521171 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020484 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030076 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047619 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.022910 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.022910 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17660.954367 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24758.156490 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20016.975674 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20016.975674 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 266779202 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 225500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 90534 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2946.729428 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16107.142857 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 66 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 66 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 676644624 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 676644624 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 676644624 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 676644624 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021219 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030175 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.041237 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023503 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023503 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17681.102760 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24885.656309 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20040.335214 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20040.335214 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 270494777 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 161000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 91798 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2946.630395 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16100 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3128454 # number of writebacks -system.cpu.dcache.writebacks::total 3128454 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2763491 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2763491 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3298046 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3298046 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6061537 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6061537 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6061537 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6061537 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7682069 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7682069 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1892636 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1892636 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9574705 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9574705 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9574705 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9574705 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 92052400500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 92052400500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45263240996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 45263240996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137315641496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 137315641496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 137315641496 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 137315641496 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015065 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010966 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014028 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11982.761480 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23915.449667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14341.501017 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14341.501017 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 3133951 # number of writebacks +system.cpu.dcache.writebacks::total 3133951 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2966989 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2966989 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3313729 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3313729 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6280718 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6280718 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6280718 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6280718 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7728483 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7728483 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893997 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893997 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9622480 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9622480 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9622480 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9622480 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 93034311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 93034311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45389589120 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 45389589120 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138423900120 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 138423900120 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138423900120 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 138423900120 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015333 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12037.848954 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23964.974137 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14385.470286 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14385.470286 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2928111 # number of replacements -system.cpu.l2cache.tagsinuse 26779.513847 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7850665 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2955434 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.656349 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 102043879500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 10799.372069 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 11.094827 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15969.046951 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.329571 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000339 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.487337 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.817246 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 5654817 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5654844 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3128454 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3128454 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 980108 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 980108 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 6634925 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6634952 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 6634925 # number of overall hits -system.cpu.l2cache.overall_hits::total 6634952 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 719 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 2027251 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2027970 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 912529 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 912529 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 719 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2939780 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2940499 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 719 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2939780 # number of overall misses -system.cpu.l2cache.overall_misses::total 2940499 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24699000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 69597988500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 69622687500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31651212500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 31651212500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24699000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 101249201000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 101273900000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24699000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 101249201000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 101273900000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 746 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7682068 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7682814 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3128454 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3128454 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1892637 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1892637 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 746 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9574705 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9575451 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 746 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9574705 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9575451 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963807 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.263894 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.482147 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963807 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.307036 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963807 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.307036 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34351.877608 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34331.214290 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34685.157951 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34351.877608 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34441.080965 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34351.877608 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34441.080965 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 56425000 # number of cycles access was blocked +system.cpu.l2cache.replacements 2952443 # number of replacements +system.cpu.l2cache.tagsinuse 26872.767236 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7878289 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2979766 # 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number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3133951 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893998 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1893998 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 786 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9622480 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9623266 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 786 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9622480 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9623266 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964377 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.265060 # 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number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 718 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2027241 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2027959 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 912529 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 912529 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 718 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2939770 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2940488 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 718 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2939770 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2940488 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22382500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63220880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63243262500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28812389000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28812389000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22382500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92033269000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 92055651500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22382500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92033269000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 92055651500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962466 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.263893 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.482147 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962466 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307035 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962466 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307035 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31173.398329 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31185.675507 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31574.217367 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31173.398329 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31306.282124 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31173.398329 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31306.282124 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 757 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2048504 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2049261 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 915651 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 915651 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 757 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2964155 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2964912 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 757 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2964155 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2964912 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23603500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63886529000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63910132500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28922104500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28922104500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23603500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92808633500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 92832237000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23603500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92808633500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 92832237000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.963104 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265059 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483449 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963104 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308045 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963104 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308045 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31180.317041 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31186.919332 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31586.384441 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31180.317041 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31310.317274 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31180.317041 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31310.317274 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout index ddac6bec8..6032e061b 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:36:18 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:58:42 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 41833966000 because target called exit() +122 123 124 Exiting @ tick 42005374000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 7525585e3..2e73aee88 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041834 # Number of seconds simulated -sim_ticks 41833966000 # Number of ticks simulated -final_tick 41833966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.042005 # Number of seconds simulated +sim_ticks 42005374000 # Number of ticks simulated +final_tick 42005374000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151560 # Simulator instruction rate (inst/s) -host_op_rate 151560 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68989742 # Simulator tick rate (ticks/s) +host_inst_rate 147839 # Simulator instruction rate (inst/s) +host_op_rate 147839 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67571644 # Simulator tick rate (ticks/s) host_mem_usage 213560 # Number of bytes of host memory used -host_seconds 606.38 # Real time elapsed on the host +host_seconds 621.64 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read 316032 # Number of bytes read from this memory @@ -17,9 +17,9 @@ system.physmem.bytes_written 0 # Nu system.physmem.num_reads 4938 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 7554436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 4274421 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 7554436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 7523609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 4256979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 7523609 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -36,10 +36,10 @@ system.cpu.dtb.data_hits 26498119 # DT system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 26498152 # DTB accesses -system.cpu.itb.fetch_hits 9991202 # ITB hits +system.cpu.itb.fetch_hits 10037351 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 9991251 # ITB accesses +system.cpu.itb.fetch_accesses 10037400 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,16 +53,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83667933 # number of cpu cycles simulated +system.cpu.numCycles 84010749 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83292959 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 83632403 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10907 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7700653 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75967280 # Number of cycles cpu stages are processed. -system.cpu.activity 90.796172 # Percentage of cycles cpu is active +system.cpu.timesIdled 11097 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7735993 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 76274756 # Number of cycles cpu stages are processed. +system.cpu.activity 90.791663 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -74,158 +74,158 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.910393 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.914124 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.910393 # CPI: Total CPI of All Threads -system.cpu.ipc 1.098426 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.914124 # CPI: Total CPI of All Threads +system.cpu.ipc 1.093944 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.098426 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 13542330 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 9941405 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4410938 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 8655858 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 4135478 # Number of BTB hits +system.cpu.ipc_total 1.093944 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 13563923 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 9779691 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4496836 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 7950423 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 3848158 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 47.776639 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 6269254 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7273076 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73609025 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 123 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 48.401928 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 5997418 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7566505 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73742077 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136184497 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206079 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136317549 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206798 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8057967 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38654467 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26652325 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3861647 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 548433 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4410080 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5830622 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 43.064235 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57347630 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 458254 # Number of Multipy Operations Executed +system.cpu.regfile_manager.floatRegFileAccesses 8058686 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 38530251 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26765541 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3521133 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 974845 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4495978 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5744724 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 43.903025 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57471384 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 458266 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 27446781 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 56221152 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 67.195579 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34307675 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49360258 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.995431 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33744588 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49923345 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.668434 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65638077 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18029856 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.549303 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29755825 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53912108 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.435807 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 7551 # number of replacements -system.cpu.icache.tagsinuse 1491.782957 # Cycle average of tags in use -system.cpu.icache.total_refs 9979713 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9436 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1057.621132 # Average number of references to valid blocks. +system.cpu.stage0.idleCycles 27790213 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 56220536 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.920646 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34560671 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49450078 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.861608 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34032650 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49978099 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.490124 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65981194 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18029555 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.461010 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 30068425 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53942324 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.208836 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 8111 # number of replacements +system.cpu.icache.tagsinuse 1492.322334 # Cycle average of tags in use +system.cpu.icache.total_refs 10025618 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 9996 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1002.962985 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1491.782957 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728410 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728410 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 9979713 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 9979713 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 9979713 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 9979713 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 9979713 # number of overall hits -system.cpu.icache.overall_hits::total 9979713 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11486 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11486 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11486 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11486 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11486 # number of overall misses -system.cpu.icache.overall_misses::total 11486 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 291407500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 291407500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 291407500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 291407500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 291407500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 291407500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9991199 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9991199 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9991199 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9991199 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9991199 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9991199 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001150 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001150 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001150 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25370.668640 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25370.668640 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25370.668640 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1492.322334 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728673 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728673 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10025618 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10025618 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10025618 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10025618 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10025618 # number of overall hits +system.cpu.icache.overall_hits::total 10025618 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11728 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11728 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11728 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11728 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11728 # number of overall misses +system.cpu.icache.overall_misses::total 11728 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 295393500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 295393500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 295393500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 295393500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 295393500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 295393500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 10037346 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 10037346 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 10037346 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 10037346 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 10037346 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 10037346 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001168 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001168 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001168 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25187.031037 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 69500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 97000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 17375 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 16166.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2050 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2050 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2050 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2050 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2050 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2050 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9436 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9436 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9436 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 9436 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 9436 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 9436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 222700000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 222700000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 222700000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 222700000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 222700000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 222700000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23601.102162 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23601.102162 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23601.102162 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1732 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1732 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1732 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1732 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1732 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1732 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9996 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 9996 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 9996 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 9996 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 9996 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 9996 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 228898000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 228898000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 228898000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 228898000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 228898000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 228898000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22898.959584 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.532122 # Cycle average of tags in use -system.cpu.dcache.total_refs 26491206 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.511431 # Cycle average of tags in use +system.cpu.dcache.total_refs 26491208 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11916.871795 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11916.872695 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.532122 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.351937 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.351937 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995645 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995645 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6495561 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6495561 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26491206 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26491206 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26491206 # number of overall hits -system.cpu.dcache.overall_hits::total 26491206 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 553 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 553 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5542 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5542 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6095 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6095 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6095 # number of overall misses -system.cpu.dcache.overall_misses::total 6095 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28393500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28393500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 303801000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 303801000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 332194500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 332194500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 332194500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 332194500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 1441.511431 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.351932 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.351932 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995646 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995646 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6495562 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6495562 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26491208 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26491208 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26491208 # number of overall hits +system.cpu.dcache.overall_hits::total 26491208 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 552 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 552 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5541 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5541 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6093 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6093 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6093 # number of overall misses +system.cpu.dcache.overall_misses::total 6093 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28391500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28391500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 303790500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 303790500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 332182000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 332182000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 332182000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 332182000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -238,28 +238,28 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000852 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000230 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000230 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51344.484629 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54817.935763 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54502.789171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54502.789171 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51433.876812 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54825.933947 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 41047000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 41043500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 824 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 823 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49814.320388 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49870.595383 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3794 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3794 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3872 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3872 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3872 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3872 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3793 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3793 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3870 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3870 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3870 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3870 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -268,49 +268,49 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92997500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92997500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116210500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 116210500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116210500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 116210500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23216000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23216000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92995500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92995500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116211500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 116211500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116211500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 116211500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48869.473684 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53202.231121 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.428250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.428250 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48875.789474 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53201.086957 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2189.253602 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6704 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2189.730470 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7264 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.042657 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.213285 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.838059 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1820.375269 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.040274 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055553 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010713 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066811 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 6642 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 17.847253 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1820.879596 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.003621 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055569 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066825 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7202 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6695 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7255 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 6642 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 7202 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6721 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 6642 # number of overall hits +system.cpu.l2cache.demand_hits::total 7281 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7202 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits -system.cpu.l2cache.overall_hits::total 6721 # number of overall hits +system.cpu.l2cache.overall_hits::total 7281 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses @@ -322,44 +322,44 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 146193000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22134500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 168327500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90565000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 90565000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 146193000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 112699500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 258892500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 146193000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 112699500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 258892500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 9436 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 146177000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22139000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 168316000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90566000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 90566000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 146177000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112705000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 258882000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 146177000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112705000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 258882000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 9996 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 9911 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 10471 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 9996 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 11659 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9436 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 12219 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9996 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 11659 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.296100 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 12219 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279512 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.296100 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279512 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.296100 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279512 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52323.908375 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52451.421801 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52592.915215 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52323.908375 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52565.065299 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52323.908375 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52565.065299 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.181818 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52462.085308 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52593.495935 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,31 +379,31 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112072000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16981500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 129053500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69344000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69344000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112072000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86325500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 198397500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112072000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86325500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 198397500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112070000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16981000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 129051000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69345500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69345500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112070000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86326500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 198396500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112070000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86326500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 198396500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40111.667860 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40240.521327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40269.454123 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40111.667860 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40263.759328 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40111.667860 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40263.759328 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.952040 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40239.336493 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40270.325203 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index f5b2c31fd..58e98acc5 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:45:24 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 18:07:15 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 29167093500 because target called exit() +122 123 124 Exiting @ tick 23638033500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 221154573..8502942e2 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.029167 # Number of seconds simulated -sim_ticks 29167093500 # Number of ticks simulated -final_tick 29167093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023638 # Number of seconds simulated +sim_ticks 23638033500 # Number of ticks simulated +final_tick 23638033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 198361 # Simulator instruction rate (inst/s) -host_op_rate 198361 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68729352 # Simulator tick rate (ticks/s) +host_inst_rate 231314 # Simulator instruction rate (inst/s) +host_op_rate 231314 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64954124 # Simulator tick rate (ticks/s) host_mem_usage 214912 # Number of bytes of host memory used -host_seconds 424.38 # Real time elapsed on the host +host_seconds 363.92 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 332416 # Number of bytes read from this memory -system.physmem.bytes_inst_read 193856 # Number of instructions bytes read from this memory +system.physmem.bytes_read 336064 # Number of bytes read from this memory +system.physmem.bytes_inst_read 197952 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 5194 # Number of read requests responded to by this memory +system.physmem.num_reads 5251 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 11396953 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 6646394 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 11396953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 14217088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 8374301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 14217088 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 25236325 # DTB read hits -system.cpu.dtb.read_misses 540509 # DTB read misses +system.cpu.dtb.read_hits 23223377 # DTB read hits +system.cpu.dtb.read_misses 198479 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 25776834 # DTB read accesses -system.cpu.dtb.write_hits 7362909 # DTB write hits -system.cpu.dtb.write_misses 1032 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7363941 # DTB write accesses -system.cpu.dtb.data_hits 32599234 # DTB hits -system.cpu.dtb.data_misses 541541 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 33140775 # DTB accesses -system.cpu.itb.fetch_hits 18604047 # ITB hits -system.cpu.itb.fetch_misses 85 # ITB misses +system.cpu.dtb.read_accesses 23421856 # DTB read accesses +system.cpu.dtb.write_hits 7079825 # DTB write hits +system.cpu.dtb.write_misses 1403 # DTB write misses +system.cpu.dtb.write_acv 5 # DTB write access violations +system.cpu.dtb.write_accesses 7081228 # DTB write accesses +system.cpu.dtb.data_hits 30303202 # DTB hits +system.cpu.dtb.data_misses 199882 # DTB misses +system.cpu.dtb.data_acv 5 # DTB access violations +system.cpu.dtb.data_accesses 30503084 # DTB accesses +system.cpu.itb.fetch_hits 14943347 # ITB hits +system.cpu.itb.fetch_misses 91 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 18604132 # ITB accesses +system.cpu.itb.fetch_accesses 14943438 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,247 +53,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 58334188 # number of cpu cycles simulated +system.cpu.numCycles 47276068 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 18443606 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 13550904 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1909309 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15151906 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11744171 # Number of BTB hits +system.cpu.BPredUnit.lookups 15033034 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10893927 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 965097 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 8612659 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7067377 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1797123 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2508 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 19753130 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 155901269 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18443606 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13541294 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 28873870 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8029527 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3519156 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1819 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 18604047 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 633220 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 58241050 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.676828 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.252315 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1490279 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6040 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15621230 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 128217007 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15033034 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8557656 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22378884 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4633381 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5548401 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1854 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14943347 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 336798 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47185446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.717300 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.373013 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29367180 50.42% 50.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2937608 5.04% 55.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2015194 3.46% 58.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3338566 5.73% 64.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4094138 7.03% 71.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1423310 2.44% 74.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1755062 3.01% 77.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1585835 2.72% 79.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11724157 20.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24806562 52.57% 52.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2389979 5.07% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1207538 2.56% 60.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1775063 3.76% 63.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2802024 5.94% 69.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1169800 2.48% 72.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1228019 2.60% 74.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 790135 1.67% 76.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11016326 23.35% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 58241050 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316171 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.672554 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 21649179 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2708949 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 27144653 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 658698 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6079571 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2969190 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13806 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 150046107 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 43597 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6079571 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 23241789 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 566661 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6095 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 26202396 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2144538 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 144061667 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 244284 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1605069 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 105522995 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 186327738 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 175726328 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10601410 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 47185446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317984 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.712091 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17463925 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4249040 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20759249 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1090184 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3623048 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2545357 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12255 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 125130253 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31826 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3623048 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18629909 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 965094 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8920 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20661182 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3297293 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 122152175 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 401388 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2422623 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89685518 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 158620062 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 148881837 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9738225 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37095634 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 535 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 531 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6071657 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29750182 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9383371 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2457988 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 836885 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 120824169 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 510 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 104934850 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 288533 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 35688110 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 27652526 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 121 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 58241050 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.801733 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.850509 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 21258157 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1427 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1434 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8739521 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25557847 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8301356 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2609711 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 904973 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 106143007 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2358 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96975947 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 189226 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21491456 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16142477 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1969 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47185446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.055209 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.876136 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19806248 34.01% 34.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11039636 18.96% 52.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9348946 16.05% 69.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6752104 11.59% 80.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5521673 9.48% 90.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2974014 5.11% 95.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1775531 3.05% 98.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 852122 1.46% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 170776 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12454883 26.40% 26.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9420722 19.97% 46.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8458741 17.93% 64.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6315379 13.38% 77.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4948925 10.49% 88.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2846998 6.03% 94.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1728154 3.66% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 801160 1.70% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 210484 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 58241050 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47185446 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 161609 9.97% 9.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 218 0.01% 9.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 6469 0.40% 10.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 2295 0.14% 10.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 845619 52.17% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 527151 32.52% 95.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77634 4.79% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 186828 11.91% 11.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 238 0.02% 11.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7150 0.46% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5464 0.35% 12.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 842994 53.75% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 446294 28.45% 94.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79499 5.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 63561145 60.57% 60.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 485535 0.46% 61.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2794061 2.66% 63.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115045 0.11% 63.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2411045 2.30% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 308682 0.29% 66.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 763571 0.73% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 318 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 27006510 25.74% 92.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7488931 7.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58979048 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 480591 0.50% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2800978 2.89% 64.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115548 0.12% 64.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2385848 2.46% 66.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311419 0.32% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759609 0.78% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23970757 24.72% 92.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7171823 7.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 104934850 # Type of FU issued -system.cpu.iq.rate 1.798857 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1620995 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015448 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 254843963 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 146750024 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 92740043 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15176315 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9791044 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7062550 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 98540004 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8015834 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1319105 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96975947 # Type of FU issued +system.cpu.iq.rate 2.051269 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1568467 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016174 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 227768377 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 118855856 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87353688 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15126656 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8815414 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7066282 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90552040 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7992367 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1520027 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9753984 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 15279 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28494 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2882268 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5561649 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 19937 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34563 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1800253 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10177 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10514 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6079571 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 81043 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15363 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 132624218 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 876009 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29750182 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9383371 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 510 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 184 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28494 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1787084 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 342134 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2129218 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 102333218 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25777384 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2601632 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3623048 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 133924 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17201 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 116441723 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 394323 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25557847 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8301356 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2358 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2853 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 36 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34563 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 569788 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 508452 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1078240 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95678343 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23422851 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1297604 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 11799539 # number of nop insts executed -system.cpu.iew.exec_refs 33141424 # number of memory reference insts executed -system.cpu.iew.exec_branches 12916232 # Number of branches executed -system.cpu.iew.exec_stores 7364040 # Number of stores executed -system.cpu.iew.exec_rate 1.754258 # Inst execution rate -system.cpu.iew.wb_sent 101006568 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99802593 # cumulative count of insts written-back -system.cpu.iew.wb_producers 67789343 # num instructions producing a value -system.cpu.iew.wb_consumers 93484829 # num instructions consuming a value +system.cpu.iew.exec_nop 10296358 # number of nop insts executed +system.cpu.iew.exec_refs 30504278 # number of memory reference insts executed +system.cpu.iew.exec_branches 12076445 # Number of branches executed +system.cpu.iew.exec_stores 7081427 # Number of stores executed +system.cpu.iew.exec_rate 2.023822 # Inst execution rate +system.cpu.iew.wb_sent 94963988 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94419970 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64608180 # num instructions producing a value +system.cpu.iew.wb_consumers 89987821 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.710877 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.725137 # average fanout of values written-back +system.cpu.iew.wb_rate 1.997204 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717966 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitCommittedOps 91903055 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 40723267 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 24539814 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1895854 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 52161479 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.761895 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.510937 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 953116 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43562398 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.109688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.736301 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23655247 45.35% 45.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11195713 21.46% 66.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5070133 9.72% 76.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2810925 5.39% 81.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1675607 3.21% 85.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1392452 2.67% 87.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 795157 1.52% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 831289 1.59% 90.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4734956 9.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17041146 39.12% 39.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9957627 22.86% 61.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4507142 10.35% 72.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2283698 5.24% 77.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1617573 3.71% 81.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1122316 2.58% 83.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 722162 1.66% 85.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 820666 1.88% 87.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5490068 12.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 52161479 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43562398 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -304,64 +304,64 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4734956 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5490068 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 180051805 # The number of ROB reads -system.cpu.rob.rob_writes 271380444 # The number of ROB writes -system.cpu.timesIdled 2277 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 93138 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 154514159 # The number of ROB reads +system.cpu.rob.rob_writes 236533126 # The number of ROB writes +system.cpu.timesIdled 2183 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 90622 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.692972 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.692972 # CPI: Total CPI of All Threads -system.cpu.ipc 1.443060 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.443060 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 138495671 # number of integer regfile reads -system.cpu.int_regfile_writes 75435014 # number of integer regfile writes -system.cpu.fp_regfile_reads 6177236 # number of floating regfile reads -system.cpu.fp_regfile_writes 6044349 # number of floating regfile writes -system.cpu.misc_regfile_reads 715554 # number of misc regfile reads +system.cpu.cpi 0.561609 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.561609 # CPI: Total CPI of All Threads +system.cpu.ipc 1.780599 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.780599 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129442497 # number of integer regfile reads +system.cpu.int_regfile_writes 70765525 # number of integer regfile writes +system.cpu.fp_regfile_reads 6190739 # number of floating regfile reads +system.cpu.fp_regfile_writes 6047859 # number of floating regfile writes +system.cpu.misc_regfile_reads 714278 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8695 # number of replacements -system.cpu.icache.tagsinuse 1593.002324 # Cycle average of tags in use -system.cpu.icache.total_refs 18592194 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10628 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1749.359616 # Average number of references to valid blocks. +system.cpu.icache.replacements 10359 # number of replacements +system.cpu.icache.tagsinuse 1607.190165 # Cycle average of tags in use +system.cpu.icache.total_refs 14929668 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12297 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1214.090266 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1593.002324 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.777833 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.777833 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 18592194 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 18592194 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 18592194 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 18592194 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 18592194 # number of overall hits -system.cpu.icache.overall_hits::total 18592194 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11853 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11853 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11853 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11853 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11853 # number of overall misses -system.cpu.icache.overall_misses::total 11853 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 188036500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 188036500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 188036500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 188036500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 188036500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 188036500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 18604047 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 18604047 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 18604047 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 18604047 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 18604047 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 18604047 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000637 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000637 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000637 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15864.042858 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15864.042858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15864.042858 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1607.190165 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.784761 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.784761 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14929668 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14929668 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14929668 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14929668 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14929668 # number of overall hits +system.cpu.icache.overall_hits::total 14929668 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13679 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13679 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13679 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13679 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13679 # number of overall misses +system.cpu.icache.overall_misses::total 13679 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 203969000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 203969000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 203969000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 203969000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 203969000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 203969000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14943347 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14943347 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14943347 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14943347 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14943347 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14943347 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000915 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000915 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000915 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14911.104613 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14911.104613 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14911.104613 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -370,258 +370,258 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1225 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1225 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1225 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1225 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1225 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1225 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10628 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10628 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10628 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10628 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10628 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10628 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 124769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 124769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124769000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 124769000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11739.649981 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11739.649981 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11739.649981 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1382 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1382 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1382 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1382 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1382 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1382 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12297 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12297 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12297 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12297 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12297 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12297 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130905500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 130905500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130905500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 130905500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130905500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 130905500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10645.319997 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10645.319997 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10645.319997 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 159 # number of replacements -system.cpu.dcache.tagsinuse 1462.507461 # Cycle average of tags in use -system.cpu.dcache.total_refs 30399158 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2246 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13534.798753 # Average number of references to valid blocks. +system.cpu.dcache.replacements 158 # number of replacements +system.cpu.dcache.tagsinuse 1455.343539 # Cycle average of tags in use +system.cpu.dcache.total_refs 28184934 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2238 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12593.804290 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1462.507461 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.357057 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.357057 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23906051 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23906051 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493055 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493055 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 30399106 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 30399106 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 30399106 # number of overall hits -system.cpu.dcache.overall_hits::total 30399106 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 938 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 938 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8048 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8048 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1455.343539 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.355308 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.355308 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21691339 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21691339 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493048 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493048 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 547 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 547 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28184387 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28184387 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28184387 # number of overall hits +system.cpu.dcache.overall_hits::total 28184387 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 946 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 946 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8055 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8055 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 8986 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8986 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8986 # number of overall misses -system.cpu.dcache.overall_misses::total 8986 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28163500 # 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number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 38000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 318052500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 318052500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 318052500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 318052500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23906989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23906989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 317737000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 317737000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 317737000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 317737000 # 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miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001238 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018868 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000296 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000296 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30025.053305 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36020.004970 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 548 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 548 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28193388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28193388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28193388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28193388 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001239 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001825 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000319 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000319 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30077.695560 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35913.531968 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35394.224349 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35394.224349 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35300.188868 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35300.188868 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 424 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6317 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6317 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6741 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6741 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6741 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6741 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 514 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 435 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 435 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6329 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6329 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6764 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6764 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6764 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6764 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 511 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 511 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1726 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1726 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2245 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2245 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2245 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2245 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16469500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16469500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61655000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 61655000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2237 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2237 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2237 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2237 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16444500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16444500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61474000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61474000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78124500 # 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number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2246 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 12874 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 10628 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2246 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 12874 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.285002 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.891262 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985557 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.285002 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.963936 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.285002 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.963936 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34334.103665 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34410.675381 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34726.846424 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34334.103665 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34659.815242 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34334.103665 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34659.815242 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1726 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1726 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 12297 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2238 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 14535 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12297 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2238 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 14535 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.251525 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894531 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984936 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.251525 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964254 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.251525 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964254 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34320.562561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34414.847162 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34718.823529 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.562561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34654.309546 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.562561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34654.309546 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3029 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 459 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3488 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3029 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5194 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3029 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5194 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 94144500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14345500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 108490000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53828000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53828000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 94144500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68173500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 162318000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 94144500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68173500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 162318000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.891262 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985557 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31081.049851 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31253.812636 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31552.168816 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31081.049851 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31488.914550 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31081.049851 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31488.914550 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3093 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3551 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1700 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1700 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3093 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2158 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5251 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3093 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2158 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5251 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 96110500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14313000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 110423500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53634000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53634000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96110500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67947000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 164057500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96110500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67947000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 164057500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894531 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984936 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964254 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964254 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31073.553185 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31251.091703 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31549.411765 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31073.553185 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31486.098239 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31073.553185 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31486.098239 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index d10088405..8c858c201 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:37:09 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:58:01 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing +Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sav +Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -21,4 +23,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 105850842000 because target called exit() +122 123 124 Exiting @ tick 88632152500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 98dddaff0..64cc4b80a 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.105851 # Number of seconds simulated -sim_ticks 105850842000 # Number of ticks simulated -final_tick 105850842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.088632 # Number of seconds simulated +sim_ticks 88632152500 # Number of ticks simulated +final_tick 88632152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122767 # Simulator instruction rate (inst/s) -host_op_rate 134419 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75414821 # Simulator tick rate (ticks/s) -host_mem_usage 227032 # Number of bytes of host memory used -host_seconds 1403.58 # Real time elapsed on the host -sim_insts 172314144 # Number of instructions simulated -sim_ops 188667627 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 239936 # Number of bytes read from this memory -system.physmem.bytes_inst_read 128320 # Number of instructions bytes read from this memory +host_inst_rate 134694 # Simulator instruction rate (inst/s) +host_op_rate 147478 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69281557 # Simulator tick rate (ticks/s) +host_mem_usage 227272 # Number of bytes of host memory used +host_seconds 1279.30 # Real time elapsed on the host +sim_insts 172315139 # Number of instructions simulated +sim_ops 188668622 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 244352 # Number of bytes read from this memory +system.physmem.bytes_inst_read 132032 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 3749 # Number of read requests responded to by this memory +system.physmem.num_reads 3818 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2266737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1212272 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2266737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2756923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1489663 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2756923 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -63,315 +63,315 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 211701685 # number of cpu cycles simulated +system.cpu.numCycles 177264306 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 102100879 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80677195 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 9930193 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 84233443 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79245701 # Number of BTB hits +system.cpu.BPredUnit.lookups 96525090 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 74749964 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6668938 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 46796658 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 44215963 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4698090 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 111402 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 44542965 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 416708415 # Number of instructions fetch has processed -system.cpu.fetch.Branches 102100879 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83943791 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 108793327 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 33207424 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 35058719 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4389679 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 114813 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 39966229 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 381133369 # Number of instructions fetch has processed +system.cpu.fetch.Branches 96525090 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48605642 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80754991 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27412697 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 35762422 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9389 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 40619675 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2204435 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 211643202 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.135620 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.646860 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 36758976 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1679336 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 177207232 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.350259 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.058598 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 103052143 48.69% 48.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4614041 2.18% 50.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 32953123 15.57% 66.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 18235328 8.62% 75.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 9171108 4.33% 79.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 12530200 5.92% 85.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 8476968 4.01% 89.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4316297 2.04% 91.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 18293994 8.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 96615622 54.52% 54.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5430463 3.06% 57.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10300720 5.81% 63.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10325695 5.83% 69.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8756862 4.94% 74.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6889395 3.89% 78.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6237128 3.52% 81.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8634116 4.87% 86.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24017231 13.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 211643202 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.482287 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.968376 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 53231519 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 33609414 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 100494512 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1217161 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23090596 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14181130 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 166488 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 422617374 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 695976 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 23090596 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 62189594 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 455687 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28663702 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 92677243 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4566380 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 388527700 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 20997 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2241803 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 666137382 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1656361753 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1638646831 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17714922 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298061936 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 368075446 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2723266 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2675408 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 23504222 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 46900559 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16903337 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3858030 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2525525 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 332647611 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2225423 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 261830951 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 960204 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 143464205 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 342029155 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 589405 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 211643202 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.237134 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.489338 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 177207232 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.544526 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.150085 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 46183847 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 34297054 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74780894 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1386206 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20559231 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14846637 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 165269 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392589126 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 748420 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20559231 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 52356007 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 443712 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 29007637 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 69958724 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4881921 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 367191514 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 92621 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2515930 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 627979317 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1558602975 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1541578337 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17024638 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298063528 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 329915789 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2303042 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2294526 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 21773052 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 41898813 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 15562062 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3360389 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2124393 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 324040554 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2103109 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 248819756 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 576048 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 136002156 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 346792965 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 466892 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 177207232 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.404117 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.633607 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 97826086 46.22% 46.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 37864076 17.89% 64.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34104807 16.11% 80.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 22781361 10.76% 90.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11447248 5.41% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4765675 2.25% 98.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2321089 1.10% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 393603 0.19% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 139257 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 78492090 44.29% 44.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 28577659 16.13% 60.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 26660356 15.04% 75.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 21359445 12.05% 87.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12490578 7.05% 94.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5763951 3.25% 97.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3149996 1.78% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 544249 0.31% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 168908 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 211643202 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 177207232 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 397917 18.24% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5522 0.25% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 50 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 46 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1324685 60.73% 79.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 453082 20.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 627952 27.03% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5535 0.24% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 48 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 1 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1223626 52.68% 79.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 465789 20.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 204918446 78.26% 78.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 928788 0.35% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33078 0.01% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 166576 0.06% 78.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 257183 0.10% 78.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76398 0.03% 78.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467924 0.18% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 207596 0.08% 79.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71825 0.03% 79.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 325 0.00% 79.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 40744644 15.56% 94.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13958168 5.33% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194916381 78.34% 78.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 997256 0.40% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33202 0.01% 78.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 163976 0.07% 78.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 252533 0.10% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76462 0.03% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 463893 0.19% 79.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206151 0.08% 79.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71843 0.03% 79.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 37907135 15.23% 94.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13730603 5.52% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 261830951 # Type of FU issued -system.cpu.iq.rate 1.236792 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2181302 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008331 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 734699293 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 476117347 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 242859396 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3747317 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2232204 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1844998 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 262127165 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1885088 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1590290 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 248819756 # Type of FU issued +system.cpu.iq.rate 1.403665 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2322951 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009336 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 674003670 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 460004017 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 236904190 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3742073 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2153997 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1836768 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 249257876 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1884831 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1793335 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17048851 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 31549 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12762 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4256480 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12046906 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 20817 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12587 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2915006 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 20 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 150 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23090596 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13781 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 840 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 334926486 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3752435 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 46900559 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16903337 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2201532 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 340 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 255 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12762 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 9994816 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1695108 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11689924 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 249206258 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 38606621 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12624693 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 20559231 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11749 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 500 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 326199297 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1048998 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 41898813 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 15562062 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2080622 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 86 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 254 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12587 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4245338 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3938864 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8184202 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 241936044 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36336721 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6883712 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 53452 # number of nop insts executed -system.cpu.iew.exec_refs 52203623 # number of memory reference insts executed -system.cpu.iew.exec_branches 52584405 # Number of branches executed -system.cpu.iew.exec_stores 13597002 # Number of stores executed -system.cpu.iew.exec_rate 1.177158 # Inst execution rate -system.cpu.iew.wb_sent 246234772 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 244704394 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148512928 # num instructions producing a value -system.cpu.iew.wb_consumers 247801271 # num instructions consuming a value +system.cpu.iew.exec_nop 55634 # number of nop insts executed +system.cpu.iew.exec_refs 49775211 # number of memory reference insts executed +system.cpu.iew.exec_branches 53836233 # Number of branches executed +system.cpu.iew.exec_stores 13438490 # Number of stores executed +system.cpu.iew.exec_rate 1.364832 # Inst execution rate +system.cpu.iew.wb_sent 239697329 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 238740958 # cumulative count of insts written-back +system.cpu.iew.wb_producers 143497606 # num instructions producing a value +system.cpu.iew.wb_consumers 250089451 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.155893 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.599323 # average fanout of values written-back +system.cpu.iew.wb_rate 1.346808 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.573785 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 172328532 # The number of committed instructions -system.cpu.commit.commitCommittedOps 188682015 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 146244510 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1636018 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9791900 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 188552607 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.000686 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.681539 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 172329527 # The number of committed instructions +system.cpu.commit.commitCommittedOps 188683010 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 137516300 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1636217 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6533063 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 156648002 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.204503 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.917568 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 105375521 55.89% 55.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 40844225 21.66% 77.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 19484606 10.33% 87.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8759294 4.65% 92.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4914501 2.61% 95.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2011973 1.07% 96.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1708688 0.91% 97.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1009693 0.54% 97.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4444106 2.36% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79778069 50.93% 50.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 37231664 23.77% 74.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15824405 10.10% 84.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8489087 5.42% 90.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4756905 3.04% 93.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1480671 0.95% 94.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1767391 1.13% 95.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1258526 0.80% 96.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6061284 3.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 188552607 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172328532 # Number of instructions committed -system.cpu.commit.committedOps 188682015 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 156648002 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172329527 # Number of instructions committed +system.cpu.commit.committedOps 188683010 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42498565 # Number of memory references committed -system.cpu.commit.loads 29851708 # Number of loads committed +system.cpu.commit.refs 42498963 # Number of memory references committed +system.cpu.commit.loads 29851907 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40283906 # Number of branches committed +system.cpu.commit.branches 40284105 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150115117 # Number of committed integer instructions. +system.cpu.commit.int_insts 150115913 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4444106 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6061284 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 519029825 # The number of ROB reads -system.cpu.rob.rob_writes 693007050 # The number of ROB writes -system.cpu.timesIdled 1719 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58483 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172314144 # Number of Instructions Simulated -system.cpu.committedOps 188667627 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172314144 # Number of Instructions Simulated -system.cpu.cpi 1.228580 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.228580 # CPI: Total CPI of All Threads -system.cpu.ipc 0.813948 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.813948 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1111988877 # number of integer regfile reads -system.cpu.int_regfile_writes 407368356 # number of integer regfile writes -system.cpu.fp_regfile_reads 2928539 # number of floating regfile reads -system.cpu.fp_regfile_writes 2498508 # number of floating regfile writes -system.cpu.misc_regfile_reads 502946356 # number of misc regfile reads -system.cpu.misc_regfile_writes 824482 # number of misc regfile writes -system.cpu.icache.replacements 1934 # number of replacements -system.cpu.icache.tagsinuse 1329.301324 # Cycle average of tags in use -system.cpu.icache.total_refs 40615441 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3640 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11158.088187 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 476780827 # The number of ROB reads +system.cpu.rob.rob_writes 673054212 # The number of ROB writes +system.cpu.timesIdled 1680 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 57074 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172315139 # Number of Instructions Simulated +system.cpu.committedOps 188668622 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172315139 # Number of Instructions Simulated +system.cpu.cpi 1.028722 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.028722 # CPI: Total CPI of All Threads +system.cpu.ipc 0.972080 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.972080 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1073592031 # number of integer regfile reads +system.cpu.int_regfile_writes 384645437 # number of integer regfile writes +system.cpu.fp_regfile_reads 2906196 # number of floating regfile reads +system.cpu.fp_regfile_writes 2487132 # number of floating regfile writes +system.cpu.misc_regfile_reads 464057527 # number of misc regfile reads +system.cpu.misc_regfile_writes 824880 # number of misc regfile writes +system.cpu.icache.replacements 2566 # number of replacements +system.cpu.icache.tagsinuse 1366.287383 # Cycle average of tags in use +system.cpu.icache.total_refs 36753975 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4308 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8531.563370 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1329.301324 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.649073 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.649073 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 40615441 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 40615441 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 40615441 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 40615441 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 40615441 # number of overall hits -system.cpu.icache.overall_hits::total 40615441 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4234 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4234 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4234 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4234 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4234 # number of overall misses -system.cpu.icache.overall_misses::total 4234 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 101275500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 101275500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 101275500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 101275500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 101275500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 101275500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 40619675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 40619675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 40619675 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 40619675 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 40619675 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 40619675 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000104 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000104 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000104 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23919.579594 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23919.579594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23919.579594 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1366.287383 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.667133 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.667133 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 36753975 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36753975 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36753975 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36753975 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36753975 # number of overall hits +system.cpu.icache.overall_hits::total 36753975 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5001 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5001 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5001 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5001 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5001 # number of overall misses +system.cpu.icache.overall_misses::total 5001 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 108825000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 108825000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 108825000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108825000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 108825000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108825000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36758976 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36758976 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36758976 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36758976 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36758976 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36758976 # 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Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1864 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 24893.334764 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1403.723956 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.342706 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.342706 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 36234545 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 36234545 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356727 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356727 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 27791 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 27791 # 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miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000201 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33039.540101 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31288.949396 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31624.140893 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31624.140893 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # 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number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1009 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1009 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6438 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6438 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7522 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7522 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7522 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7522 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 755 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 755 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 7447 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7447 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7447 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7447 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1091 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1091 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1846 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1846 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1846 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1846 # 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average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 17 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 17 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 17 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 20 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2063 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 675 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2738 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1080 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1080 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2063 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3818 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2063 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1755 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3818 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64062500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21038500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 85101000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33524500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33524500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64062500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54563000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 118625500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64062500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54563000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 118625500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.478877 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.872093 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.990826 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.478877 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941524 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.478877 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941524 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31053.078042 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31168.148148 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31041.203704 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31053.078042 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31090.028490 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31053.078042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31090.028490 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 99b3e7f21..138f6116a 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 15:02:46 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 19:27:36 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -22,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 96266258000 because target called exit() +122 123 124 Exiting @ tick 87727531000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 0aeabdea4..7c2d38b1f 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,264 +1,264 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.096266 # Number of seconds simulated -sim_ticks 96266258000 # Number of ticks simulated -final_tick 96266258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.087728 # Number of seconds simulated +sim_ticks 87727531000 # Number of ticks simulated +final_tick 87727531000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89516 # Simulator instruction rate (inst/s) -host_op_rate 150037 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65247901 # Simulator tick rate (ticks/s) -host_mem_usage 229524 # Number of bytes of host memory used -host_seconds 1475.39 # Real time elapsed on the host +host_inst_rate 101058 # Simulator instruction rate (inst/s) +host_op_rate 169383 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67127344 # Simulator tick rate (ticks/s) +host_mem_usage 229892 # Number of bytes of host memory used +host_seconds 1306.88 # Real time elapsed on the host sim_insts 132071227 # Number of instructions simulated sim_ops 221363017 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 339712 # Number of bytes read from this memory -system.physmem.bytes_inst_read 214912 # Number of instructions bytes read from this memory +system.physmem.bytes_read 345792 # Number of bytes read from this memory +system.physmem.bytes_inst_read 220224 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 5308 # Number of read requests responded to by this memory +system.physmem.num_reads 5403 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3528879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2232475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 3528879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 3941659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 2510318 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 3941659 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 192532517 # number of cpu cycles simulated +system.cpu.numCycles 175455063 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 25728486 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 25728486 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2892788 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 23533152 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 20839978 # Number of BTB hits +system.cpu.BPredUnit.lookups 20916443 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20916443 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2209285 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15543482 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13847483 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 30657479 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 260466955 # Number of instructions fetch has processed -system.cpu.fetch.Branches 25728486 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 20839978 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70644215 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26785814 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 67566342 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 136 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1120 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 28758661 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 555177 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 192452166 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.262310 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.335029 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27331578 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227091825 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20916443 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13847483 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59872682 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 19479342 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 71171142 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9711 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25826236 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 465691 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 175377754 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.138493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.301400 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 123644733 64.25% 64.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4091160 2.13% 66.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3200074 1.66% 68.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4567374 2.37% 70.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4265123 2.22% 72.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4442159 2.31% 74.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5459285 2.84% 77.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3091960 1.61% 79.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39690298 20.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 117181647 66.82% 66.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3214918 1.83% 68.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2487615 1.42% 70.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3152390 1.80% 71.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3541045 2.02% 73.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3761465 2.14% 76.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4534795 2.59% 78.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2814480 1.60% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34689399 19.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 192452166 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.133632 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.352847 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 44411978 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57625858 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 56973408 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9858048 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23582874 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 423042956 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 23582874 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52998252 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14705836 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23082 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 57546904 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43595218 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 410638323 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18885984 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22330558 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 437009036 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1063910767 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1053088723 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10822044 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 175377754 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119213 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.294302 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40655078 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60979767 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46580847 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10170563 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16991499 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 366154541 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16991499 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 48551575 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 16255360 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 22908 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48159937 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 45396475 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 356930622 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 31 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20611614 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22556100 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 370578330 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 915376002 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 905357204 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10018798 # Number of floating rename lookups system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 202645627 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1783 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1777 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 94569707 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103994638 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37171273 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 66711674 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21456392 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 395555693 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2683 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 287296212 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 238230 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 173600960 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 348497721 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1437 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 192452166 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.492819 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.482262 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 136214921 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1884 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1879 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 95075204 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89798900 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 33126150 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59105892 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19470251 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 344622515 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7679 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 271009025 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 252543 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 122771831 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 234148079 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6433 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 175377754 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.545287 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.468253 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 60170871 31.27% 31.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 53695201 27.90% 59.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 36000837 18.71% 77.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20815986 10.82% 88.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13514067 7.02% 95.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 5325466 2.77% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2181156 1.13% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 607811 0.32% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 140771 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 49123743 28.01% 28.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 52511910 29.94% 57.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34319849 19.57% 77.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19020528 10.85% 88.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12714994 7.25% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4949443 2.82% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2083502 1.19% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 542650 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 111135 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 192452166 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 175377754 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 103783 3.80% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2313613 84.82% 88.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 310319 11.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91290 3.51% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2230006 85.80% 89.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 277845 10.69% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1202882 0.42% 0.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 186701896 64.99% 65.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1648118 0.57% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 73212241 25.48% 91.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 24531075 8.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212979 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 176351426 65.07% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1596977 0.59% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68342169 25.22% 91.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23505474 8.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 287296212 # Type of FU issued -system.cpu.iq.rate 1.492196 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2727715 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009494 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 764505561 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 564134434 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 277997574 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5504974 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 5363501 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2644368 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 286052729 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2768316 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18967849 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 271009025 # Type of FU issued +system.cpu.iq.rate 1.544606 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2599141 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009591 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 714934206 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 462829464 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 263397424 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5313282 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4873666 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2553131 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 269732632 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2662555 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18949841 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 47345048 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33748 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 344727 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16655557 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 33149310 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 29835 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 306343 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12610434 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 48770 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 47714 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23582874 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 506702 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 199063 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 395558376 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 136305 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103994638 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37171273 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1768 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 106766 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14420 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 344727 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2499729 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 593078 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3092807 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 283409034 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 71642320 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3887178 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16991499 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 515293 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 247384 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 344630194 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 299081 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89798900 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 33126150 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1841 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 161274 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 32917 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 306343 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1299828 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1028827 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2328655 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 267903545 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 67266011 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3105480 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 95673519 # number of memory reference insts executed -system.cpu.iew.exec_branches 15642768 # Number of branches executed -system.cpu.iew.exec_stores 24031199 # Number of stores executed -system.cpu.iew.exec_rate 1.472006 # Inst execution rate -system.cpu.iew.wb_sent 281921944 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 280641942 # cumulative count of insts written-back -system.cpu.iew.wb_producers 227553614 # num instructions producing a value -system.cpu.iew.wb_consumers 378165457 # num instructions consuming a value +system.cpu.iew.exec_refs 90381113 # number of memory reference insts executed +system.cpu.iew.exec_branches 14784987 # Number of branches executed +system.cpu.iew.exec_stores 23115102 # Number of stores executed +system.cpu.iew.exec_rate 1.526907 # Inst execution rate +system.cpu.iew.wb_sent 266831657 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 265950555 # cumulative count of insts written-back +system.cpu.iew.wb_producers 214539100 # num instructions producing a value +system.cpu.iew.wb_consumers 362277288 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.457634 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.601730 # average fanout of values written-back +system.cpu.iew.wb_rate 1.515776 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.592196 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 174222633 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 123379420 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2892920 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 168869292 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.310854 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.745147 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2210265 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158386255 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.397615 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.796088 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 63124360 37.38% 37.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 62150025 36.80% 74.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15630374 9.26% 83.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11975959 7.09% 90.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5416595 3.21% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2994905 1.77% 95.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2021663 1.20% 96.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1189804 0.70% 97.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4365607 2.59% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 54200924 34.22% 34.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 60421756 38.15% 72.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15533803 9.81% 82.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12711410 8.03% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4532649 2.86% 93.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2958963 1.87% 94.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2077692 1.31% 96.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1244602 0.79% 97.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4704456 2.97% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 168869292 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158386255 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071227 # Number of instructions committed system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -269,64 +269,64 @@ system.cpu.commit.branches 12326943 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4365607 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4704456 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 560089335 # The number of ROB reads -system.cpu.rob.rob_writes 814800236 # The number of ROB writes -system.cpu.timesIdled 1747 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 80351 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 498424236 # The number of ROB reads +system.cpu.rob.rob_writes 706514017 # The number of ROB writes +system.cpu.timesIdled 1681 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 77309 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071227 # Number of Instructions Simulated system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated -system.cpu.cpi 1.457793 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.457793 # CPI: Total CPI of All Threads -system.cpu.ipc 0.685968 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.685968 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 530367480 # number of integer regfile reads -system.cpu.int_regfile_writes 288604591 # number of integer regfile writes -system.cpu.fp_regfile_reads 3608788 # number of floating regfile reads -system.cpu.fp_regfile_writes 2298113 # number of floating regfile writes -system.cpu.misc_regfile_reads 149639402 # number of misc regfile reads +system.cpu.cpi 1.328488 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.328488 # CPI: Total CPI of All Threads +system.cpu.ipc 0.752735 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.752735 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511675262 # number of integer regfile reads +system.cpu.int_regfile_writes 274174484 # number of integer regfile writes +system.cpu.fp_regfile_reads 3515494 # number of floating regfile reads +system.cpu.fp_regfile_writes 2227241 # number of floating regfile writes +system.cpu.misc_regfile_reads 139504609 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 4205 # number of replacements -system.cpu.icache.tagsinuse 1597.649860 # Cycle average of tags in use -system.cpu.icache.total_refs 28751182 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6167 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4662.101832 # Average number of references to valid blocks. +system.cpu.icache.replacements 5602 # number of replacements +system.cpu.icache.tagsinuse 1631.479553 # Cycle average of tags in use +system.cpu.icache.total_refs 25817139 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7573 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3409.103262 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1597.649860 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.780102 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.780102 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 28751182 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 28751182 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 28751182 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 28751182 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 28751182 # number of overall hits -system.cpu.icache.overall_hits::total 28751182 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 7479 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 7479 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 7479 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 7479 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 7479 # number of overall misses -system.cpu.icache.overall_misses::total 7479 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 173725000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 173725000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 173725000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 173725000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 173725000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 173725000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 28758661 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 28758661 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 28758661 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 28758661 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 28758661 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 28758661 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000260 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000260 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000260 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23228.372777 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1631.479553 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.796621 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.796621 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25817139 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25817139 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25817139 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25817139 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25817139 # number of overall hits +system.cpu.icache.overall_hits::total 25817139 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9097 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9097 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9097 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9097 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9097 # number of overall misses +system.cpu.icache.overall_misses::total 9097 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 188035000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 188035000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 188035000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 188035000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 188035000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 188035000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25826236 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25826236 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25826236 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25826236 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25826236 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25826236 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000352 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000352 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20670.001099 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20670.001099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20670.001099 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -335,80 +335,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1119 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1119 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1119 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1119 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1119 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1119 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6360 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6360 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6360 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6360 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6360 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6360 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 125233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 125233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125233500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 125233500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19690.801887 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1378 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1378 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1378 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1378 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1378 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1378 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7719 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7719 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7719 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7719 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7719 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7719 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130954500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 130954500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130954500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 130954500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130954500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 130954500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16965.215702 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16965.215702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16965.215702 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 56 # number of replacements -system.cpu.dcache.tagsinuse 1415.486536 # Cycle average of tags in use -system.cpu.dcache.total_refs 72938173 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1987 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 36707.686462 # Average number of references to valid blocks. +system.cpu.dcache.replacements 54 # number of replacements +system.cpu.dcache.tagsinuse 1429.840369 # Cycle average of tags in use +system.cpu.dcache.total_refs 68659767 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1998 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34364.247748 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1415.486536 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.345578 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.345578 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 52423955 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 52423955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513973 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513973 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 72937928 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 72937928 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 72937928 # number of overall hits -system.cpu.dcache.overall_hits::total 72937928 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 771 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 771 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1757 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1757 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2528 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2528 # number of overall misses -system.cpu.dcache.overall_misses::total 2528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24605500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24605500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 66582500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66582500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91188000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91188000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91188000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91188000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 52424726 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 52424726 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1429.840369 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.349082 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.349082 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 48145557 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 48145557 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514023 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514023 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68659580 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68659580 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68659580 # number of overall hits +system.cpu.dcache.overall_hits::total 68659580 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 765 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 765 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1707 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1707 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2472 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2472 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2472 # number of overall misses +system.cpu.dcache.overall_misses::total 2472 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24609000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24609000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64758500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64758500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 89367500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 89367500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89367500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89367500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 48146322 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 48146322 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 72940456 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 72940456 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 72940456 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 72940456 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000015 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000086 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000035 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000035 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31913.748379 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37895.560615 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36071.202532 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36071.202532 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 68662052 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 68662052 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 68662052 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 68662052 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000016 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000036 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000036 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32168.627451 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37937.024019 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36151.901294 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36151.901294 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,119 +419,119 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 13 # number of writebacks system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 344 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 344 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 346 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 346 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 346 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 346 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 427 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1755 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1755 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2182 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2182 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2182 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2182 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14039500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 14039500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61244500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 61244500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 75284000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 75284000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 75284000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 75284000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000086 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000030 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000030 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32879.391101 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34897.150997 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34502.291476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34502.291476 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 323 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 323 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 326 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 326 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 442 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 442 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1704 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1704 # 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Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2496.824684 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2842 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3755 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.756858 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2591.074934 # Cycle average of tags in use +system.cpu.l2cache.total_refs 4164 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3853 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 1.080716 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1.944495 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2209.976363 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 284.903826 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9573 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 7573 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2000 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9573 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.454377 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.931973 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994882 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.544511 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.980392 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.544511 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.980392 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34257.742704 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34167.088608 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34126.366559 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34257.742704 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.615385 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34257.742704 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.615385 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994869 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.454377 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.981000 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.454377 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.981000 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34254.577158 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34183.698297 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34158.607350 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34254.577158 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34163.863405 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34254.577158 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34163.863405 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,48 +540,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3358 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 395 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3753 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 193 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 193 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1555 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1555 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3358 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1950 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5308 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3358 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1950 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5308 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104175500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12238000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116413500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5983000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5983000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48232500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48232500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104175500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60470500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 164646000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104175500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60470500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 164646000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927230 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3441 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 411 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3852 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 146 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 146 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1551 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1551 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3441 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1962 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5403 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3441 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5403 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106751500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12743500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 119495000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4526000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4526000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48112000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48112000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106751500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60855500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 167607000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106751500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60855500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 167607000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.454377 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.931973 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994882 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.079214 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30982.278481 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994869 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.454377 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981000 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.454377 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981000 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.394362 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.082725 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31017.684887 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.987105 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.394362 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31017.074414 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.394362 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31017.074414 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |