diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
| commit | 806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6 (patch) | |
| tree | bf8944a02c194cb657534276190f2a17859b3675 /tests/long/se | |
| parent | a9a7002a3b3ad1e423d16ace826e80574d4ddc4f (diff) | |
| download | gem5-806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6.tar.xz | |
stats: Update stats to reflect snoop-filter changes
Diffstat (limited to 'tests/long/se')
39 files changed, 9913 insertions, 9679 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 8f24165d3..2f7887688 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.061241 # Number of seconds simulated -sim_ticks 61240850500 # Number of ticks simulated -final_tick 61240850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 61241011500 # Number of ticks simulated +final_tick 61241011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 182783 # Simulator instruction rate (inst/s) -host_op_rate 183693 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 123547949 # Simulator tick rate (ticks/s) -host_mem_usage 442472 # Number of bytes of host memory used -host_seconds 495.69 # Real time elapsed on the host +host_inst_rate 252391 # Simulator instruction rate (inst/s) +host_op_rate 253648 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 170598134 # Simulator tick rate (ticks/s) +host_mem_usage 450980 # Number of bytes of host memory used +host_seconds 358.98 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 49536 # Nu system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 808872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15466800 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16275672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 808872 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 808872 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 808872 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15466800 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 16275672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 808870 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15466760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16275629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 808870 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 808870 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 808870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15466760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16275629 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15574 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61240757000 # Total gap between requests +system.physmem.totGap 61240917000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 644.601036 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 438.502120 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 402.393837 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 247 16.00% 16.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 189 12.24% 28.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 92 5.96% 34.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 68 4.40% 38.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 69 4.47% 43.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 87 5.63% 48.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 40 2.59% 51.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 47 3.04% 54.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 705 45.66% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation -system.physmem.totQLat 73458500 # Total ticks spent queuing -system.physmem.totMemAccLat 365471000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1543 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 644.935839 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 438.870546 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 402.302511 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 247 16.01% 16.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 187 12.12% 28.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 93 6.03% 34.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 68 4.41% 38.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 69 4.47% 43.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 87 5.64% 48.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 40 2.59% 51.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 47 3.05% 54.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 705 45.69% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1543 # Bytes accessed per row activation +system.physmem.totQLat 73241750 # Total ticks spent queuing +system.physmem.totMemAccLat 365254250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4716.74 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4702.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23466.74 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23452.82 # Average memory access latency per DRAM burst system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s @@ -220,35 +220,35 @@ system.physmem.readRowHits 14026 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.06 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 3932243.29 # Average gap between requests +system.physmem.avgGap 3932253.56 # Average gap between requests system.physmem.pageHitRate 90.06 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 6305040 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 3440250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 63780600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2494978920 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34554891750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41123220960 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.518851 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57475186750 # Time in different power states +system.physmem_0.actBackEnergy 2491477695 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34557963000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41122783185 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.511702 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57480391250 # Time in different power states system.physmem_0.memoryStateTime::REF 2044900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1719043250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1713925750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5367600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2928750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 57517200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5360040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2924625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2555622360 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34501695750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41122956060 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.514525 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57387265750 # Time in different power states +system.physmem_1.actBackEnergy 2555146980 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34502112750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41122878195 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.513254 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57387655250 # Time in different power states system.physmem_1.memoryStateTime::REF 2044900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1807269750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1806574750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 20752188 # Number of BP lookups system.cpu.branchPred.condPredicted 17062075 # Number of conditional branches predicted @@ -377,29 +377,29 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 122481701 # number of cpu cycles simulated +system.cpu.numCycles 122482023 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2176622 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2176623 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.351853 # CPI: cycles per instruction -system.cpu.ipc 0.739726 # IPC: instructions per cycle -system.cpu.tickCycles 109255125 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13226576 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.351856 # CPI: cycles per instruction +system.cpu.ipc 0.739724 # IPC: instructions per cycle +system.cpu.tickCycles 109255164 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13226859 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 946097 # number of replacements -system.cpu.dcache.tags.tagsinuse 3616.871508 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3616.872758 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26263183 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.639841 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 20511562500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3616.871508 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.883025 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.883025 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.872758 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.883026 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.883026 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2246 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 1594 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 55455001 # Number of tag accesses @@ -428,14 +428,14 @@ system.cpu.dcache.demand_misses::cpu.data 989217 # n system.cpu.dcache.demand_misses::total 989217 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 989221 # number of overall misses system.cpu.dcache.overall_misses::total 989221 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918942500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11918942500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542548000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2542548000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14461490500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14461490500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14461490500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14461490500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919048000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11919048000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542627500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2542627500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14461675500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14461675500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14461675500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14461675500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22509137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22509137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) @@ -460,14 +460,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.036309 system.cpu.dcache.demand_miss_rate::total 0.036309 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.220234 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.220234 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34224.172511 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34224.172511 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.128563 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14619.128563 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.069450 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14619.069450 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.335544 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.335544 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.242627 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.242627 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.315580 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14619.315580 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.256465 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14619.256465 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -496,16 +496,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950190 system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865257500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865257500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481584500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481584500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865351000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865351000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481616500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481616500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346842000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12346842000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12346998500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12346998500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346967500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12346967500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12347124000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12347124000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040136 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040136 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses @@ -516,69 +516,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034877 system.cpu.dcache.demand_mshr_miss_rate::total 0.034877 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034876 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.739906 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.739906 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31681.481877 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31681.481877 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.843401 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.843401 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.166150 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.166150 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.076974 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.076974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.200652 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.200652 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.209053 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.209053 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.332730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.332730 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 689.439690 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27770466 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 689.439811 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27770468 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34626.516209 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34626.518703 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 689.439690 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.336640 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.336640 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 689.439811 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.336641 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.336641 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55543338 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55543338 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27770466 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27770466 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27770466 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27770466 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27770466 # number of overall hits -system.cpu.icache.overall_hits::total 27770466 # number of overall hits +system.cpu.icache.tags.tag_accesses 55543342 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55543342 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27770468 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27770468 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27770468 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27770468 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27770468 # number of overall hits +system.cpu.icache.overall_hits::total 27770468 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 60107000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 60107000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 60107000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 60107000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 60107000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 60107000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27771268 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27771268 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27771268 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27771268 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27771268 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27771268 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 59898000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 59898000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 59898000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 59898000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 59898000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 59898000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27771270 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27771270 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27771270 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27771270 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27771270 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27771270 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74946.384040 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74946.384040 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74946.384040 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74946.384040 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74946.384040 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74946.384040 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74685.785536 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74685.785536 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74685.785536 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74685.785536 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74685.785536 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74685.785536 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,38 +593,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59305000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59305000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59305000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59305000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59305000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59305000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59096000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59096000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59096000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59096000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59096000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59096000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73946.384040 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73946.384040 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73946.384040 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73946.384040 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73946.384040 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73946.384040 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73685.785536 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73685.785536 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73685.785536 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73685.785536 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10245.543243 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 10245.556298 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1833992 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 117.888539 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9355.642515 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444420 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456307 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 9355.655412 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444539 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456347 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.285512 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020582 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006575 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.312669 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.312670 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id @@ -660,18 +660,18 @@ system.cpu.l2cache.demand_misses::total 15582 # nu system.cpu.l2cache.overall_misses::cpu.inst 776 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses system.cpu.l2cache.overall_misses::total 15582 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067640500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1067640500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57828000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 57828000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21914500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 21914500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 57828000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1089555000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1147383000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 57828000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1089555000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1147383000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067673500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1067673500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57597000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 57597000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21897000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 21897000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 57597000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1089570500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1147167500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 57597000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1089570500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1147167500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 943278 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 943278 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46765 # number of ReadExReq accesses(hits+misses) @@ -698,18 +698,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016385 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967581 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73407.625138 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73407.625138 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74520.618557 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74520.618557 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83643.129771 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83643.129771 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74520.618557 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73588.747805 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73635.155949 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74520.618557 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73588.747805 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73635.155949 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.894114 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.894114 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74222.938144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74222.938144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83576.335878 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83576.335878 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73621.325889 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73621.325889 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -740,18 +740,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15574 system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922200500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922200500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49941000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49941000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18963500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18963500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49941000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941164000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 991105000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49941000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941164000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 991105000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922233500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922233500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49710000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49710000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18946000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18946000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49710000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941179500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 990889500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49710000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941179500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 990889500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311002 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311002 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses @@ -764,19 +764,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63407.625138 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63407.625138 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64523.255814 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64523.255814 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74076.171875 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74076.171875 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64523.255814 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63592.162162 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63638.435855 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64523.255814 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63592.162162 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63638.435855 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.894114 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.894114 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64224.806202 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64224.806202 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74007.812500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74007.812500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1897097 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 943278 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2674 # Transaction distribution @@ -792,14 +798,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 121233472 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1897097 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.012905 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1897097 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1896781 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 316 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1897097 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1891826500 # Layer occupancy (ticks) @@ -827,9 +833,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21739500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21741000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82130500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82130750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 6f66b7dfa..6db072c1c 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,113 +1,113 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058182 # Number of seconds simulated -sim_ticks 58182114500 # Number of ticks simulated -final_tick 58182114500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058181 # Number of seconds simulated +sim_ticks 58181475500 # Number of ticks simulated +final_tick 58181475500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128679 # Simulator instruction rate (inst/s) -host_op_rate 129320 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 82645168 # Simulator tick rate (ticks/s) -host_mem_usage 446228 # Number of bytes of host memory used -host_seconds 704.00 # Real time elapsed on the host +host_inst_rate 122946 # Simulator instruction rate (inst/s) +host_op_rate 123559 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78962453 # Simulator tick rate (ticks/s) +host_mem_usage 448784 # Number of bytes of host memory used +host_seconds 736.82 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 44288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 51456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 933184 # Number of bytes read from this memory -system.physmem.bytes_read::total 1028928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44288 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44288 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 27456 # Number of bytes written to this memory -system.physmem.bytes_written::total 27456 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 692 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 804 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14581 # Number of read requests responded to by this memory -system.physmem.num_reads::total 16077 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 429 # Number of write requests responded to by this memory -system.physmem.num_writes::total 429 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 761196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 884395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 16039018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17684610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 761196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 761196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 471898 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 471898 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 471898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 761196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 884395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 16039018 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18156508 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 16077 # Number of read requests accepted -system.physmem.writeReqs 429 # Number of write requests accepted -system.physmem.readBursts 16077 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 429 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1014080 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 14848 # Total number of bytes read from write queue -system.physmem.bytesWritten 26048 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1028928 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 27456 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 232 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 44416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 50176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 933312 # Number of bytes read from this memory +system.physmem.bytes_read::total 1027904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 28672 # Number of bytes written to this memory +system.physmem.bytes_written::total 28672 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 694 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 784 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14583 # Number of read requests responded to by this memory +system.physmem.num_reads::total 16061 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 448 # Number of write requests responded to by this memory +system.physmem.num_writes::total 448 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 763404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 862405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 16041394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17667204 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 763404 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 763404 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 492803 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 492803 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 492803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 763404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 862405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 16041394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18160007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 16061 # Number of read requests accepted +system.physmem.writeReqs 448 # Number of write requests accepted +system.physmem.readBursts 16061 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 448 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1014144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 13760 # Total number of bytes read from write queue +system.physmem.bytesWritten 26688 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1027904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 28672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 215 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1011 # Per bank write bursts +system.physmem.perBankRdBursts::0 1015 # Per bank write bursts system.physmem.perBankRdBursts::1 876 # Per bank write bursts -system.physmem.perBankRdBursts::2 957 # Per bank write bursts -system.physmem.perBankRdBursts::3 1029 # Per bank write bursts -system.physmem.perBankRdBursts::4 1060 # Per bank write bursts -system.physmem.perBankRdBursts::5 1137 # Per bank write bursts -system.physmem.perBankRdBursts::6 1146 # Per bank write bursts -system.physmem.perBankRdBursts::7 1099 # Per bank write bursts -system.physmem.perBankRdBursts::8 1049 # Per bank write bursts +system.physmem.perBankRdBursts::2 960 # Per bank write bursts +system.physmem.perBankRdBursts::3 1024 # Per bank write bursts +system.physmem.perBankRdBursts::4 1064 # Per bank write bursts +system.physmem.perBankRdBursts::5 1138 # Per bank write bursts +system.physmem.perBankRdBursts::6 1126 # Per bank write bursts +system.physmem.perBankRdBursts::7 1116 # Per bank write bursts +system.physmem.perBankRdBursts::8 1048 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 940 # Per bank write bursts -system.physmem.perBankRdBursts::11 901 # Per bank write bursts -system.physmem.perBankRdBursts::12 907 # Per bank write bursts -system.physmem.perBankRdBursts::13 888 # Per bank write bursts -system.physmem.perBankRdBursts::14 960 # Per bank write bursts -system.physmem.perBankRdBursts::15 923 # Per bank write bursts -system.physmem.perBankWrBursts::0 29 # Per bank write bursts +system.physmem.perBankRdBursts::10 947 # Per bank write bursts +system.physmem.perBankRdBursts::11 899 # Per bank write bursts +system.physmem.perBankRdBursts::12 909 # Per bank write bursts +system.physmem.perBankRdBursts::13 891 # Per bank write bursts +system.physmem.perBankRdBursts::14 939 # Per bank write bursts +system.physmem.perBankRdBursts::15 932 # Per bank write bursts +system.physmem.perBankWrBursts::0 39 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 8 # Per bank write bursts -system.physmem.perBankWrBursts::3 7 # Per bank write bursts -system.physmem.perBankWrBursts::4 4 # Per bank write bursts -system.physmem.perBankWrBursts::5 30 # Per bank write bursts -system.physmem.perBankWrBursts::6 102 # Per bank write bursts -system.physmem.perBankWrBursts::7 27 # Per bank write bursts -system.physmem.perBankWrBursts::8 34 # Per bank write bursts +system.physmem.perBankWrBursts::2 11 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 10 # Per bank write bursts +system.physmem.perBankWrBursts::5 33 # Per bank write bursts +system.physmem.perBankWrBursts::6 78 # Per bank write bursts +system.physmem.perBankWrBursts::7 51 # Per bank write bursts +system.physmem.perBankWrBursts::8 44 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 11 # Per bank write bursts -system.physmem.perBankWrBursts::11 5 # Per bank write bursts -system.physmem.perBankWrBursts::12 6 # Per bank write bursts -system.physmem.perBankWrBursts::13 38 # Per bank write bursts -system.physmem.perBankWrBursts::14 82 # Per bank write bursts -system.physmem.perBankWrBursts::15 24 # Per bank write bursts +system.physmem.perBankWrBursts::10 13 # Per bank write bursts +system.physmem.perBankWrBursts::11 2 # Per bank write bursts +system.physmem.perBankWrBursts::12 8 # Per bank write bursts +system.physmem.perBankWrBursts::13 25 # Per bank write bursts +system.physmem.perBankWrBursts::14 64 # Per bank write bursts +system.physmem.perBankWrBursts::15 39 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58181957500 # Total gap between requests +system.physmem.totGap 58181318500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 16077 # Read request sizes (log2) +system.physmem.readPktSize::6 16061 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 429 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10965 # What read queue length does an incoming req see +system.physmem.writePktSize::6 448 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 10962 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 2513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 456 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 299 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 298 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 275 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 295 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 58 # What read queue length does an incoming req see @@ -148,26 +148,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 24 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -197,93 +197,93 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1937 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 535.822406 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 300.454496 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 434.844935 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 623 32.16% 32.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 199 10.27% 42.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 99 5.11% 47.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 70 3.61% 51.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 49 2.53% 53.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 51 2.63% 56.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 51 2.63% 58.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 47 2.43% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 748 38.62% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1937 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1956 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 531.533742 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 297.285521 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 435.040107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 621 31.75% 31.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 232 11.86% 43.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 86 4.40% 48.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 69 3.53% 51.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 49 2.51% 54.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 52 2.66% 56.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 53 2.71% 59.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 46 2.35% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 748 38.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1956 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 23 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 687.695652 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 31.373989 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3139.186163 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 686.869565 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 31.250235 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3138.483903 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-511 22 95.65% 95.65% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 4.35% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 23 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 23 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.695652 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.676543 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.822125 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4 17.39% 17.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18 78.26% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 4.35% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.130435 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.125203 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.457697 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 21 91.30% 91.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 4.35% 95.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 4.35% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 23 # Writes before turning the bus around for reads -system.physmem.totQLat 162696744 # Total ticks spent queuing -system.physmem.totMemAccLat 459790494 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 79225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10268.02 # Average queueing delay per DRAM burst +system.physmem.totQLat 162337192 # Total ticks spent queuing +system.physmem.totMemAccLat 459449692 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 79230000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10244.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29018.02 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28994.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 17.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.45 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 17.68 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.47 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBW 0.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 17.67 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.49 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.47 # Average read queue length when enqueuing -system.physmem.avgWrQLen 18.75 # Average write queue length when enqueuing -system.physmem.readRowHits 14165 # Number of row buffer hits during reads -system.physmem.writeRowHits 138 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing +system.physmem.avgWrQLen 20.72 # Average write queue length when enqueuing +system.physmem.readRowHits 14167 # Number of row buffer hits during reads +system.physmem.writeRowHits 131 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.47 # Row buffer hit rate for writes -system.physmem.avgGap 3524897.46 # Average gap between requests -system.physmem.pageHitRate 87.91 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7749000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 4228125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 64591800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1302480 # Energy for write commands per rank (pJ) +system.physmem.writeRowHitRate 29.57 # Row buffer hit rate for writes +system.physmem.avgGap 3524218.21 # Average gap between requests +system.physmem.pageHitRate 87.78 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7983360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 4356000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 64662000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1438560 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2489657400 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32723562000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 39091051125 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.908601 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 54427806081 # Time in different power states +system.physmem_0.actBackEnergy 2503358775 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32711543250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39093302265 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.947294 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54407827569 # Time in different power states system.physmem_0.memoryStateTime::REF 1942720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1808607669 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1828586181 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6811560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3716625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 58687200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1211760 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 6788880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3704250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 58663800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1263600 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2472306885 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32738773500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 39081467850 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.744040 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54453180249 # Time in different power states +system.physmem_1.actBackEnergy 2462347845 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32747517750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39080246445 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.722887 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54468275483 # Time in different power states system.physmem_1.memoryStateTime::REF 1942720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1783438751 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1768727017 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 28257673 # Number of BP lookups -system.cpu.branchPred.condPredicted 23279792 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 837861 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11842586 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11784928 # Number of BTB hits +system.cpu.branchPred.lookups 28257355 # Number of BP lookups +system.cpu.branchPred.condPredicted 23279453 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 837859 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11842476 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11784812 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.513130 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 75759 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 99.513075 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 75760 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -403,83 +403,83 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 116364230 # number of cpu cycles simulated +system.cpu.numCycles 116362952 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 748840 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134987137 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28257673 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11860687 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 114722877 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 748921 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134986415 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28257355 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11860572 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 114720736 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1679131 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 949 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 833 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32301983 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 576 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116313064 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.165803 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.319035 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 953 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 835 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32301690 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 580 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116311010 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.165818 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.319039 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58742008 50.50% 50.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13941997 11.99% 62.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9231022 7.94% 70.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34398037 29.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58740461 50.50% 50.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13941673 11.99% 62.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9230825 7.94% 70.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34398051 29.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116313064 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 116311010 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.242838 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.160040 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8839881 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64052748 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33035096 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9558012 # Number of cycles decode is unblocking +system.cpu.fetch.rate 1.160046 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8839998 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64050748 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33034874 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9558063 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 827327 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4101304 # Number of times decode resolved a branch +system.cpu.decode.BranchResolved 4101313 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 12342 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114430189 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1996961 # Number of squashed instructions handled by decode +system.cpu.decode.DecodedInsts 114429656 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1996969 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 827327 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15280915 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49896712 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 109420 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35425336 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14773354 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110898724 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1415582 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11131047 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1144428 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1527040 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 487812 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129956476 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483272365 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119474128 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 430 # Number of floating rename lookups +system.cpu.rename.IdleCycles 15281198 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49893829 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 109582 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35425015 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14774059 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110898152 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1415674 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11131476 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1144261 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1527056 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 488175 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129955893 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483270095 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119473614 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 428 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22643557 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22642974 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21506605 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26812984 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5349507 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 517744 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 254125 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109690412 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 21507084 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26812785 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5349554 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 517855 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 254082 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109689870 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101387626 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1074735 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18657629 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41690294 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 101387714 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1074676 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18657087 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41688114 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116313064 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.871679 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.989298 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 116311010 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.871695 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.989305 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54672209 47.00% 47.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31362113 26.96% 73.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22008866 18.92% 92.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7072036 6.08% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1197527 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54670243 47.00% 47.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31362294 26.96% 73.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22008143 18.92% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7072499 6.08% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197518 1.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -487,9 +487,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116313064 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116311010 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9793385 48.69% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9794091 48.69% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 50 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.69% # attempts to use FU when none available @@ -512,19 +512,19 @@ system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.69% # at system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 14 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9616432 47.81% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 703828 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9615955 47.81% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 703739 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71984128 71.00% 71.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10709 0.01% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71984145 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10710 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued @@ -546,90 +546,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 53 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 52 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 123 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24343025 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5049584 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24343095 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5049585 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101387626 # Type of FU issued -system.cpu.iq.rate 0.871295 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20113709 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198384 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 340276307 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128356979 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99625202 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 453 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 112 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121501099 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 290480 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 101387714 # Type of FU issued +system.cpu.iq.rate 0.871306 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20113848 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198385 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340274513 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128355901 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99625297 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 449 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 614 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 111 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121501328 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 234 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 290500 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4337073 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 4336874 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1516 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1343 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 604663 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1345 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 604710 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7562 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130598 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7564 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130574 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 827327 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8118752 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684481 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109711326 # Number of instructions dispatched to IQ +system.cpu.iew.iewBlockCycles 8118136 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 684680 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109710785 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26812984 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5349507 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26812785 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5349554 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 179113 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 342349 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1343 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 436660 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412872 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 849532 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100126680 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23806374 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1260946 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 179049 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 342646 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1345 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 436655 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412870 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 849525 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100126849 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23806470 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1260865 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12667 # number of nop insts executed -system.cpu.iew.exec_refs 28724279 # number of memory reference insts executed -system.cpu.iew.exec_branches 20624229 # Number of branches executed -system.cpu.iew.exec_stores 4917905 # Number of stores executed -system.cpu.iew.exec_rate 0.860459 # Inst execution rate -system.cpu.iew.wb_sent 99709898 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99625314 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59703303 # num instructions producing a value -system.cpu.iew.wb_consumers 95544285 # num instructions consuming a value +system.cpu.iew.exec_nop 12668 # number of nop insts executed +system.cpu.iew.exec_refs 28724380 # number of memory reference insts executed +system.cpu.iew.exec_branches 20624234 # Number of branches executed +system.cpu.iew.exec_stores 4917910 # Number of stores executed +system.cpu.iew.exec_rate 0.860470 # Inst execution rate +system.cpu.iew.wb_sent 99710000 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99625408 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59703416 # num instructions producing a value +system.cpu.iew.wb_consumers 95544446 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.856151 # insts written-back per cycle +system.cpu.iew.wb_rate 0.856161 # insts written-back per cycle system.cpu.iew.wb_fanout 0.624876 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 17385621 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 17385130 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 825623 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 113620717 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.801382 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.737978 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 825621 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113618734 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.801396 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.737990 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77197638 67.94% 67.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18614899 16.38% 84.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7150727 6.29% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3466583 3.05% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1641577 1.44% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 544810 0.48% 95.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 704355 0.62% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 179975 0.16% 96.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4120153 3.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77195687 67.94% 67.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18614563 16.38% 84.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7151371 6.29% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3466253 3.05% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1641564 1.44% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 544784 0.48% 95.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 704352 0.62% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 179993 0.16% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4120167 3.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 113620717 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113618734 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -675,78 +675,78 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4120153 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 217934090 # The number of ROB reads -system.cpu.rob.rob_writes 219571457 # The number of ROB writes -system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 51166 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4120167 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 217931602 # The number of ROB reads +system.cpu.rob.rob_writes 219570402 # The number of ROB writes +system.cpu.timesIdled 589 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 51942 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.284518 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.284518 # CPI: Total CPI of All Threads -system.cpu.ipc 0.778502 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.778502 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108111423 # number of integer regfile reads -system.cpu.int_regfile_writes 58700979 # number of integer regfile writes -system.cpu.fp_regfile_reads 58 # number of floating regfile reads +system.cpu.cpi 1.284504 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.284504 # CPI: Total CPI of All Threads +system.cpu.ipc 0.778511 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.778511 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108111563 # number of integer regfile reads +system.cpu.int_regfile_writes 58701013 # number of integer regfile writes +system.cpu.fp_regfile_reads 59 # number of floating regfile reads system.cpu.fp_regfile_writes 92 # number of floating regfile writes -system.cpu.cc_regfile_reads 369063033 # number of cc regfile reads -system.cpu.cc_regfile_writes 58693305 # number of cc regfile writes -system.cpu.misc_regfile_reads 28414934 # number of misc regfile reads +system.cpu.cc_regfile_reads 369063684 # number of cc regfile reads +system.cpu.cc_regfile_writes 58693489 # number of cc regfile writes +system.cpu.misc_regfile_reads 28414952 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.replacements 5470204 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.787652 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18251843 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5470716 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.336280 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 5470194 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.787648 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18251935 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5470706 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.336303 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 35373500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.787652 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.787648 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999585 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999585 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 357 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 343 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61908596 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61908596 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13889769 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13889769 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4353793 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4353793 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61908668 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61908668 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13889868 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13889868 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4353786 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4353786 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18243562 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18243562 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18244084 # number of overall hits -system.cpu.dcache.overall_hits::total 18244084 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9585887 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9585887 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 381188 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 381188 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18243654 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18243654 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18244176 # number of overall hits +system.cpu.dcache.overall_hits::total 18244176 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9585829 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9585829 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 381195 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 381195 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9967075 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9967075 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9967082 # number of overall misses -system.cpu.dcache.overall_misses::total 9967082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88721516500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88721516500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4007000296 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4007000296 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9967024 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9967024 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9967031 # number of overall misses +system.cpu.dcache.overall_misses::total 9967031 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88721011000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88721011000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4006916840 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4006916840 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 296500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92728516796 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92728516796 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92728516796 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92728516796 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23475656 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23475656 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 92727927840 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92727927840 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92727927840 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92727927840 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23475697 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23475697 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -755,100 +755,100 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28210637 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28210637 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28211166 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28211166 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408333 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408333 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080505 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080505 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28210678 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28210678 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28211207 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28211207 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408330 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408330 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080506 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080506 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353309 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353309 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353303 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353303 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9255.431083 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9255.431083 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10511.874183 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10511.874183 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.353307 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353307 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353300 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353300 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9255.434350 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9255.434350 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10511.462218 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10511.462218 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9303.483399 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9303.483399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9303.476865 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9303.476865 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 329940 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 111027 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121461 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.716427 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.648310 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9303.471913 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9303.471913 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9303.465379 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9303.465379 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 329844 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 111014 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121439 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12836 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.716129 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.648644 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 5432438 # number of writebacks -system.cpu.dcache.writebacks::total 5432438 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337660 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4337660 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158703 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158703 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 5433212 # number of writebacks +system.cpu.dcache.writebacks::total 5433212 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337614 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4337614 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158708 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158708 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4496363 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4496363 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4496363 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4496363 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248227 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248227 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222485 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222485 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4496322 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4496322 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4496322 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4496322 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248215 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248215 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222487 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222487 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5470712 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5470712 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5470716 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5470716 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43248007500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43248007500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2284927222 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2284927222 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 5470702 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5470702 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5470706 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5470706 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43247632500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43247632500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285123725 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285123725 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45532934722 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45532934722 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45533149222 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45533149222 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223560 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223560 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45532756225 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45532756225 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45532970725 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45532970725 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223559 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223559 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193924 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193924 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193923 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193923 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193920 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.193920 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8240.498648 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8240.498648 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.028191 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.028191 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8240.446037 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8240.446037 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.819082 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.819082 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8323.036329 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8323.036329 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8323.069452 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8323.069452 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8323.018915 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8323.018915 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8323.052038 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8323.052038 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 451 # number of replacements -system.cpu.icache.tags.tagsinuse 428.507566 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32300812 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 428.507470 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32300517 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 910 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35495.397802 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 35495.073626 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 428.507566 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 428.507470 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.836929 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.836929 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id @@ -857,196 +857,196 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 51 system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 331 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64604850 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64604850 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 32300812 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32300812 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32300812 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32300812 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32300812 # number of overall hits -system.cpu.icache.overall_hits::total 32300812 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1158 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1158 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1158 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1158 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1158 # number of overall misses -system.cpu.icache.overall_misses::total 1158 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 61588984 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 61588984 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 61588984 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 61588984 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 61588984 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 61588984 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32301970 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32301970 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32301970 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32301970 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32301970 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32301970 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 64604262 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64604262 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 32300517 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32300517 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32300517 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32300517 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32300517 # number of overall hits +system.cpu.icache.overall_hits::total 32300517 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1159 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1159 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1159 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1159 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1159 # number of overall misses +system.cpu.icache.overall_misses::total 1159 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62258984 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62258984 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62258984 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62258984 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62258984 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62258984 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32301676 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32301676 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32301676 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32301676 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32301676 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32301676 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53185.651123 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53185.651123 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53185.651123 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53185.651123 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53185.651123 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53185.651123 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 19024 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 135 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53717.846419 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53717.846419 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53717.846419 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53717.846419 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53717.846419 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53717.846419 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 18998 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 136 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 221 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 84.551111 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 85.963801 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 27.200000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 248 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 248 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 248 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 248 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 249 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 249 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 249 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 249 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 910 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 910 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 910 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 910 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49864488 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49864488 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49864488 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49864488 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49864488 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 49864488 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50293988 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50293988 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50293988 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50293988 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50293988 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50293988 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54796.140659 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54796.140659 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54796.140659 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54796.140659 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54796.140659 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54796.140659 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55268.118681 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55268.118681 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55268.118681 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55268.118681 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55268.118681 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55268.118681 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 4982376 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 5297288 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 273784 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 4980719 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 5295706 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 273829 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 14074296 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 642 # number of replacements -system.cpu.l2cache.tags.tagsinuse 12072.124687 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 10689018 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 16082 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 664.657257 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 14074518 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 620 # number of replacements +system.cpu.l2cache.tags.tagsinuse 12071.188165 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 10691146 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 16060 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 665.700249 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11058.580214 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 574.634156 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 222.368326 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 216.541992 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.674962 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035073 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.013572 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013217 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.736824 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 275 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15165 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 11063.420038 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 575.029353 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 219.514162 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 213.224612 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.675258 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035097 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.013398 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013014 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.736767 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 266 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15174 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 17 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 10 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 238 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 22 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 9 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 224 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 966 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1062 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 971 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1064 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13065 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.016785 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.925598 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 175272448 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 175272448 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 5432438 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 5432438 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 226006 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 226006 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 217 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 217 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243653 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 5243653 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 217 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 5469659 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5469876 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 217 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 5469659 # number of overall hits -system.cpu.l2cache.overall_hits::total 5469876 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 504 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 504 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 693 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 693 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 553 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 553 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 693 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1057 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1750 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 693 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1057 # number of overall misses -system.cpu.l2cache.overall_misses::total 1750 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 42131500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 42131500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47516500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 47516500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32807500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 32807500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 47516500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 74939000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 122455500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 47516500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 74939000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 122455500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 5432438 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 5432438 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 226510 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 226510 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.762637 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.762637 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000084 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.762637 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000143 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000270 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.762637 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000143 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.004056 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41019.803691 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41019.803691 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96347.507331 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96347.507331 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62579.479769 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62579.479769 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 56055.075594 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 56055.075594 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62579.479769 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73144.278607 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68257.352941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62579.479769 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73144.278607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41019.803691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42855.849908 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.004061 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 40925.493009 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 40925.493009 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95749.271137 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95749.271137 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62990.634006 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62990.634006 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 56670.068027 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 56670.068027 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62990.634006 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73767.219388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68707.036536 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62990.634006 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73767.219388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 40925.493009 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42773.594608 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 5245116 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 5432867 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 35515 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 22583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226510 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226510 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 10942261 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5470659 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 6201 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 6201 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 5245097 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 5433660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 34692 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 22620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 910 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244206 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244187 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2259 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16408733 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16410992 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16408705 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16410964 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697801856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 697860096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 23225 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10965506 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.002118 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045973 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697850752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 697908992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 23240 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10965501 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001098 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.033119 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 10942281 99.79% 99.79% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 23225 0.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10953460 99.89% 99.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12041 0.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10965506 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10903578500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 10965501 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10904342500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1366996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1367495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206077992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 8206062992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 15736 # Transaction distribution -system.membus.trans_dist::Writeback 429 # Transaction distribution -system.membus.trans_dist::CleanEvict 169 # Transaction distribution -system.membus.trans_dist::ReadExReq 341 # Transaction distribution -system.membus.trans_dist::ReadExResp 341 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 15736 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32752 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 32752 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1056384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1056384 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 15718 # Transaction distribution +system.membus.trans_dist::Writeback 448 # Transaction distribution +system.membus.trans_dist::CleanEvict 139 # Transaction distribution +system.membus.trans_dist::ReadExReq 343 # Transaction distribution +system.membus.trans_dist::ReadExResp 343 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 15718 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 32709 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1056576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1056576 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 16675 # Request fanout histogram +system.membus.snoop_fanout::samples 16648 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 16675 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 16648 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 16675 # Request fanout histogram -system.membus.reqLayer0.occupancy 28309413 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 16648 # Request fanout histogram +system.membus.reqLayer0.occupancy 28374711 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 84107303 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 84025804 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 86fbc3533..8cbe9f760 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.361489 # Number of seconds simulated -sim_ticks 361488535500 # Number of ticks simulated -final_tick 361488535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 361488536500 # Number of ticks simulated +final_tick 361488536500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1224088 # Simulator instruction rate (inst/s) -host_op_rate 1224138 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1814798992 # Simulator tick rate (ticks/s) -host_mem_usage 426288 # Number of bytes of host memory used -host_seconds 199.19 # Real time elapsed on the host +host_inst_rate 1117046 # Simulator instruction rate (inst/s) +host_op_rate 1117092 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1656101101 # Simulator tick rate (ticks/s) +host_mem_usage 428664 # Number of bytes of host memory used +host_seconds 218.28 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -31,7 +31,7 @@ system.physmem.bw_total::cpu.data 2606821 # To system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 722977071 # number of cpu cycles simulated +system.cpu.numCycles 722977073 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 243825150 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 105711441 # nu system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 722977070.998000 # Number of busy cycles +system.cpu.num_busy_cycles 722977072.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29302884 # Number of branches fetched @@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction system.cpu.dcache.tags.replacements 935475 # number of replacements -system.cpu.dcache.tags.tagsinuse 3562.469039 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3562.469029 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 134366268500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469039 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 134366269500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469029 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -126,16 +126,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses system.cpu.dcache.overall_misses::total 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613736000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11613736000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12832738000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12832738000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12832738000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12832738000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) @@ -156,16 +156,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.386401 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.386401 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13658.140399 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13658.140399 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,16 +186,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567 system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720878000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720878000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720879000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720879000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1172292000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1172292000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 90000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 90000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893170000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11893170000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893170000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11893170000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893171000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11893171000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893171000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11893171000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses @@ -206,24 +206,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.385281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.385281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.386401 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.386401 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25097.238279 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25097.238279 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22500 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22500 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 25 # number of replacements -system.cpu.icache.tags.tagsinuse 725.412974 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 725.412972 # Cycle average of tags in use system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 725.412974 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 725.412972 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id @@ -304,13 +304,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53863.378685 system.cpu.icache.overall_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9730.625133 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9730.625106 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670093 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635586 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670068 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635584 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319455 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy @@ -458,6 +458,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.412969 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 233 # Transaction distribution @@ -473,14 +479,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1875953 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.001033 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1875953 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1875951 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1875953 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1873242500 # Layer occupancy (ticks) diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 40c2eacfb..9774ca6b0 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061602 # Nu sim_ticks 61602395500 # Number of ticks simulated final_tick 61602395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 83209 # Simulator instruction rate (inst/s) -host_op_rate 146518 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32444685 # Simulator tick rate (ticks/s) -host_mem_usage 451056 # Number of bytes of host memory used -host_seconds 1898.69 # Real time elapsed on the host +host_inst_rate 109389 # Simulator instruction rate (inst/s) +host_op_rate 192617 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42652748 # Simulator tick rate (ticks/s) +host_mem_usage 458300 # Number of bytes of host memory used +host_seconds 1444.28 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,12 +222,12 @@ system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Wr system.physmem.wrPerTurnAround::18 7 77.78% 88.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 1 11.11% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads -system.physmem.totQLat 132992250 # Total ticks spent queuing -system.physmem.totMemAccLat 701923500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 132940250 # Total ticks spent queuing +system.physmem.totMemAccLat 701871500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 151715000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4382.96 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4381.25 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23132.96 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23131.25 # Average memory access latency per DRAM burst system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s @@ -249,28 +249,28 @@ system.physmem_0.preEnergy 5960625 # En system.physmem_0.readEnergy 122031000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 991440 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2832651765 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34473588000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41469365190 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.233667 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57335439750 # Time in different power states +system.physmem_0.actBackEnergy 2832436305 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34473777000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41469338730 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.233237 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57335755750 # Time in different power states system.physmem_0.memoryStateTime::REF 2056860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2206407250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2206091250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 114207600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3020113080 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34309140000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41481582315 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.432156 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57061058750 # Time in different power states +system.physmem_1.actBackEnergy 3020027580 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34309215000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41481571815 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.431985 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57061184750 # Time in different power states system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2480990750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2480864750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 36908902 # Number of BP lookups system.cpu.branchPred.condPredicted 36908902 # Number of conditional branches predicted @@ -325,24 +325,24 @@ system.cpu.decode.SquashCycles 776598 # Nu system.cpu.decode.DecodedInsts 331225454 # Number of instructions handled by decode system.cpu.rename.SquashCycles 776598 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 18253440 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8529181 # Number of cycles rename is blocking +system.cpu.rename.BlockCycles 8529193 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 16791 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 40202739 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 55361222 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 325142962 # Number of instructions processed by rename +system.cpu.rename.UnblockCycles 55361210 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 325142958 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 1786 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 778279 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 48626761 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4947640 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 327068193 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 863737847 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 532004044 # Number of integer rename lookups +system.cpu.rename.LQFullEvents 48626800 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4947589 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 327068190 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 863737834 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 532004035 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 425 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 47855446 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 47855443 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 492 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 490 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 66412230 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 66412234 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 105336194 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 36169393 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 49402360 # Number of conflicting loads. @@ -358,13 +358,13 @@ system.cpu.iq.issued_per_cycle::samples 123139971 # Nu system.cpu.iq.issued_per_cycle::mean 2.485814 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 2.139103 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 30260082 24.57% 24.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19566754 15.89% 40.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 16687046 13.55% 54.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17331207 14.07% 68.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 14759369 11.99% 80.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12567445 10.21% 90.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6273255 5.09% 95.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30260078 24.57% 24.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19566758 15.89% 40.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 16687037 13.55% 54.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17331221 14.07% 68.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 14759373 11.99% 80.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12567435 10.21% 90.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6273256 5.09% 95.38% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 3904180 3.17% 98.55% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 1790633 1.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle @@ -401,7 +401,7 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.53% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3433517 86.49% 95.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3433516 86.49% 95.02% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 197609 4.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available @@ -441,15 +441,15 @@ system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Ty system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 306103022 # Type of FU issued system.cpu.iq.rate 2.484506 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3969923 # FU busy when requested +system.cpu.iq.fu_busy_cnt 3969922 # FU busy when requested system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 739361487 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 739361486 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 366454631 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 304282654 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 310039424 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 310039423 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 180 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 58196276 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -464,14 +464,14 @@ system.cpu.iew.lsq.thread0.cacheBlocked 141546 # Nu system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 776598 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 5329301 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3100547 # Number of cycles IEW is unblocking +system.cpu.iew.iewUnblockCycles 3100559 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 322303730 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 76830 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 105336194 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 36169393 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2588 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3102570 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3102582 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 41328 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 371679 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 414777 # Number of branches that were predicted not taken incorrectly @@ -485,7 +485,7 @@ system.cpu.iew.exec_refs 131430383 # nu system.cpu.iew.exec_branches 31401847 # Number of branches executed system.cpu.iew.exec_stores 33679798 # Number of stores executed system.cpu.iew.exec_rate 2.476825 # Inst execution rate -system.cpu.iew.wb_sent 304565841 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent 304565840 # cumulative count of insts sent to commit system.cpu.iew.wb_count 304282787 # cumulative count of insts written-back system.cpu.iew.wb_producers 230213925 # num instructions producing a value system.cpu.iew.wb_consumers 333861001 # num instructions consuming a value @@ -500,14 +500,14 @@ system.cpu.commit.committed_per_cycle::samples 117119203 system.cpu.commit.committed_per_cycle::mean 2.375293 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 3.092758 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52926109 45.19% 45.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15815586 13.50% 58.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52926112 45.19% 45.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 15815584 13.50% 58.69% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 10978620 9.37% 68.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8749339 7.47% 75.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1860123 1.59% 77.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1720770 1.47% 78.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 865930 0.74% 79.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 690109 0.59% 79.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8749335 7.47% 75.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1860124 1.59% 77.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1720771 1.47% 78.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 865932 0.74% 79.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 690108 0.59% 79.92% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 23512617 20.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle @@ -570,7 +570,7 @@ system.cpu.cpi_total 0.779834 # CP system.cpu.ipc 1.282325 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.282325 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 491477122 # number of integer regfile reads -system.cpu.int_regfile_writes 239432261 # number of integer regfile writes +system.cpu.int_regfile_writes 239432260 # number of integer regfile writes system.cpu.fp_regfile_reads 110 # number of floating regfile reads system.cpu.fp_regfile_writes 84 # number of floating regfile writes system.cpu.cc_regfile_reads 107533023 # number of cc regfile reads @@ -609,14 +609,14 @@ system.cpu.dcache.demand_misses::cpu.data 2785082 # n system.cpu.dcache.demand_misses::total 2785082 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2785082 # number of overall misses system.cpu.dcache.overall_misses::total 2785082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304422000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32304422000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956618494 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2956618494 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35261040494 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35261040494 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35261040494 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35261040494 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304507500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32304507500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956593494 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2956593494 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35261100994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35261100994 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35261100994 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35261100994 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 39416377 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 39416377 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) @@ -633,19 +633,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.039306 system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.929169 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.929169 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.498659 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.498659 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.683059 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12660.683059 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.683059 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12660.683059 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 221512 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.960940 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.960940 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.232497 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.232497 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.704781 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12660.704781 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.704781 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12660.704781 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 221514 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 43222 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.124983 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.125029 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -667,14 +667,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2076410 system.cpu.dcache.demand_mshr_misses::total 2076410 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2076410 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2076410 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24196094000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24196094000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995490995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26995490995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995490995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26995490995 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24196144500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24196144500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799371995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799371995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995516495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26995516495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995516495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26995516495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses @@ -683,22 +683,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305 system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.029305 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.223474 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.223474 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.040736 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.040736 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.040736 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.040736 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.248795 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.248795 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.374372 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.374372 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.053017 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.053017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.053017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.053017 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 53 # number of replacements -system.cpu.icache.tags.tagsinuse 825.040012 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 825.039934 # Cycle average of tags in use system.cpu.icache.tags.total_refs 27442569 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1013 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 27090.393880 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 825.040012 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 825.039934 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.402852 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.402852 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id @@ -721,12 +721,12 @@ system.cpu.icache.demand_misses::cpu.inst 1323 # n system.cpu.icache.demand_misses::total 1323 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1323 # number of overall misses system.cpu.icache.overall_misses::total 1323 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 97269000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 97269000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 97269000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 97269000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 97269000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 97269000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 97144000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 97144000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 97144000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 97144000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 97144000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 97144000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 27443892 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 27443892 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 27443892 # number of demand (read+write) accesses @@ -739,12 +739,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73521.541950 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73521.541950 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73521.541950 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73521.541950 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73521.541950 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73521.541950 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73427.059713 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73427.059713 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73427.059713 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73427.059713 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73427.059713 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73427.059713 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -765,34 +765,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1014 system.cpu.icache.demand_mshr_misses::total 1014 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1014 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77416000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 77416000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77416000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 77416000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77416000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 77416000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77391000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 77391000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77391000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 77391000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77391000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 77391000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76347.140039 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76347.140039 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76347.140039 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76347.140039 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76347.140039 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76347.140039 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76322.485207 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76322.485207 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76322.485207 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76322.485207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76322.485207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76322.485207 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 487 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20712.335895 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 20712.335726 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4035103 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 30405 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 132.711824 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19791.576431 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841934 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917530 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 19791.576352 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841852 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917522 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.603991 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020595 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.007505 # Average percentage of cache occupancy @@ -834,18 +834,18 @@ system.cpu.l2cache.demand_misses::total 30422 # nu system.cpu.l2cache.overall_misses::cpu.inst 998 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29424 # number of overall misses system.cpu.l2cache.overall_misses::total 30422 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118154500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2118154500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75720000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 75720000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32849000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 32849000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 75720000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2151003500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2226723500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 75720000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2151003500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2226723500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118128500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2118128500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75694000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 75694000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32848500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 32848500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 75694000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2150977000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2226671000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 75694000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2150977000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2226671000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 2066601 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 2066601 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) @@ -874,18 +874,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.014644 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984221 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014171 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014644 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.847921 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73044.847921 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75871.743487 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75871.743487 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77110.328638 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77110.328638 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75871.743487 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73103.707858 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73194.513839 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75871.743487 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73103.707858 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73194.513839 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73043.951307 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73043.951307 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75845.691383 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75845.691383 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77109.154930 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77109.154930 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75845.691383 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73102.807232 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73192.788114 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75845.691383 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73102.807232 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73192.788114 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -910,18 +910,18 @@ system.cpu.l2cache.demand_mshr_misses::total 30422 system.cpu.l2cache.overall_mshr_misses::cpu.inst 998 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29424 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 30422 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828174500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828174500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65740000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65740000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28589000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28589000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65740000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856763500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1922503500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65740000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856763500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1922503500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828148500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828148500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65714000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65714000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28588500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28588500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65714000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856737000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1922451000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65714000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856737000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1922451000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353337 # mshr miss rate for ReadExReq accesses @@ -936,19 +936,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.847921 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.847921 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.743487 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.743487 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67110.328638 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67110.328638 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.743487 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63103.707858 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63194.513839 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.743487 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63103.707858 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63194.513839 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63043.951307 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63043.951307 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65845.691383 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65845.691383 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67109.154930 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67109.154930 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65845.691383 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63102.807232 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63192.788114 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65845.691383 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63102.807232 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63192.788114 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4149790 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072370 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 42 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 279 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 1995354 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2066785 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6027 # Transaction distribution @@ -966,15 +972,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 265217536 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 487 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4150277 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.000117 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010832 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000088 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.009390 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4149790 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 487 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4149911 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 366 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4150277 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4141496000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) @@ -1005,7 +1011,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 30636 # Request fanout histogram -system.membus.reqLayer0.occupancy 42746500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 42746000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 160323750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index d40f8a71c..d05ee6d96 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu sim_ticks 365988859500 # Number of ticks simulated final_tick 365988859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 643347 # Simulator instruction rate (inst/s) -host_op_rate 1132831 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1490347920 # Simulator tick rate (ticks/s) -host_mem_usage 451472 # Number of bytes of host memory used -host_seconds 245.57 # Real time elapsed on the host +host_inst_rate 563395 # Simulator instruction rate (inst/s) +host_op_rate 992048 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1305133674 # Simulator tick rate (ticks/s) +host_mem_usage 455224 # Number of bytes of host memory used +host_seconds 280.42 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -449,6 +449,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.490660 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.060155 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.098389 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2062584 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 486 # Transaction distribution @@ -464,15 +470,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 264327616 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 313 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4130707 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.000076 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.008704 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000048 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.006906 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4130394 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 313 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4130510 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 197 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4130707 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4127679000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index 0819be4e4..91596dbee 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.412080 # Nu sim_ticks 412080064500 # Number of ticks simulated final_tick 412080064500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 229857 # Simulator instruction rate (inst/s) -host_op_rate 229857 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 154795079 # Simulator tick rate (ticks/s) -host_mem_usage 293864 # Number of bytes of host memory used -host_seconds 2662.10 # Real time elapsed on the host +host_inst_rate 310711 # Simulator instruction rate (inst/s) +host_op_rate 310711 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 209245414 # Simulator tick rate (ticks/s) +host_mem_usage 301844 # Number of bytes of host memory used +host_seconds 1969.36 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -704,6 +704,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68179.213483 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69564.106203 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69554.365436 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 5082760 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538418 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2391 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2391 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 1766182 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2633081 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 252234 # Transaction distribution @@ -719,15 +725,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 312573696 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 346897 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 5429657 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.063889 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.244556 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000440 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.020980 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5082760 93.61% 93.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 346897 6.39% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5427266 99.96% 99.96% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2391 0.04% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 5429657 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4881002000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 0b95ee278..7a68c081f 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.363605 # Number of seconds simulated -sim_ticks 363605295500 # Number of ticks simulated -final_tick 363605295500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.363600 # Number of seconds simulated +sim_ticks 363599502500 # Number of ticks simulated +final_tick 363599502500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163495 # Simulator instruction rate (inst/s) -host_op_rate 177087 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 117350463 # Simulator tick rate (ticks/s) -host_mem_usage 312624 # Number of bytes of host memory used -host_seconds 3098.46 # Real time elapsed on the host +host_inst_rate 226144 # Simulator instruction rate (inst/s) +host_op_rate 244944 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 162315109 # Simulator tick rate (ticks/s) +host_mem_usage 321124 # Number of bytes of host memory used +host_seconds 2240.08 # Real time elapsed on the host sim_insts 506582156 # Number of instructions simulated sim_ops 548695379 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 219264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 219456 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9004480 # Number of bytes read from this memory -system.physmem.bytes_read::total 9223744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6189056 # Number of bytes written to this memory -system.physmem.bytes_written::total 6189056 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3426 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 9223936 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219456 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6189376 # Number of bytes written to this memory +system.physmem.bytes_written::total 6189376 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3429 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 140695 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144121 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96704 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96704 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 603028 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24764436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25367463 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 603028 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 603028 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17021358 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17021358 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17021358 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 603028 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24764436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42388822 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144121 # Number of read requests accepted -system.physmem.writeReqs 96704 # Number of write requests accepted -system.physmem.readBursts 144121 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96704 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9217792 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue -system.physmem.bytesWritten 6187328 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9223744 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6189056 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 144124 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96709 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96709 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 603565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24764830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25368396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 603565 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 603565 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17022510 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17022510 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17022510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 603565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24764830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42390905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144124 # Number of read requests accepted +system.physmem.writeReqs 96709 # Number of write requests accepted +system.physmem.readBursts 144124 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96709 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9217920 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6016 # Total number of bytes read from write queue +system.physmem.bytesWritten 6188224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9223936 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6189376 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9327 # Per bank write bursts +system.physmem.perBankRdBursts::0 9331 # Per bank write bursts system.physmem.perBankRdBursts::1 8969 # Per bank write bursts -system.physmem.perBankRdBursts::2 9002 # Per bank write bursts +system.physmem.perBankRdBursts::2 9003 # Per bank write bursts system.physmem.perBankRdBursts::3 8675 # Per bank write bursts -system.physmem.perBankRdBursts::4 9455 # Per bank write bursts +system.physmem.perBankRdBursts::4 9453 # Per bank write bursts system.physmem.perBankRdBursts::5 9352 # Per bank write bursts -system.physmem.perBankRdBursts::6 8946 # Per bank write bursts +system.physmem.perBankRdBursts::6 8945 # Per bank write bursts system.physmem.perBankRdBursts::7 8102 # Per bank write bursts system.physmem.perBankRdBursts::8 8582 # Per bank write bursts -system.physmem.perBankRdBursts::9 8671 # Per bank write bursts +system.physmem.perBankRdBursts::9 8674 # Per bank write bursts system.physmem.perBankRdBursts::10 8765 # Per bank write bursts -system.physmem.perBankRdBursts::11 9475 # Per bank write bursts -system.physmem.perBankRdBursts::12 9349 # Per bank write bursts -system.physmem.perBankRdBursts::13 9515 # Per bank write bursts -system.physmem.perBankRdBursts::14 8723 # Per bank write bursts -system.physmem.perBankRdBursts::15 9120 # Per bank write bursts -system.physmem.perBankWrBursts::0 6189 # Per bank write bursts +system.physmem.perBankRdBursts::11 9476 # Per bank write bursts +system.physmem.perBankRdBursts::12 9348 # Per bank write bursts +system.physmem.perBankRdBursts::13 9513 # Per bank write bursts +system.physmem.perBankRdBursts::14 8719 # Per bank write bursts +system.physmem.perBankRdBursts::15 9123 # Per bank write bursts +system.physmem.perBankWrBursts::0 6195 # Per bank write bursts system.physmem.perBankWrBursts::1 6094 # Per bank write bursts -system.physmem.perBankWrBursts::2 6010 # Per bank write bursts +system.physmem.perBankWrBursts::2 6011 # Per bank write bursts system.physmem.perBankWrBursts::3 5821 # Per bank write bursts -system.physmem.perBankWrBursts::4 6183 # Per bank write bursts -system.physmem.perBankWrBursts::5 6186 # Per bank write bursts +system.physmem.perBankWrBursts::4 6181 # Per bank write bursts +system.physmem.perBankWrBursts::5 6188 # Per bank write bursts system.physmem.perBankWrBursts::6 6015 # Per bank write bursts -system.physmem.perBankWrBursts::7 5498 # Per bank write bursts -system.physmem.perBankWrBursts::8 5738 # Per bank write bursts -system.physmem.perBankWrBursts::9 5829 # Per bank write bursts +system.physmem.perBankWrBursts::7 5499 # Per bank write bursts +system.physmem.perBankWrBursts::8 5743 # Per bank write bursts +system.physmem.perBankWrBursts::9 5830 # Per bank write bursts system.physmem.perBankWrBursts::10 5965 # Per bank write bursts system.physmem.perBankWrBursts::11 6463 # Per bank write bursts -system.physmem.perBankWrBursts::12 6313 # Per bank write bursts +system.physmem.perBankWrBursts::12 6312 # Per bank write bursts system.physmem.perBankWrBursts::13 6285 # Per bank write bursts -system.physmem.perBankWrBursts::14 6005 # Per bank write bursts -system.physmem.perBankWrBursts::15 6083 # Per bank write bursts +system.physmem.perBankWrBursts::14 6003 # Per bank write bursts +system.physmem.perBankWrBursts::15 6086 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 363605269500 # Total gap between requests +system.physmem.totGap 363599476500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144121 # Read request sizes (log2) +system.physmem.readPktSize::6 144124 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96704 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143663 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96709 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,34 +144,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5541 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 5659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5691 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 5701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -193,53 +193,55 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65251 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 236.074482 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.620272 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.651300 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24697 37.85% 37.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18374 28.16% 66.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6917 10.60% 76.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7938 12.17% 88.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2038 3.12% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1147 1.76% 93.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 769 1.18% 94.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 621 0.95% 95.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2750 4.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65251 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5585 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.786571 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 381.841879 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5581 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65302 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 235.912652 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.372535 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.914583 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24788 37.96% 37.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18406 28.19% 66.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6849 10.49% 76.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7905 12.11% 88.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2084 3.19% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1111 1.70% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 761 1.17% 94.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 643 0.98% 95.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2755 4.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65302 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5583 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.797421 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 381.883100 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5579 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5585 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5585 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.310116 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.217866 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.213646 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2534 45.37% 45.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 92 1.65% 47.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 2660 47.63% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 156 2.79% 97.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 36 0.64% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 18 0.32% 98.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 16 0.29% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 9 0.16% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 7 0.13% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 10 0.18% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 4 0.07% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.07% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 4 0.07% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 6 0.11% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.04% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 4 0.07% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 3 0.05% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 4 0.07% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 2 0.04% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 2 0.04% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5583 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5583 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.318825 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.224966 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.238810 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2516 45.07% 45.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 99 1.77% 46.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 2663 47.70% 94.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 163 2.92% 97.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 38 0.68% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 18 0.32% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 14 0.25% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 8 0.14% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 6 0.11% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 9 0.16% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.09% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.07% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 4 0.07% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 6 0.11% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.04% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 3 0.05% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.04% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 4 0.07% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 2 0.04% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 2 0.04% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 2 0.04% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 1 0.02% 99.82% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::43 1 0.02% 99.84% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44 1 0.02% 99.86% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::47 1 0.02% 99.87% # Writes before turning the bus around for reads @@ -249,13 +251,13 @@ system.physmem.wrPerTurnAround::53 1 0.02% 99.95% # Wr system.physmem.wrPerTurnAround::55 1 0.02% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::61 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::62 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5585 # Writes before turning the bus around for reads -system.physmem.totQLat 1541292750 # Total ticks spent queuing -system.physmem.totMemAccLat 4241817750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720140000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10701.34 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5583 # Writes before turning the bus around for reads +system.physmem.totQLat 1538433000 # Total ticks spent queuing +system.physmem.totMemAccLat 4238995500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720150000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10681.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29451.34 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29431.34 # Average memory access latency per DRAM burst system.physmem.avgRdBW 25.35 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 25.37 # Average system read bandwidth in MiByte/s @@ -265,50 +267,50 @@ system.physmem.busUtil 0.33 # Da system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.51 # Average write queue length when enqueuing -system.physmem.readRowHits 110876 # Number of row buffer hits during reads -system.physmem.writeRowHits 64571 # Number of row buffer hits during writes +system.physmem.avgWrQLen 19.80 # Average write queue length when enqueuing +system.physmem.readRowHits 110870 # Number of row buffer hits during reads +system.physmem.writeRowHits 64542 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.77 # Row buffer hit rate for writes -system.physmem.avgGap 1509831.91 # Average gap between requests -system.physmem.pageHitRate 72.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 248028480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135333000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 560164800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 310884480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47382783300 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 176597692500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 248983621440 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.768610 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 293478926000 # Time in different power states -system.physmem_0.memoryStateTime::REF 12141480000 # Time in different power states +system.physmem.writeRowHitRate 66.74 # Row buffer hit rate for writes +system.physmem.avgGap 1509757.70 # Average gap between requests +system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 248293080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135477375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 560086800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 310832640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23748226320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47486002320 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 176502477750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 248991396285 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.804658 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 293320694250 # Time in different power states +system.physmem_0.memoryStateTime::REF 12141220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 57982170250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 58133810750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 245080080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133724250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 563004000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 315375120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 46983341835 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 176948079750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 248937339915 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.641324 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 294063578500 # Time in different power states -system.physmem_1.memoryStateTime::REF 12141480000 # Time in different power states +system.physmem_1.actEnergy 245148120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133761375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562957200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 315401040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23748226320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46957937220 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 176965692750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 248929124025 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.633389 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 294092512000 # Time in different power states +system.physmem_1.memoryStateTime::REF 12141220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 57397836750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57361058000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 131896308 # Number of BP lookups -system.cpu.branchPred.condPredicted 98031712 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6139352 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68410049 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64397752 # Number of BTB hits +system.cpu.branchPred.lookups 131895360 # Number of BP lookups +system.cpu.branchPred.condPredicted 98029927 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6139026 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68388068 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64396789 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.134930 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9981293 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 18014 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.163779 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9981632 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 18119 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -427,98 +429,98 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 727210591 # number of cpu cycles simulated +system.cpu.numCycles 727199005 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582156 # Number of instructions committed system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13199856 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13199573 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.435524 # CPI: cycles per instruction -system.cpu.ipc 0.696610 # IPC: instructions per cycle -system.cpu.tickCycles 690727435 # Number of cycles that the object actually ticked -system.cpu.idleCycles 36483156 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139971 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.789837 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171168979 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1144067 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.614471 # Average number of references to valid blocks. +system.cpu.cpi 1.435501 # CPI: cycles per instruction +system.cpu.ipc 0.696621 # IPC: instructions per cycle +system.cpu.tickCycles 690715590 # Number of cycles that the object actually ticked +system.cpu.idleCycles 36483415 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139984 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.789434 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171168644 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1144080 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.612478 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.789837 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.789434 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993845 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3499 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346593001 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346593001 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114650515 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114650515 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53538628 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538628 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2754 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2754 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 346592332 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346592332 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114650184 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114650184 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53538625 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538625 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2753 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2753 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168189143 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168189143 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168191897 # number of overall hits -system.cpu.dcache.overall_hits::total 168191897 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 854793 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854793 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 700678 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700678 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 17 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 17 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1555471 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1555471 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1555488 # number of overall misses -system.cpu.dcache.overall_misses::total 1555488 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024452000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14024452000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21892214000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21892214000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35916666000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35916666000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35916666000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35916666000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115505308 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115505308 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168188809 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168188809 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168191562 # number of overall hits +system.cpu.dcache.overall_hits::total 168191562 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 854786 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854786 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700681 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700681 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1555467 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1555467 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1555482 # number of overall misses +system.cpu.dcache.overall_misses::total 1555482 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024022500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14024022500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21893600500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21893600500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35917623000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35917623000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35917623000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35917623000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115504970 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115504970 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2771 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2771 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2768 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2768 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169744614 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169744614 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169747385 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169747385 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169744276 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169744276 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169747044 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169747044 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007400 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007400 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.006135 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.006135 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005419 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005419 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.009164 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.009164 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009164 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009164 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.840019 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.840019 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31244.329064 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31244.329064 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23090.540422 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23090.540422 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23090.288064 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23090.288064 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.471912 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.471912 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31246.174079 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31246.174079 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23091.215050 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23091.215050 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23090.992374 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23090.992374 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -527,111 +529,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068574 # number of writebacks -system.cpu.dcache.writebacks::total 1068574 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66907 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66907 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344511 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344511 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 411418 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411418 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 411418 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411418 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787886 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787886 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356167 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356167 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 14 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 14 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1144053 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1144053 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1144067 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1144067 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12337562000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12337562000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11120015500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11120015500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1028000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1028000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23457577500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23457577500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23458605500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23458605500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1068583 # number of writebacks +system.cpu.dcache.writebacks::total 1068583 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66886 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66886 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344513 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344513 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 411399 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411399 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 411399 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411399 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787900 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 787900 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356168 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356168 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1144068 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1144068 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1144080 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1144080 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12337991000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12337991000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11121217500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11121217500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 946000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 946000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23459208500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23459208500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23460154500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23460154500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006821 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006821 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006567 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006567 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005052 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005052 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004335 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004335 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006740 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006740 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15659.069967 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15659.069967 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31221.352624 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31221.352624 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 73428.571429 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 73428.571429 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20503.925517 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20503.925517 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20504.573159 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20504.573159 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15659.336210 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15659.336210 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31224.639777 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31224.639777 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78833.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78833.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20505.082303 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20505.082303 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20505.694095 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20505.694095 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 17719 # number of replacements -system.cpu.icache.tags.tagsinuse 1188.326281 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199317838 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19591 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10173.949160 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 17702 # number of replacements +system.cpu.icache.tags.tagsinuse 1188.317648 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 199314883 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19574 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10182.634260 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1188.326281 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.580237 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.580237 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1188.317648 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.580233 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.580233 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 303 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1407 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 306 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 398694449 # Number of tag accesses -system.cpu.icache.tags.data_accesses 398694449 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 199317838 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 199317838 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 199317838 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 199317838 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 199317838 # number of overall hits -system.cpu.icache.overall_hits::total 199317838 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19591 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19591 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19591 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19591 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19591 # number of overall misses -system.cpu.icache.overall_misses::total 19591 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 490899000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 490899000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 490899000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 490899000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 490899000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 490899000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 199337429 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 199337429 # 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number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19574 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19574 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19574 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19574 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19574 # number of overall misses +system.cpu.icache.overall_misses::total 19574 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 491333500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 491333500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 491333500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 491333500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 491333500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 491333500 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.175284 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.175284 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050631 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050631 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175284 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.122989 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123868 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175284 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.122989 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123868 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78407.432386 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78407.432386 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79364.471000 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79364.471000 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82301.792879 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82301.792879 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79364.471000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79511.179100 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79507.686971 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79364.471000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79511.179100 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79507.686971 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -770,8 +772,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 96704 # number of writebacks -system.cpu.l2cache.writebacks::total 96704 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 96709 # number of writebacks +system.cpu.l2cache.writebacks::total 96709 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits @@ -782,114 +784,120 @@ system.cpu.l2cache.demand_mshr_hits::total 16 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1193 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1193 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1197 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1197 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100829 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 100829 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3426 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3426 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3429 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3429 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39866 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39866 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3426 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3429 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 140695 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144121 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3426 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144124 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3429 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 140695 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144121 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6896262500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6896262500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 237598000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 237598000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2886048500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2886048500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 237598000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9782311000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10019909000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 237598000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9782311000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10019909000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 144124 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6897453000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6897453000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 237701500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 237701500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2882229000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2882229000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 237701500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9779682000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10017383500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 237701500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9779682000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10017383500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282896 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282896 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.174876 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.174876 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050614 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050614 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174876 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122978 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123852 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174876 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122978 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123852 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68395.625267 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68395.625267 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69351.430239 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69351.430239 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72393.731501 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72393.731501 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69351.430239 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69528.490707 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69524.281680 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69351.430239 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69528.490707 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69524.281680 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282894 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282894 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.175181 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.175181 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050613 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050613 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.175181 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123855 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.175181 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123855 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68407.432386 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68407.432386 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69320.939049 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69320.939049 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72297.923042 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72297.923042 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69320.939049 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69509.804897 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69505.311399 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69320.939049 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69509.804897 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69505.311399 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 807241 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1165278 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 98858 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356417 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356417 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 19591 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 787650 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56664 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423421 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3480085 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1253824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141609024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142862848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 111367 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2432715 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.045779 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.209005 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 2321340 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1157756 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4922 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2616 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2613 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 807234 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1165292 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 98842 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356420 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356420 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 19574 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 787660 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56613 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423459 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3480072 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141610432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142863168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 111370 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2432710 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005152 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.071609 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2321348 95.42% 95.42% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 111367 4.58% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2420180 99.48% 99.48% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12527 0.51% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2432715 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2229248000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2432710 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2229253000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29387997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 29379463 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1716107486 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1716126986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadResp 43292 # Transaction distribution -system.membus.trans_dist::Writeback 96704 # Transaction distribution -system.membus.trans_dist::CleanEvict 13244 # Transaction distribution +system.membus.trans_dist::ReadResp 43295 # Transaction distribution +system.membus.trans_dist::Writeback 96709 # Transaction distribution +system.membus.trans_dist::CleanEvict 13242 # Transaction distribution system.membus.trans_dist::ReadExReq 100829 # Transaction distribution system.membus.trans_dist::ReadExResp 100829 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 43292 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 398190 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15412800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15412800 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 43295 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398199 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 398199 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15413312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15413312 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 254069 # Request fanout histogram +system.membus.snoop_fanout::samples 254075 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 254069 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 254075 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 254069 # Request fanout histogram -system.membus.reqLayer0.occupancy 683631500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 254075 # Request fanout histogram +system.membus.reqLayer0.occupancy 683661500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 765040250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 765035500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index c93b4b47a..153b00611 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233332 # Number of seconds simulated -sim_ticks 233331881000 # Number of ticks simulated -final_tick 233331881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233306 # Number of seconds simulated +sim_ticks 233306027000 # Number of ticks simulated +final_tick 233306027000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137799 # Simulator instruction rate (inst/s) -host_op_rate 149285 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63638999 # Simulator tick rate (ticks/s) -host_mem_usage 320760 # Number of bytes of host memory used -host_seconds 3666.49 # Real time elapsed on the host +host_inst_rate 128535 # Simulator instruction rate (inst/s) +host_op_rate 139249 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59354207 # Simulator tick rate (ticks/s) +host_mem_usage 322028 # Number of bytes of host memory used +host_seconds 3930.74 # Real time elapsed on the host sim_insts 505237724 # Number of instructions simulated sim_ops 547350945 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 689792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9194752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16497856 # Number of bytes read from this memory -system.physmem.bytes_read::total 26382400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 689792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 689792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18714240 # Number of bytes written to this memory -system.physmem.bytes_written::total 18714240 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10778 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143668 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257779 # Number of read requests responded to by this memory -system.physmem.num_reads::total 412225 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292410 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292410 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2956270 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39406325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70705537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 113068132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2956270 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2956270 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80204385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80204385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80204385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2956270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39406325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70705537 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 193272517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 412225 # Number of read requests accepted -system.physmem.writeReqs 292410 # Number of write requests accepted -system.physmem.readBursts 412225 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292410 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26244608 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 137792 # Total number of bytes read from write queue -system.physmem.bytesWritten 18711808 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26382400 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18714240 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2153 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26528 # Per bank write bursts -system.physmem.perBankRdBursts::1 25539 # Per bank write bursts -system.physmem.perBankRdBursts::2 25303 # Per bank write bursts -system.physmem.perBankRdBursts::3 24713 # Per bank write bursts -system.physmem.perBankRdBursts::4 27194 # Per bank write bursts -system.physmem.perBankRdBursts::5 26607 # Per bank write bursts -system.physmem.perBankRdBursts::6 24941 # Per bank write bursts -system.physmem.perBankRdBursts::7 24442 # Per bank write bursts -system.physmem.perBankRdBursts::8 25767 # Per bank write bursts -system.physmem.perBankRdBursts::9 24723 # Per bank write bursts -system.physmem.perBankRdBursts::10 25091 # Per bank write bursts -system.physmem.perBankRdBursts::11 26187 # Per bank write bursts -system.physmem.perBankRdBursts::12 26462 # Per bank write bursts -system.physmem.perBankRdBursts::13 26013 # Per bank write bursts -system.physmem.perBankRdBursts::14 25052 # Per bank write bursts -system.physmem.perBankRdBursts::15 25510 # Per bank write bursts -system.physmem.perBankWrBursts::0 18779 # Per bank write bursts -system.physmem.perBankWrBursts::1 18326 # Per bank write bursts -system.physmem.perBankWrBursts::2 18027 # Per bank write bursts -system.physmem.perBankWrBursts::3 17939 # Per bank write bursts -system.physmem.perBankWrBursts::4 18703 # Per bank write bursts -system.physmem.perBankWrBursts::5 18353 # Per bank write bursts -system.physmem.perBankWrBursts::6 17755 # Per bank write bursts -system.physmem.perBankWrBursts::7 17808 # Per bank write bursts -system.physmem.perBankWrBursts::8 18074 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 683648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9174464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16490944 # Number of bytes read from this memory +system.physmem.bytes_read::total 26349056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 683648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 683648 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18702784 # Number of bytes written to this memory +system.physmem.bytes_written::total 18702784 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10682 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143351 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257671 # Number of read requests responded to by this memory +system.physmem.num_reads::total 411704 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292231 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292231 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2930263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39323733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70683746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 112937742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2930263 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2930263 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80164170 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80164170 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80164170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2930263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39323733 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70683746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193101912 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 411704 # Number of read requests accepted +system.physmem.writeReqs 292231 # Number of write requests accepted +system.physmem.readBursts 411704 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292231 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26211648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 137408 # Total number of bytes read from write queue +system.physmem.bytesWritten 18700672 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26349056 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18702784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2147 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 26604 # Per bank write bursts +system.physmem.perBankRdBursts::1 25479 # Per bank write bursts +system.physmem.perBankRdBursts::2 25122 # Per bank write bursts +system.physmem.perBankRdBursts::3 24753 # Per bank write bursts +system.physmem.perBankRdBursts::4 27168 # Per bank write bursts +system.physmem.perBankRdBursts::5 26312 # Per bank write bursts +system.physmem.perBankRdBursts::6 25243 # Per bank write bursts +system.physmem.perBankRdBursts::7 24096 # Per bank write bursts +system.physmem.perBankRdBursts::8 25848 # Per bank write bursts +system.physmem.perBankRdBursts::9 24676 # Per bank write bursts +system.physmem.perBankRdBursts::10 25150 # Per bank write bursts +system.physmem.perBankRdBursts::11 26103 # Per bank write bursts +system.physmem.perBankRdBursts::12 26513 # Per bank write bursts +system.physmem.perBankRdBursts::13 25940 # Per bank write bursts +system.physmem.perBankRdBursts::14 25062 # Per bank write bursts +system.physmem.perBankRdBursts::15 25488 # Per bank write bursts +system.physmem.perBankWrBursts::0 18828 # Per bank write bursts +system.physmem.perBankWrBursts::1 18294 # Per bank write bursts +system.physmem.perBankWrBursts::2 17806 # Per bank write bursts +system.physmem.perBankWrBursts::3 17978 # Per bank write bursts +system.physmem.perBankWrBursts::4 18719 # Per bank write bursts +system.physmem.perBankWrBursts::5 18281 # Per bank write bursts +system.physmem.perBankWrBursts::6 17995 # Per bank write bursts +system.physmem.perBankWrBursts::7 17635 # Per bank write bursts +system.physmem.perBankWrBursts::8 18144 # Per bank write bursts system.physmem.perBankWrBursts::9 17824 # Per bank write bursts -system.physmem.perBankWrBursts::10 18093 # Per bank write bursts -system.physmem.perBankWrBursts::11 18724 # Per bank write bursts -system.physmem.perBankWrBursts::12 18814 # Per bank write bursts -system.physmem.perBankWrBursts::13 18339 # Per bank write bursts -system.physmem.perBankWrBursts::14 18411 # Per bank write bursts -system.physmem.perBankWrBursts::15 18403 # Per bank write bursts +system.physmem.perBankWrBursts::10 18107 # Per bank write bursts +system.physmem.perBankWrBursts::11 18749 # Per bank write bursts +system.physmem.perBankWrBursts::12 18847 # Per bank write bursts +system.physmem.perBankWrBursts::13 18260 # Per bank write bursts +system.physmem.perBankWrBursts::14 18418 # Per bank write bursts +system.physmem.perBankWrBursts::15 18313 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 233331863000 # Total gap between requests +system.physmem.totGap 233306009000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 412225 # Read request sizes (log2) +system.physmem.readPktSize::6 411704 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292410 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 311682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4415 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292231 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 311101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 49294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,30 +148,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 20067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -197,102 +197,103 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 307255 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 146.312346 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.902161 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 182.114345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 184693 60.11% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 81851 26.64% 86.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16642 5.42% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7320 2.38% 94.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4729 1.54% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2259 0.74% 96.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1737 0.57% 97.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1607 0.52% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6417 2.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 307255 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17328 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.664070 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 116.589701 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 17327 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 306850 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 146.361336 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.891492 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 182.277612 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 184544 60.14% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 81708 26.63% 86.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16503 5.38% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7231 2.36% 94.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4881 1.59% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2237 0.73% 96.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1756 0.57% 97.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1532 0.50% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6458 2.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 306850 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17319 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.647035 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 116.821350 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 17318 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17328 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17328 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.872807 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.831610 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.219578 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 10506 60.63% 60.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 279 1.61% 62.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5596 32.29% 94.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 616 3.55% 98.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 141 0.81% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 60 0.35% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 44 0.25% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 41 0.24% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 25 0.14% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 12 0.07% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 7 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17328 # Writes before turning the bus around for reads -system.physmem.totQLat 9022211140 # Total ticks spent queuing -system.physmem.totMemAccLat 16711061140 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2050360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22001.53 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17319 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17319 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.871528 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.829762 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.229266 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10538 60.85% 60.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 299 1.73% 62.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5524 31.90% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 601 3.47% 97.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 136 0.79% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 86 0.50% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 52 0.30% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 38 0.22% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 24 0.14% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 14 0.08% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17319 # Writes before turning the bus around for reads +system.physmem.totQLat 9105020732 # Total ticks spent queuing +system.physmem.totMemAccLat 16784214482 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2047785000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22231.39 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40751.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 112.48 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.19 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 113.07 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.20 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40981.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 112.35 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 80.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 112.94 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 80.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.51 # Data bus utilization in percentage +system.physmem.busUtil 1.50 # Data bus utilization in percentage system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.59 # Average write queue length when enqueuing -system.physmem.readRowHits 299444 # Number of row buffer hits during reads -system.physmem.writeRowHits 95740 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.74 # Row buffer hit rate for writes -system.physmem.avgGap 331138.62 # Average gap between requests -system.physmem.pageHitRate 56.26 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1156823640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 631203375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1601035800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 944071200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15240017520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 75187551735 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 74044498500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 168805201770 # Total energy per rank (pJ) -system.physmem_0.averagePower 723.458661 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 122654182736 # Time in different power states -system.physmem_0.memoryStateTime::REF 7791420000 # Time in different power states +system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.84 # Average write queue length when enqueuing +system.physmem.readRowHits 299267 # Number of row buffer hits during reads +system.physmem.writeRowHits 95628 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes +system.physmem.avgGap 331431.18 # Average gap between requests +system.physmem.pageHitRate 56.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1155833280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 630663000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1596964200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 942956640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15237983280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 74824379370 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 74344372500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 168733152270 # Total energy per rank (pJ) +system.physmem_0.averagePower 723.246471 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 123152752220 # Time in different power states +system.physmem_0.memoryStateTime::REF 7790380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 102885452264 # Time in different power states +system.physmem_0.memoryStateTime::ACT 102358687280 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1166024160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 636223500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1597377600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 950499360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15240017520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 74554879950 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 74599507500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 168744529590 # Total energy per rank (pJ) -system.physmem_1.averagePower 723.198461 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 123580654566 # Time in different power states -system.physmem_1.memoryStateTime::REF 7791420000 # Time in different power states +system.physmem_1.actEnergy 1163673000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 634940625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1597073400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 950279040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15237983280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 74177760825 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 74911581750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 168673291920 # Total energy per rank (pJ) +system.physmem_1.averagePower 722.989890 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 124105976502 # Time in different power states +system.physmem_1.memoryStateTime::REF 7790380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 101958813184 # Time in different power states +system.physmem_1.memoryStateTime::ACT 101406021498 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 175090137 # Number of BP lookups -system.cpu.branchPred.condPredicted 131338905 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7443529 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90540858 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83879425 # Number of BTB hits +system.cpu.branchPred.lookups 175092094 # Number of BP lookups +system.cpu.branchPred.condPredicted 131341607 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7444018 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90535143 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83876326 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.642622 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12110692 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104166 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.645047 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12109430 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104164 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,129 +412,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 466663763 # number of cpu cycles simulated +system.cpu.numCycles 466612055 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7839248 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 731808788 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175090137 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95990117 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 450472274 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14939659 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5656 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 157 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 14269 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236720425 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34587 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 465801433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.701462 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.179511 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7841296 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731804732 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175092094 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95985756 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 450426990 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14940841 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5959 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 183 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13996 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236719309 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34673 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 465758844 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.701594 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.179451 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 93869731 20.15% 20.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132699774 28.49% 48.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57852108 12.42% 61.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181379820 38.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 93829138 20.15% 20.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132701430 28.49% 48.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57853582 12.42% 61.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181374694 38.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 465801433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.375195 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.568171 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32373679 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 117343382 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 287062106 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22041011 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6981255 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24049971 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496386 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 715809364 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 30003912 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6981255 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63434666 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 54211510 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40338612 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276664591 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24170799 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686600417 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13340367 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9416739 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2386420 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1670076 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1927738 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 831025477 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3019202538 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 723925996 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 465758844 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.375241 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.568337 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32366390 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 117283842 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 287098365 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22028374 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6981873 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24050011 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496385 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715808617 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 30003155 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6981873 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63420619 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 54156177 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40346363 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276695654 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24158158 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686602803 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13340804 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9402338 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2387140 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1669358 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1928954 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 831026912 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3019223277 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723937000 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 176901726 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544701 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1534906 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42308307 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143530339 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67981565 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12860716 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11266999 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668170903 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978331 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610248763 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5854866 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 123798289 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 319264737 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 699 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 465801433 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.310105 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101429 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176903161 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544702 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1535188 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42285800 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143529225 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67986348 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12855797 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11202653 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668172379 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978330 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610256171 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5859842 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 123799764 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 319235639 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 698 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 465758844 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.310241 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101448 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 148653685 31.91% 31.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 101184506 21.72% 53.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145749505 31.29% 84.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63290175 13.59% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6923088 1.49% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 474 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 148618613 31.91% 31.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 101179975 21.72% 53.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145721974 31.29% 84.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63321350 13.60% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6916462 1.48% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 470 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 465801433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 465758844 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71924616 52.97% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44553347 32.81% 85.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19296722 14.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71923603 52.95% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44560845 32.81% 85.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19351011 14.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413148587 67.70% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 351752 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413149972 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351777 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued @@ -561,84 +562,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134215566 21.99% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62532855 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134213690 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62540729 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610248763 # Type of FU issued -system.cpu.iq.rate 1.307684 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135774715 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222491 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1827928247 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 794975703 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594980555 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 610256171 # Type of FU issued +system.cpu.iq.rate 1.307845 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135835489 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222588 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1827966224 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 794978756 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594986581 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 746023301 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 746091483 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7276983 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 7271635 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27645583 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25497 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28922 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11121088 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27644469 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25562 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29008 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11125871 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225125 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22421 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225728 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22400 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6981255 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22978687 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 924846 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672636723 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6981873 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22924718 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 919849 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672638124 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143530339 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67981565 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489789 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 258799 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 529739 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28922 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3821583 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3731049 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7552632 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599397786 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129576337 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10850977 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 143529225 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67986348 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489788 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 258699 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 524927 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29008 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3821848 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3731355 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7553203 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599403304 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129574600 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10852867 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1487489 # number of nop insts executed -system.cpu.iew.exec_refs 190533026 # number of memory reference insts executed -system.cpu.iew.exec_branches 131372234 # Number of branches executed -system.cpu.iew.exec_stores 60956689 # Number of stores executed -system.cpu.iew.exec_rate 1.284432 # Inst execution rate -system.cpu.iew.wb_sent 596275489 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594980571 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349907425 # num instructions producing a value -system.cpu.iew.wb_consumers 570632122 # num instructions consuming a value +system.cpu.iew.exec_nop 1487415 # number of nop insts executed +system.cpu.iew.exec_refs 190539133 # number of memory reference insts executed +system.cpu.iew.exec_branches 131373270 # Number of branches executed +system.cpu.iew.exec_stores 60964533 # Number of stores executed +system.cpu.iew.exec_rate 1.284586 # Inst execution rate +system.cpu.iew.wb_sent 596281070 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594986597 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349903865 # num instructions producing a value +system.cpu.iew.wb_consumers 570650112 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.274966 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613193 # average fanout of values written-back +system.cpu.iew.wb_rate 1.275121 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613167 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 110027797 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 110031903 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6954955 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 448686365 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.222892 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.888131 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6955471 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 448643201 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.223009 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.887847 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 219669318 48.96% 48.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116312485 25.92% 74.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43742979 9.75% 84.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23278779 5.19% 89.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11577691 2.58% 92.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7777719 1.73% 94.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8261206 1.84% 95.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4236050 0.94% 96.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13830138 3.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 219610457 48.95% 48.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116308832 25.92% 74.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43746420 9.75% 84.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23291517 5.19% 89.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11578245 2.58% 92.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7791027 1.74% 94.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8269909 1.84% 95.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4243315 0.95% 96.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13803479 3.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 448686365 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 448643201 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581608 # Number of instructions committed system.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -684,182 +685,182 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694829 # Class of committed instruction -system.cpu.commit.bw_lim_events 13830138 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1093571715 # The number of ROB reads -system.cpu.rob.rob_writes 1334590067 # The number of ROB writes -system.cpu.timesIdled 13966 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 862330 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13803479 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1093559316 # The number of ROB reads +system.cpu.rob.rob_writes 1334598854 # The number of ROB writes +system.cpu.timesIdled 13995 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 853211 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237724 # Number of Instructions Simulated system.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.923652 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.923652 # CPI: Total CPI of All Threads -system.cpu.ipc 1.082659 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.082659 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611088796 # number of integer regfile reads -system.cpu.int_regfile_writes 328119086 # number of integer regfile writes +system.cpu.cpi 0.923550 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.923550 # CPI: Total CPI of All Threads +system.cpu.ipc 1.082779 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.082779 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611100755 # number of integer regfile reads +system.cpu.int_regfile_writes 328116502 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170176811 # number of cc regfile reads -system.cpu.cc_regfile_writes 376539852 # number of cc regfile writes -system.cpu.misc_regfile_reads 217970841 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170188783 # number of cc regfile reads +system.cpu.cc_regfile_writes 376538117 # number of cc regfile writes +system.cpu.misc_regfile_reads 217976814 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2820945 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.631358 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169354520 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2821457 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 60.023782 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 498530000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.631358 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999280 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999280 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2820876 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.631746 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169355780 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2821388 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.025697 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 498153000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.631746 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999281 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999281 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356242117 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356242117 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114648793 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114648793 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51725790 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51725790 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2786 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2786 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 356248226 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356248226 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114651895 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114651895 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51723951 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51723951 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2787 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2787 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 166374583 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166374583 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 166377369 # number of overall hits -system.cpu.dcache.overall_hits::total 166377369 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4842267 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4842267 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2513516 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2513516 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 166375846 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166375846 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166378633 # number of overall hits +system.cpu.dcache.overall_hits::total 166378633 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4842252 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4842252 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2515355 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2515355 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7355783 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7355783 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7355794 # number of overall misses -system.cpu.dcache.overall_misses::total 7355794 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 56187510500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 56187510500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19050466441 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19050466441 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1271500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1271500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75237976941 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75237976941 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75237976941 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75237976941 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119491060 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119491060 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7357607 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7357607 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7357619 # number of overall misses +system.cpu.dcache.overall_misses::total 7357619 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 56173880000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 56173880000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19052445440 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19052445440 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1310000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1310000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75226325440 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75226325440 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75226325440 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75226325440 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119494147 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119494147 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2797 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2797 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2799 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2799 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173730366 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173730366 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173733163 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173733163 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040524 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040524 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046341 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046341 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003933 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.003933 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173733453 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173733453 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173736252 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173736252 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040523 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040523 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046375 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046375 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004287 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.004287 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042340 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042340 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042340 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042340 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11603.554802 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11603.554802 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7579.210334 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7579.210334 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19265.151515 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19265.151515 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10228.411706 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10228.411706 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10228.396410 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10228.396410 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 19 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 931670 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221105 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.213699 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.042350 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042350 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042349 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042349 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11600.775837 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11600.775837 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7574.455868 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7574.455868 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19848.484848 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19848.484848 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10224.292415 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10224.292415 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10224.275739 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10224.275739 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 932011 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 221163 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.214136 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2357131 # number of writebacks -system.cpu.dcache.writebacks::total 2357131 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540406 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2540406 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1993903 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1993903 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2352880 # number of writebacks +system.cpu.dcache.writebacks::total 2352880 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540436 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2540436 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995769 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1995769 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4534309 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4534309 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4534309 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4534309 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301861 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2301861 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519613 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519613 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4536205 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4536205 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4536205 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4536205 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301816 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2301816 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519586 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519586 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2821474 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2821474 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2821484 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2821484 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28687651000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 28687651000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4620185994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4620185994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 674500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 674500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33307836994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 33307836994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33308511494 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 33308511494 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019264 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019264 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 2821402 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2821402 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2821412 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2821412 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28692574000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28692574000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4617588494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4617588494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 686000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 686000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33310162494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 33310162494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33310848494 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 33310848494 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019263 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019263 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009580 # 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mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12462.807702 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12462.807702 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8891.590461 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8891.590461 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67450 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67450 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11805.119237 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11805.119237 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11805.316455 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11805.316455 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12465.190093 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12465.190093 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8887.053335 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8887.053335 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68600 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68600 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11806.244730 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11806.244730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11806.446026 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11806.446026 # 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Cycle average of tags in use +system.cpu.icache.tags.total_refs 236636536 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 73971 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3199.044707 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 114942017500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.213956 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.910574 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.910574 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id @@ -867,202 +868,202 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 119 system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 473514607 # Number of tag accesses -system.cpu.icache.tags.data_accesses 473514607 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 236637753 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 236637753 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 236637753 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 236637753 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 236637753 # number of overall hits -system.cpu.icache.overall_hits::total 236637753 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 82554 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 82554 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 82554 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 82554 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 82554 # number of overall misses -system.cpu.icache.overall_misses::total 82554 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1566745159 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1566745159 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1566745159 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1566745159 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1566745159 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1566745159 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 236720307 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 236720307 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 236720307 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 236720307 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 236720307 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 236720307 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 473512362 # Number of tag accesses +system.cpu.icache.tags.data_accesses 473512362 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 236636536 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 236636536 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 236636536 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 236636536 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 236636536 # number of overall hits +system.cpu.icache.overall_hits::total 236636536 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 82647 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 82647 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 82647 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 82647 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 82647 # number of overall misses +system.cpu.icache.overall_misses::total 82647 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1564864673 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1564864673 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1564864673 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1564864673 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1564864673 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1564864673 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 236719183 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 236719183 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 236719183 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 236719183 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 236719183 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 236719183 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000349 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000349 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000349 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000349 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000349 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000349 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18978.428168 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18978.428168 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18978.428168 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18978.428168 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18978.428168 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18978.428168 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 198034 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7006 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.266343 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18934.319128 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18934.319128 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18934.319128 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18934.319128 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18934.319128 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18934.319128 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 190768 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6939 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 27.492146 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 23.750000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8560 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 8560 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 8560 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 8560 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 8560 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 8560 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 73994 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 73994 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 73994 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 73994 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 73994 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 73994 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1278636265 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1278636265 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1278636265 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1278636265 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1278636265 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1278636265 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8650 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 8650 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 8650 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 8650 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 8650 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 8650 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 73997 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 73997 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 73997 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 73997 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 73997 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 73997 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1275745779 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1275745779 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1275745779 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1275745779 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1275745779 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1275745779 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17280.269549 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17280.269549 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17280.269549 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17280.269549 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17280.269549 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17280.269549 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17240.506764 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17240.506764 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17240.506764 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17240.506764 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17240.506764 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17240.506764 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 8511909 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8513040 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 167 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 8512194 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 8513359 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 195 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 743544 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 401080 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15418.085448 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5068240 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 417417 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.141911 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 34601120500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8466.854939 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 473.689855 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4911.860449 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1565.680205 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.516776 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.028912 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.299796 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.095562 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.941045 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 1090 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15247 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 32 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 243 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 815 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1541 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10024 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3332 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.066528 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.930603 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 93191002 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 93191002 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 2357131 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2357131 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 25 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 25 # 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number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.074074 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.074074 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007131 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007131 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.145739 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.145739 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.060860 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.060860 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.145739 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050920 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.053342 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.145739 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050920 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.041667 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.144425 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.144425 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.060750 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.060750 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.144425 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050809 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.053201 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144425 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050809 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.148517 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69015.083205 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69015.083205 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16750 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16750 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92483.476625 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92483.476625 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67464.514333 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67464.514333 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71307.966587 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71307.966587 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67464.514333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71856.555694 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71550.033021 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67464.514333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71856.555694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69015.083205 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69925.549787 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.148304 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69356.062148 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69356.062148 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92304.151871 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92304.151871 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67648.272957 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67648.272957 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71343.207508 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71343.207508 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67648.272957 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71878.519309 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71585.133249 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67648.272957 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71878.519309 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69356.062148 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70155.690850 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 2373490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2649541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 621819 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 317371 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521960 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521960 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 73994 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299497 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220555 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440647 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8661202 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331429632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 336163072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 718484 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6508328 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.110389 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.313375 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 5789744 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894372 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23770 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 30234 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 30144 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 2373438 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2645111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 626124 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 317103 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 521946 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521946 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 73997 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299442 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220575 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440808 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8661383 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331153152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 335887104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 717772 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6507488 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.011967 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108866 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5789877 88.96% 88.96% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 718451 11.04% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6429701 98.80% 98.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 77697 1.19% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 90 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6508328 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5252069500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 111018442 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6507488 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5247752000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 111080826 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4232215467 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4232108471 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.trans_dist::ReadResp 408504 # Transaction distribution -system.membus.trans_dist::Writeback 292410 # Transaction distribution -system.membus.trans_dist::CleanEvict 103085 # Transaction distribution -system.membus.trans_dist::UpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 3721 # Transaction distribution -system.membus.trans_dist::ReadExResp 3721 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 408504 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1219951 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1219951 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45096640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45096640 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 408044 # Transaction distribution +system.membus.trans_dist::Writeback 292231 # Transaction distribution +system.membus.trans_dist::CleanEvict 102781 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 3660 # Transaction distribution +system.membus.trans_dist::ReadExResp 3660 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 408044 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1218424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1218424 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45051840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45051840 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 807723 # Request fanout histogram +system.membus.snoop_fanout::samples 806718 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 807723 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 806718 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 807723 # Request fanout histogram -system.membus.reqLayer0.occupancy 2173813941 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 806718 # Request fanout histogram +system.membus.reqLayer0.occupancy 2171550377 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2179181168 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2176359308 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 7568a8b98..ad7524f92 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.707533 # Number of seconds simulated -sim_ticks 707533448500 # Number of ticks simulated -final_tick 707533448500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.707537 # Number of seconds simulated +sim_ticks 707536959500 # Number of ticks simulated +final_tick 707536959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1147583 # Simulator instruction rate (inst/s) -host_op_rate 1242781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1607870578 # Simulator tick rate (ticks/s) -host_mem_usage 316160 # Number of bytes of host memory used -host_seconds 440.04 # Real time elapsed on the host +host_inst_rate 1064510 # Simulator instruction rate (inst/s) +host_op_rate 1152817 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1491485099 # Simulator tick rate (ticks/s) +host_mem_usage 319084 # Number of bytes of host memory used +host_seconds 474.38 # Real time elapsed on the host sim_insts 504986854 # Number of instructions simulated sim_ops 546878105 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 139793 # Nu system.physmem.num_reads::total 142533 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 96032 # Number of write requests responded to by this memory system.physmem.num_writes::total 96032 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 247847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12644988 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12892835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 247847 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 247847 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8686583 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8686583 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8686583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 247847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12644988 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21579418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 247846 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12644925 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12892771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 247846 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 247846 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8686540 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8686540 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8686540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 247846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12644925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21579311 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1415066897 # number of cpu cycles simulated +system.cpu.numCycles 1415073919 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504986854 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 172745235 # nu system.cpu.num_load_insts 115884756 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1415066896.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1415073918.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 121548302 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548695379 # Class of executed instruction system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.318183 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4065.318106 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11716394500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318183 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 11716435500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318106 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138917 # n system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817723000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11817723000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11820971000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11820971000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 8866220000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 8866220000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20683943000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20683943000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20683943000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20683943000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20687191000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20687191000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20687191000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20687191000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) @@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.491859 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.491859 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15103.641825 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15103.641825 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24886.936507 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 24886.936507 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18161.062659 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18161.062659 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18161.046713 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18161.046713 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18163.914491 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18163.914491 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18163.898542 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18163.898542 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11035066000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11035066000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11038314000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11038314000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509960000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509960000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19545026000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19545026000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19545080000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19545080000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19548274000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19548274000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19548328000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19548328000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses @@ -336,26 +336,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14099.491859 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14099.491859 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14103.641825 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14103.641825 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23886.936507 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23886.936507 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17161.062659 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17161.062659 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17161.095004 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17161.095004 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17163.914491 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17163.914491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17163.946834 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17163.946834 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 983.369510 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 983.371232 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516599856 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 44839.845152 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 983.369510 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.480161 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.480161 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 983.371232 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id @@ -377,12 +377,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 265181000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 265181000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 265181000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 265181000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 265181000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 265181000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 265444000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 265444000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 265444000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 265444000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 265444000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 265444000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516611377 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611377 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516611377 # number of demand (read+write) accesses @@ -395,12 +395,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23017.186008 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23017.186008 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23017.186008 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23017.186008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23017.186008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23017.186008 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23040.013888 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23040.013888 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23040.013888 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23040.013888 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -415,38 +415,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253660000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 253660000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253660000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 253660000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253660000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 253660000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253923000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 253923000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253923000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 253923000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253923000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 253923000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22017.186008 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22017.186008 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22017.186008 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22017.186008 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22017.186008 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22017.186008 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22040.013888 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22040.013888 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22040.013888 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22040.013888 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22040.013888 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22040.013888 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109779 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27249.065072 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 27249.077163 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1743796 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 140956 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 12.371208 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 338493397000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23345.004709 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.705162 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3616.355202 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 338494154000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23345.006122 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.705462 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3616.365578 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.712433 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008780 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.110362 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831575 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.110363 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.831576 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id @@ -485,14 +485,14 @@ system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5292536500 system.cpu.l2cache.ReadExReq_miss_latency::total 5292536500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 144147000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 144147000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2053299500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2053299500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2053419500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2053419500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 144147000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7345836000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7489983000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7345956000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7490103000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 144147000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7345836000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7489983000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7345956000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7490103000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 1064880 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1064880 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) @@ -523,14 +523,14 @@ system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.245004 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.245004 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52608.394161 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52608.394161 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52567.831541 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52567.831541 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52570.903738 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52570.903738 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.953045 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52549.114942 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52549.956852 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.953045 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52549.114942 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52549.956852 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -559,14 +559,14 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285206500 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285206500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116747000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116747000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662699500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662699500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662819500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662819500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116747000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5947906000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6064653000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5948026000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6064773000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116747000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5947906000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6064653000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5948026000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6064773000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282751 # mshr miss rate for ReadExReq accesses @@ -585,15 +585,21 @@ system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42540.245004 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42540.245004 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42608.394161 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42608.394161 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42567.831541 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42567.831541 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42570.903738 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42570.903738 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42547.953045 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.114942 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42547.953045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.114942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 2295049 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1144662 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3461 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2140 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2139 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1160912 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 90016 # Transaction distribution @@ -609,14 +615,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 141780416 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 109779 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 2404828 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.045649 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.208724 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.003790 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.061455 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2295049 95.44% 95.44% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 109779 4.56% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2395714 99.62% 99.62% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 9113 0.38% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 2404828 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2212404500 # Layer occupancy (ticks) @@ -646,9 +652,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 251058 # Request fanout histogram -system.membus.reqLayer0.occupancy 643796820 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 643796492 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 719009492 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 719009164 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index c2ca7f71b..987362254 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.403707 # Number of seconds simulated -sim_ticks 403706643500 # Number of ticks simulated -final_tick 403706643500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.403931 # Number of seconds simulated +sim_ticks 403931323500 # Number of ticks simulated +final_tick 403931323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76271 # Simulator instruction rate (inst/s) -host_op_rate 141034 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37237827 # Simulator tick rate (ticks/s) -host_mem_usage 423672 # Number of bytes of host memory used -host_seconds 10841.31 # Real time elapsed on the host +host_inst_rate 95186 # Simulator instruction rate (inst/s) +host_op_rate 176009 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46498470 # Simulator tick rate (ticks/s) +host_mem_usage 433064 # Number of bytes of host memory used +host_seconds 8686.98 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 216320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24497408 # Number of bytes read from this memory -system.physmem.bytes_read::total 24713728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18869312 # Number of bytes written to this memory -system.physmem.bytes_written::total 18869312 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3380 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382772 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386152 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294833 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294833 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 535835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60681211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 61217046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 535835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 535835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 46740157 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 46740157 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 46740157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 535835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60681211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 107957203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386152 # Number of read requests accepted -system.physmem.writeReqs 294833 # Number of write requests accepted -system.physmem.readBursts 386152 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294833 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24695616 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18112 # Total number of bytes read from write queue -system.physmem.bytesWritten 18867776 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24713728 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18869312 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 283 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24500544 # Number of bytes read from this memory +system.physmem.bytes_read::total 24718528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18869632 # Number of bytes written to this memory +system.physmem.bytes_written::total 18869632 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382821 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386227 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 294838 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294838 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 539656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60655222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 61194878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 539656 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 539656 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 46714951 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 46714951 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 46714951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 539656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60655222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 107909829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386228 # Number of read requests accepted +system.physmem.writeReqs 294838 # Number of write requests accepted +system.physmem.readBursts 386228 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 294838 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24699456 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19136 # Total number of bytes read from write queue +system.physmem.bytesWritten 18868032 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24718592 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18869632 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 299 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 195189 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24028 # Per bank write bursts -system.physmem.perBankRdBursts::1 26400 # Per bank write bursts -system.physmem.perBankRdBursts::2 24980 # Per bank write bursts -system.physmem.perBankRdBursts::3 24600 # Per bank write bursts -system.physmem.perBankRdBursts::4 23395 # Per bank write bursts -system.physmem.perBankRdBursts::5 23728 # Per bank write bursts -system.physmem.perBankRdBursts::6 24595 # Per bank write bursts -system.physmem.perBankRdBursts::7 24357 # Per bank write bursts -system.physmem.perBankRdBursts::8 23707 # Per bank write bursts -system.physmem.perBankRdBursts::9 23543 # Per bank write bursts -system.physmem.perBankRdBursts::10 24760 # Per bank write bursts -system.physmem.perBankRdBursts::11 23969 # Per bank write bursts -system.physmem.perBankRdBursts::12 23156 # Per bank write bursts -system.physmem.perBankRdBursts::13 22899 # Per bank write bursts -system.physmem.perBankRdBursts::14 23872 # Per bank write bursts -system.physmem.perBankRdBursts::15 23880 # Per bank write bursts -system.physmem.perBankWrBursts::0 18605 # Per bank write bursts -system.physmem.perBankWrBursts::1 19929 # Per bank write bursts -system.physmem.perBankWrBursts::2 19196 # Per bank write bursts -system.physmem.perBankWrBursts::3 18982 # Per bank write bursts -system.physmem.perBankWrBursts::4 18144 # Per bank write bursts -system.physmem.perBankWrBursts::5 18488 # Per bank write bursts -system.physmem.perBankWrBursts::6 19136 # Per bank write bursts -system.physmem.perBankWrBursts::7 19077 # Per bank write bursts -system.physmem.perBankWrBursts::8 18672 # Per bank write bursts -system.physmem.perBankWrBursts::9 17940 # Per bank write bursts -system.physmem.perBankWrBursts::10 18886 # Per bank write bursts -system.physmem.perBankWrBursts::11 17736 # Per bank write bursts -system.physmem.perBankWrBursts::12 17372 # Per bank write bursts -system.physmem.perBankWrBursts::13 16987 # Per bank write bursts -system.physmem.perBankWrBursts::14 17811 # Per bank write bursts -system.physmem.perBankWrBursts::15 17848 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 196128 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24062 # Per bank write bursts +system.physmem.perBankRdBursts::1 26430 # Per bank write bursts +system.physmem.perBankRdBursts::2 24903 # Per bank write bursts +system.physmem.perBankRdBursts::3 24577 # Per bank write bursts +system.physmem.perBankRdBursts::4 23181 # Per bank write bursts +system.physmem.perBankRdBursts::5 23704 # Per bank write bursts +system.physmem.perBankRdBursts::6 24550 # Per bank write bursts +system.physmem.perBankRdBursts::7 24303 # Per bank write bursts +system.physmem.perBankRdBursts::8 23663 # Per bank write bursts +system.physmem.perBankRdBursts::9 23568 # Per bank write bursts +system.physmem.perBankRdBursts::10 24789 # Per bank write bursts +system.physmem.perBankRdBursts::11 23975 # Per bank write bursts +system.physmem.perBankRdBursts::12 23330 # Per bank write bursts +system.physmem.perBankRdBursts::13 22932 # Per bank write bursts +system.physmem.perBankRdBursts::14 24089 # Per bank write bursts +system.physmem.perBankRdBursts::15 23873 # Per bank write bursts +system.physmem.perBankWrBursts::0 18604 # Per bank write bursts +system.physmem.perBankWrBursts::1 19922 # Per bank write bursts +system.physmem.perBankWrBursts::2 19191 # Per bank write bursts +system.physmem.perBankWrBursts::3 18985 # Per bank write bursts +system.physmem.perBankWrBursts::4 18090 # Per bank write bursts +system.physmem.perBankWrBursts::5 18485 # Per bank write bursts +system.physmem.perBankWrBursts::6 19138 # Per bank write bursts +system.physmem.perBankWrBursts::7 19082 # Per bank write bursts +system.physmem.perBankWrBursts::8 18642 # Per bank write bursts +system.physmem.perBankWrBursts::9 17946 # Per bank write bursts +system.physmem.perBankWrBursts::10 18887 # Per bank write bursts +system.physmem.perBankWrBursts::11 17737 # Per bank write bursts +system.physmem.perBankWrBursts::12 17398 # Per bank write bursts +system.physmem.perBankWrBursts::13 16988 # Per bank write bursts +system.physmem.perBankWrBursts::14 17875 # Per bank write bursts +system.physmem.perBankWrBursts::15 17843 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 403706602500 # Total gap between requests +system.physmem.totGap 403931308500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386152 # Read request sizes (log2) +system.physmem.readPktSize::6 386228 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294833 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 294838 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,37 +144,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -193,246 +193,248 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146765 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.814963 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.408246 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.979648 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54126 36.88% 36.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39824 27.13% 64.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13787 9.39% 73.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7512 5.12% 78.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5608 3.82% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3872 2.64% 84.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3087 2.10% 87.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2794 1.90% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16155 11.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146765 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17509 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.037923 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 218.270562 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17499 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.637860 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.325639 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.046473 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54140 36.86% 36.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39981 27.22% 64.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13765 9.37% 73.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7667 5.22% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5371 3.66% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3914 2.67% 85.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3025 2.06% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2731 1.86% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16272 11.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146866 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17494 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.060078 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 218.173610 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17485 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 4 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17509 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17509 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.837569 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.769084 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.527211 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17319 98.91% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 139 0.79% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 19 0.11% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 11 0.06% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 2 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 2 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 2 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17509 # Writes before turning the bus around for reads -system.physmem.totQLat 4289653250 # Total ticks spent queuing -system.physmem.totMemAccLat 11524697000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1929345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11116.86 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17494 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17494 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.852235 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.776145 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.682764 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17296 98.87% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 143 0.82% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 28 0.16% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 5 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 3 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 3 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 3 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17494 # Writes before turning the bus around for reads +system.physmem.totQLat 4291077750 # Total ticks spent queuing +system.physmem.totMemAccLat 11527246500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1929645000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11118.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29866.86 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 61.17 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 46.74 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 61.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 46.74 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29868.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 61.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 46.71 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 61.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 46.71 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.84 # Data bus utilization in percentage system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.93 # Average write queue length when enqueuing -system.physmem.readRowHits 317973 # Number of row buffer hits during reads -system.physmem.writeRowHits 215927 # Number of row buffer hits during writes +system.physmem.avgWrQLen 21.35 # Average write queue length when enqueuing +system.physmem.readRowHits 317989 # Number of row buffer hits during reads +system.physmem.writeRowHits 215873 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.24 # Row buffer hit rate for writes -system.physmem.avgGap 592827.45 # Average gap between requests -system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 569094120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 310517625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1529307000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 981933840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26367818880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62417540205 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 187468813500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 279645025170 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.702062 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 311319479750 # Time in different power states -system.physmem_0.memoryStateTime::REF 13480480000 # Time in different power states +system.physmem.writeRowHitRate 73.22 # Row buffer hit rate for writes +system.physmem.avgGap 593086.88 # Average gap between requests +system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 567438480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 309614250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1526405400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 981499680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26382567120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62258546970 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 187743770250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 279769842150 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.623817 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 311776883750 # Time in different power states +system.physmem_0.memoryStateTime::REF 13488020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78902125750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78662661250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 540041040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 294665250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1479816000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 928013760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26367818880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 60324869565 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 189304489500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 279239713995 # Total energy per rank (pJ) -system.physmem_1.averagePower 691.698075 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 314381404750 # Time in different power states -system.physmem_1.memoryStateTime::REF 13480480000 # Time in different power states +system.physmem_1.actEnergy 542467800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 295989375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1483341600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 928473840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26382567120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 60448758210 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 189331310250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 279412908195 # Total energy per rank (pJ) +system.physmem_1.averagePower 691.740141 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 314432491250 # Time in different power states +system.physmem_1.memoryStateTime::REF 13488020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 75839865250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 76007072500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 219316547 # Number of BP lookups -system.cpu.branchPred.condPredicted 219316547 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 8533340 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 124021938 # Number of BTB lookups -system.cpu.branchPred.BTBHits 121820147 # Number of BTB hits +system.cpu.branchPred.lookups 219314839 # Number of BP lookups +system.cpu.branchPred.condPredicted 219314839 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 8530231 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 123981217 # Number of BTB lookups +system.cpu.branchPred.BTBHits 121825604 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.224676 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 27066490 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1406992 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.261339 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 27068206 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1407908 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 807413288 # number of cpu cycles simulated +system.cpu.numCycles 807862648 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 175921222 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1208610344 # Number of instructions fetch has processed -system.cpu.fetch.Branches 219316547 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 148886637 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 621541997 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17781141 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 241 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 95442 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 760366 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1422 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 170776115 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2324492 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 807211301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.786075 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.367353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 175941692 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1208657835 # Number of instructions fetch has processed +system.cpu.fetch.Branches 219314839 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 148893810 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 622000001 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17769177 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 227 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 92380 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 735169 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1433 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 170789403 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2323822 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 807655519 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.784658 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.367182 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 417064653 51.67% 51.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32628603 4.04% 55.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31895320 3.95% 59.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32734486 4.06% 63.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26590994 3.29% 67.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 26897855 3.33% 70.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35141039 4.35% 74.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31437377 3.89% 78.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 172820974 21.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 417598750 51.71% 51.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32531773 4.03% 55.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31857083 3.94% 59.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32716073 4.05% 63.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26594170 3.29% 67.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 26933309 3.33% 70.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 35181908 4.36% 74.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31423846 3.89% 78.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 172818607 21.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 807211301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.271629 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.496892 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 120518152 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 370503139 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 225214950 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82084490 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8890570 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2132165876 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 8890570 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 152539883 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 150620560 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 39985 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 271567858 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 223552445 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2088589695 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 134600 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 138169190 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24839349 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 50537004 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2190785289 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5278493147 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3357262511 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 59407 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 807655519 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.271475 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.496118 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 120412218 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 371076736 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 225209960 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82072017 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8884588 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2132095724 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 8884588 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 152556291 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 150817488 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 41958 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 271423783 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 223931411 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2088526658 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 137354 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 138380994 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24891978 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 50561951 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2190720490 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5278322969 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3357144423 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 60320 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 576744435 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3185 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2908 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 421985771 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 507135954 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 200817604 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 229019753 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 68232285 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2023164418 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22990 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1789038207 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 420221 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 494198707 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 833041498 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22438 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 807211301 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.216320 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.070566 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 576679636 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3187 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2956 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 423114583 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 507122992 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 200812983 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 229080264 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 68423458 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2023133283 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22942 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1788928106 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 421261 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 494167524 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 833180412 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22390 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 807655519 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.214964 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.070282 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 238530872 29.55% 29.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 123621910 15.31% 44.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 118898033 14.73% 59.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 107819129 13.36% 72.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 89545218 11.09% 84.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60296093 7.47% 91.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 42279085 5.24% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 18940691 2.35% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7280270 0.90% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 238829466 29.57% 29.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 123732265 15.32% 44.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 119115162 14.75% 59.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 107661207 13.33% 72.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 89581047 11.09% 84.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60232277 7.46% 91.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 42307619 5.24% 96.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18921199 2.34% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7275277 0.90% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 807211301 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 807655519 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11520759 42.69% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12368193 45.83% 88.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3098262 11.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11512552 42.68% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12355843 45.81% 88.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3105832 11.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2718353 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1183132640 66.13% 66.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 368609 0.02% 66.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881115 0.22% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 137 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2718297 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1183078959 66.13% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 370517 0.02% 66.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881151 0.22% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 134 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 64 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 344 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 67 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 365 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued @@ -454,84 +456,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 428541213 23.95% 90.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170395732 9.52% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 428492741 23.95% 90.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170385875 9.52% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1789038207 # Type of FU issued -system.cpu.iq.rate 2.215765 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26987214 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015085 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4412665624 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2517635859 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1762385104 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 29526 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 68682 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 5548 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1813294148 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12920 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 186084957 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1788928106 # Type of FU issued +system.cpu.iq.rate 2.214396 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26974227 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015078 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4412876800 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2517572556 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1762303286 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 30419 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 69720 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 5693 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1813170766 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 13270 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 186079397 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 123036250 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 211434 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 371907 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 51657418 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 123023075 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 212257 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 371984 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 51652797 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 23176 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1099 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 22860 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1101 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8890570 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 97719419 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6134161 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2023187408 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 375929 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 507138407 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 200817604 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7250 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1817237 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3413935 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 371907 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4848104 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4143061 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8991165 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1770021029 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 423153321 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19017178 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8884588 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 97906785 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6199562 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2023156225 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 370486 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 507125232 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 200812983 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7241 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1822287 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3474512 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 371984 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4845065 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4137242 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8982307 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1769932780 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 423113153 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 18995326 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590346194 # number of memory reference insts executed -system.cpu.iew.exec_branches 168990321 # Number of branches executed -system.cpu.iew.exec_stores 167192873 # Number of stores executed -system.cpu.iew.exec_rate 2.192212 # Inst execution rate -system.cpu.iew.wb_sent 1766892997 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1762390652 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1339756908 # num instructions producing a value -system.cpu.iew.wb_consumers 2049972766 # num instructions consuming a value +system.cpu.iew.exec_refs 590301691 # number of memory reference insts executed +system.cpu.iew.exec_branches 168980249 # Number of branches executed +system.cpu.iew.exec_stores 167188538 # Number of stores executed +system.cpu.iew.exec_rate 2.190883 # Inst execution rate +system.cpu.iew.wb_sent 1766804374 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1762308979 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1339663552 # num instructions producing a value +system.cpu.iew.wb_consumers 2049989844 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.182762 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.653549 # average fanout of values written-back +system.cpu.iew.wb_rate 2.181446 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.653498 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 494260386 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 494228972 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8618895 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 739988037 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.066234 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.575521 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 8612841 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 740434686 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.064988 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.575030 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 275878158 37.28% 37.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 172126899 23.26% 60.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 55937459 7.56% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86300571 11.66% 79.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25876597 3.50% 83.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26568843 3.59% 86.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9870767 1.33% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8919978 1.21% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78508765 10.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 276267324 37.31% 37.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 172135150 23.25% 60.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 56000087 7.56% 68.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86333753 11.66% 79.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25859703 3.49% 83.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26527369 3.58% 86.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9854605 1.33% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9004729 1.22% 89.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78451966 10.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 739988037 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 740434686 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -577,344 +579,344 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 78508765 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2684728359 # The number of ROB reads -system.cpu.rob.rob_writes 4113896609 # The number of ROB writes -system.cpu.timesIdled 2328 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 201987 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 78451966 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2685200393 # The number of ROB reads +system.cpu.rob.rob_writes 4113829657 # The number of ROB writes +system.cpu.timesIdled 2326 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 207129 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.976461 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.976461 # CPI: Total CPI of All Threads -system.cpu.ipc 1.024106 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.024106 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2722667059 # number of integer regfile reads -system.cpu.int_regfile_writes 1435857659 # number of integer regfile writes -system.cpu.fp_regfile_reads 5817 # number of floating regfile reads -system.cpu.fp_regfile_writes 496 # number of floating regfile writes -system.cpu.cc_regfile_reads 596670071 # number of cc regfile reads -system.cpu.cc_regfile_writes 405476387 # number of cc regfile writes -system.cpu.misc_regfile_reads 971632449 # number of misc regfile reads +system.cpu.cpi 0.977004 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.977004 # CPI: Total CPI of All Threads +system.cpu.ipc 1.023537 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.023537 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2722489562 # number of integer regfile reads +system.cpu.int_regfile_writes 1435790744 # number of integer regfile writes +system.cpu.fp_regfile_reads 5969 # number of floating regfile reads +system.cpu.fp_regfile_writes 521 # number of floating regfile writes +system.cpu.cc_regfile_reads 596647275 # number of cc regfile reads +system.cpu.cc_regfile_writes 405463698 # number of cc regfile writes +system.cpu.misc_regfile_reads 971582048 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2530789 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.813367 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 381875640 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2534885 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.648112 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2530897 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.817920 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 381840179 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2534993 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.627705 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.813367 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998001 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998001 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.817920 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998002 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 871 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3172 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 865 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3173 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 772839713 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 772839713 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 233227342 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 233227342 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148173773 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148173773 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 381401115 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 381401115 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 381401115 # number of overall hits -system.cpu.dcache.overall_hits::total 381401115 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2764870 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2764870 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 986429 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 986429 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3751299 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3751299 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3751299 # number of overall misses -system.cpu.dcache.overall_misses::total 3751299 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58802289500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58802289500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31059853996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31059853996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 89862143496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 89862143496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 89862143496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 89862143496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 235992212 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 235992212 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 772772413 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 772772413 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 233184165 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 233184165 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148172813 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148172813 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 381356978 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 381356978 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 381356978 # number of overall hits +system.cpu.dcache.overall_hits::total 381356978 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2774343 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2774343 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 987389 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 987389 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3761732 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3761732 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3761732 # number of overall misses +system.cpu.dcache.overall_misses::total 3761732 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59119368500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59119368500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31296279995 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31296279995 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 90415648495 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90415648495 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90415648495 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90415648495 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 235958508 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 235958508 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 385152414 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 385152414 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 385152414 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 385152414 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011716 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011716 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006613 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006613 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009740 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009740 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009740 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009740 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21267.650739 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21267.650739 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31487.166330 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31487.166330 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23954.940274 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23954.940274 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23954.940274 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23954.940274 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9795 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1045 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.373206 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 385118710 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 385118710 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 385118710 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 385118710 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011758 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011758 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006620 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006620 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009768 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009768 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009768 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009768 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21309.322063 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21309.322063 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31695.998229 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31695.998229 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24035.643287 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24035.643287 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24035.643287 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24035.643287 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10106 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1086 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.305709 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330774 # number of writebacks -system.cpu.dcache.writebacks::total 2330774 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1000095 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1000095 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19339 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 19339 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1019434 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1019434 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1019434 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1019434 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764775 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764775 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 967090 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 967090 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2731865 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2731865 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2731865 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2731865 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33541518000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33541518000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29840523997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 29840523997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63382041997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63382041997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63382041997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63382041997 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007478 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007478 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006484 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006484 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007093 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.007093 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007093 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.007093 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19006.115794 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19006.115794 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30855.994785 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30855.994785 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23201.015422 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23201.015422 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23201.015422 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23201.015422 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2330787 # number of writebacks +system.cpu.dcache.writebacks::total 2330787 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1009448 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1009448 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19379 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 19379 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1028827 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1028827 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1028827 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1028827 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764895 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764895 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 968010 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 968010 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2732905 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2732905 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2732905 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2732905 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33550858500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33550858500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30073647496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 30073647496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63624505996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63624505996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63624505996 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63624505996 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007480 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007480 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006490 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007096 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.007096 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007096 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.007096 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19010.115899 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19010.115899 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31067.496716 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31067.496716 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23280.906580 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23280.906580 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23280.906580 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23280.906580 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 6640 # number of replacements -system.cpu.icache.tags.tagsinuse 1037.923261 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 170565267 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8248 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20679.591052 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 6655 # number of replacements +system.cpu.icache.tags.tagsinuse 1037.678215 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 170577740 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8265 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20638.565033 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1037.923261 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506798 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506798 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1608 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1037.678215 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506679 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506679 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1610 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 326 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1153 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 341757570 # Number of tag accesses -system.cpu.icache.tags.data_accesses 341757570 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 170568161 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 170568161 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 170568161 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 170568161 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 170568161 # number of overall hits -system.cpu.icache.overall_hits::total 170568161 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 207953 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 207953 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 207953 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 207953 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 207953 # number of overall misses -system.cpu.icache.overall_misses::total 207953 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1300977000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1300977000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1300977000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1300977000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1300977000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1300977000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 170776114 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 170776114 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 170776114 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 170776114 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 170776114 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 170776114 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001218 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001218 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001218 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001218 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001218 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001218 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6256.110756 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6256.110756 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6256.110756 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6256.110756 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6256.110756 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6256.110756 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 718 # number of cycles access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 0.786133 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 341785100 # Number of tag accesses +system.cpu.icache.tags.data_accesses 341785100 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 170580521 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 170580521 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 170580521 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 170580521 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 170580521 # number of overall hits +system.cpu.icache.overall_hits::total 170580521 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 208882 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 208882 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 208882 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 208882 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 208882 # number of overall misses +system.cpu.icache.overall_misses::total 208882 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1312211500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1312211500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1312211500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1312211500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1312211500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1312211500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 170789403 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 170789403 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 170789403 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 170789403 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 170789403 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 170789403 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001223 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001223 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001223 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6282.070739 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6282.070739 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6282.070739 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6282.070739 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6282.070739 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6282.070739 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 889 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.833333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 74.083333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2609 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2609 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2609 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2609 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2609 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2609 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205344 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 205344 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 205344 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 205344 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 205344 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 205344 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 976991000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 976991000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 976991000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 976991000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 976991000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 976991000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001202 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001202 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001202 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4757.825892 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4757.825892 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4757.825892 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4757.825892 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4757.825892 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4757.825892 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2585 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2585 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2585 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2585 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2585 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2585 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 206297 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 206297 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 206297 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 206297 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 206297 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 206297 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 989635000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 989635000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 989635000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 989635000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 989635000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 989635000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001208 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001208 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001208 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4797.137137 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4797.137137 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4797.137137 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4797.137137 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4797.137137 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4797.137137 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 353471 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29618.497788 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3892615 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 385807 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.089540 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 189374171500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 20946.463818 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.310071 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8431.723899 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.639235 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007334 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.257316 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.903885 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32336 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 353544 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29619.458392 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3891749 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 385874 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.085543 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 189343942500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 20941.541383 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 242.518808 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8435.398201 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.639085 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007401 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.257428 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.903914 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32330 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 218 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13380 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13379 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18648 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986816 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43290247 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43290247 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 2330774 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2330774 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1839 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1839 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 563945 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 563945 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4854 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 4854 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1588121 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1588121 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4854 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2152066 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2156920 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4854 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2152066 # number of overall hits -system.cpu.l2cache.overall_hits::total 2156920 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 195142 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 195142 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206554 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206554 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3382 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3382 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176265 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 176265 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3382 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 382819 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 386201 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3382 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 382819 # number of overall misses -system.cpu.l2cache.overall_misses::total 386201 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13466000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 13466000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16374024500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16374024500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 275872500 # 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mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990664 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268078 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268078 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.410515 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.410515 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099902 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099902 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.410515 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151020 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151861 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.410515 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151020 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151861 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21050.320300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21050.320300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69272.367032 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69272.367032 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71578.231293 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71578.231293 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70450.344652 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70450.344652 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71578.231293 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69814.754492 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69830.192905 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71578.231293 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69814.754492 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69830.192905 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990733 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990733 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268107 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268107 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.412941 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099914 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099914 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151034 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151884 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151034 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151884 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22050.960694 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22050.960694 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69288.810735 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69288.810735 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72156.543427 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72156.543427 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70425.319629 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70425.319629 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72156.543427 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69812.131240 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69832.815141 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72156.543427 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69812.131240 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69832.815141 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 1969728 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2625607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 254220 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 196981 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 196981 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 770499 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 770499 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 205344 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764386 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 219812 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7983854 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8203666 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 526976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311402176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 311929152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 550579 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5828110 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.060649 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.238686 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 5476754 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2732107 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 213805 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3607 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3607 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 1970799 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2625625 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 253914 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 197912 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 197912 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 770488 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 770488 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 206297 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764505 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7985563 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8206352 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 528000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311409920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 311937920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 551588 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5830298 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.072755 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.259734 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5474639 93.94% 93.94% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 353471 6.06% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5406114 92.72% 92.72% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 424184 7.28% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5828110 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5096523027 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5830298 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5097760193 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 308017990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 309447487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3900818077 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3901446077 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 179644 # Transaction distribution -system.membus.trans_dist::Writeback 294833 # Transaction distribution -system.membus.trans_dist::CleanEvict 57066 # Transaction distribution -system.membus.trans_dist::UpgradeReq 195189 # Transaction distribution -system.membus.trans_dist::UpgradeResp 195189 # Transaction distribution -system.membus.trans_dist::ReadExReq 206507 # Transaction distribution -system.membus.trans_dist::ReadExResp 206507 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 179645 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1514580 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1514580 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1514580 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43582976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43582976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43582976 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 179703 # Transaction distribution +system.membus.trans_dist::Writeback 294838 # Transaction distribution +system.membus.trans_dist::CleanEvict 57117 # Transaction distribution +system.membus.trans_dist::UpgradeReq 196128 # Transaction distribution +system.membus.trans_dist::UpgradeResp 196128 # Transaction distribution +system.membus.trans_dist::ReadExReq 206523 # Transaction distribution +system.membus.trans_dist::ReadExResp 206523 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 179705 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1516665 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1516665 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1516665 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43588096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43588096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43588096 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 933240 # Request fanout histogram +system.membus.snoop_fanout::samples 934311 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 933240 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 934311 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 933240 # Request fanout histogram -system.membus.reqLayer0.occupancy 2243803396 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 934311 # Request fanout histogram +system.membus.reqLayer0.occupancy 2245481708 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2433027599 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2435298904 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 7244d6f89..22535a108 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.647861 # Nu sim_ticks 1647861059500 # Number of ticks simulated final_tick 1647861059500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 708384 # Simulator instruction rate (inst/s) -host_op_rate 1309882 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1411719986 # Simulator tick rate (ticks/s) -host_mem_usage 323600 # Number of bytes of host memory used -host_seconds 1167.27 # Real time elapsed on the host +host_inst_rate 657040 # Simulator instruction rate (inst/s) +host_op_rate 1214941 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1309397988 # Simulator tick rate (ticks/s) +host_mem_usage 327616 # Number of bytes of host memory used +host_seconds 1258.49 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -455,6 +455,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42534.290271 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.122697 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.291443 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 5036887 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2515615 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2616401 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 247396 # Transaction distribution @@ -470,15 +476,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 310047936 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 348182 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 5385069 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.064657 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.245920 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000321 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.017916 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5036887 93.53% 93.53% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 348182 6.47% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5383340 99.97% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1729 0.03% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 5385069 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4841670500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 988455083..e60710ec5 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.225711 # Nu sim_ticks 225710988500 # Number of ticks simulated final_tick 225710988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 225638 # Simulator instruction rate (inst/s) -host_op_rate 225638 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 127748919 # Simulator tick rate (ticks/s) -host_mem_usage 297512 # Number of bytes of host memory used -host_seconds 1766.83 # Real time elapsed on the host +host_inst_rate 311102 # Simulator instruction rate (inst/s) +host_op_rate 311102 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 176136084 # Simulator tick rate (ticks/s) +host_mem_usage 304484 # Number of bytes of host memory used +host_seconds 1281.46 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -661,6 +661,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64795.092497 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66138.637506 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65474.205845 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 13288 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3958 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 6132 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 3304 # Transaction distribution @@ -676,15 +682,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 638976 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 13288 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 13288 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 13288 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 13288 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 7298000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 49a2168d9..0e0bba79f 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.067874 # Nu sim_ticks 67874346000 # Number of ticks simulated final_tick 67874346000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172313 # Simulator instruction rate (inst/s) -host_op_rate 172313 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31140671 # Simulator tick rate (ticks/s) -host_mem_usage 298536 # Number of bytes of host memory used -host_seconds 2179.60 # Real time elapsed on the host +host_inst_rate 238872 # Simulator instruction rate (inst/s) +host_op_rate 238872 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43169272 # Simulator tick rate (ticks/s) +host_mem_usage 305488 # Number of bytes of host memory used +host_seconds 1572.28 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -955,6 +955,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65792.367963 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69503.885686 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67783.658373 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 11134 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2903 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 5042 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 656 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2247 # Transaction distribution @@ -970,15 +976,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 568768 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 11134 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11134 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11134 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 11134 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 6223000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 8c86953a0..b9717df42 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu sim_ticks 567335097500 # Number of ticks simulated final_tick 567335097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1293186 # Simulator instruction rate (inst/s) -host_op_rate 1293186 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1840317995 # Simulator tick rate (ticks/s) -host_mem_usage 300812 # Number of bytes of host memory used -host_seconds 308.28 # Real time elapsed on the host +host_inst_rate 1348015 # Simulator instruction rate (inst/s) +host_op_rate 1348015 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1918345002 # Simulator tick rate (ticks/s) +host_mem_usage 301916 # Number of bytes of host memory used +host_seconds 295.74 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -472,6 +472,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.780031 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.348481 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 1884 # Transaction distribution @@ -487,15 +493,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 10358 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 10358 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10358 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 10358 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 5828000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 333ae52c9..5974a793e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.215506 # Number of seconds simulated -sim_ticks 215505832500 # Number of ticks simulated -final_tick 215505832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.215510 # Number of seconds simulated +sim_ticks 215510486500 # Number of ticks simulated +final_tick 215510486500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114925 # Simulator instruction rate (inst/s) -host_op_rate 137980 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90709005 # Simulator tick rate (ticks/s) -host_mem_usage 317788 # Number of bytes of host memory used -host_seconds 2375.79 # Real time elapsed on the host +host_inst_rate 166248 # Simulator instruction rate (inst/s) +host_op_rate 199599 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 131220473 # Simulator tick rate (ticks/s) +host_mem_usage 326292 # Number of bytes of host memory used +host_seconds 1642.35 # Real time elapsed on the host sim_insts 273037857 # Number of instructions simulated sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 218880 # Nu system.physmem.num_reads::cpu.inst 3420 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory system.physmem.num_reads::total 7582 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1015657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1236013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2251670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1015657 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1015657 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1015657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1236013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2251670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1015635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1235986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2251621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1015635 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1015635 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1015635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1235986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2251621 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7582 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7582 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 215505593500 # Total gap between requests +system.physmem.totGap 215510247500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 893 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 318.272548 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.961816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.159233 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 550 36.21% 36.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 342 22.51% 58.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 179 11.78% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 82 5.40% 75.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 73 4.81% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 43 2.83% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 37 2.44% 85.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 30 1.97% 87.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 183 12.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation -system.physmem.totQLat 52046750 # Total ticks spent queuing -system.physmem.totMemAccLat 194209250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1514 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 319.408190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.009179 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.260420 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 549 36.26% 36.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 346 22.85% 59.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 166 10.96% 70.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 79 5.22% 75.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 78 5.15% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 48 3.17% 83.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.44% 86.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 27 1.78% 87.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 184 12.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1514 # Bytes accessed per row activation +system.physmem.totQLat 52026250 # Total ticks spent queuing +system.physmem.totMemAccLat 194188750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37910000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6864.51 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6861.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25614.51 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25611.81 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s @@ -216,47 +216,47 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6056 # Number of row buffer hits during reads +system.physmem.readRowHits 6062 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.87 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.95 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28423317.53 # Average gap between requests -system.physmem.pageHitRate 79.87 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4997160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2726625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28423931.35 # Average gap between requests +system.physmem.pageHitRate 79.95 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5050080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2755500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14075415120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5632744275 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 124359177000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 144104965380 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.699601 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 206882994500 # Time in different power states -system.physmem_0.memoryStateTime::REF 7196020000 # Time in different power states +system.physmem_0.refreshEnergy 14075923680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5660638650 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 124339380000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 144113699910 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.715971 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 206848311250 # Time in different power states +system.physmem_0.memoryStateTime::REF 7196280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1423707500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1464242250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6463800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3526875 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 6388200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3485625 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 28977000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14075415120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5808881115 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 124204671000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 144127934910 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.806188 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 206624169250 # Time in different power states -system.physmem_1.memoryStateTime::REF 7196020000 # Time in different power states +system.physmem_1.refreshEnergy 14075923680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5785657605 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 124229714250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 144130146360 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.792285 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 206662748250 # Time in different power states +system.physmem_1.memoryStateTime::REF 7196280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1683261250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1649073000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 32816945 # Number of BP lookups -system.cpu.branchPred.condPredicted 16892744 # Number of conditional branches predicted +system.cpu.branchPred.lookups 32816918 # Number of BP lookups +system.cpu.branchPred.condPredicted 16892730 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1463888 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17497063 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15468368 # Number of BTB hits +system.cpu.branchPred.BTBLookups 17497037 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15468342 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.405511 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 88.405494 # BTB Hit Percentage system.cpu.branchPred.usedRAS 6575577 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -377,24 +377,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 431011665 # number of cpu cycles simulated +system.cpu.numCycles 431020973 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037857 # Number of instructions committed system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed -system.cpu.discardedOps 3889170 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 3889164 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.578578 # CPI: cycles per instruction -system.cpu.ipc 0.633481 # IPC: instructions per cycle -system.cpu.tickCycles 427409330 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3602335 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.578612 # CPI: cycles per instruction +system.cpu.ipc 0.633468 # IPC: instructions per cycle +system.cpu.tickCycles 427416493 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3604480 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.814933 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168714880 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.814208 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168714884 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37400.771448 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37400.772334 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.814933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.814208 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.753373 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753373 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id @@ -404,42 +404,42 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337448855 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337448855 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86582107 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86582107 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047449 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047449 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 337448859 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337448859 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86582109 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86582109 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047451 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 63534 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 63534 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168629556 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168629556 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168693090 # number of overall hits -system.cpu.dcache.overall_hits::total 168693090 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168629560 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168629560 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168693094 # number of overall hits +system.cpu.dcache.overall_hits::total 168693094 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5228 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5228 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5226 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 7287 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7287 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7292 # number of overall misses -system.cpu.dcache.overall_misses::total 7292 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 135542000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 135542000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 392317500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 392317500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 527859500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 527859500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 527859500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 527859500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86584166 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86584166 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7285 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7285 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses +system.cpu.dcache.overall_misses::total 7290 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 136254500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 136254500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 393515500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 393515500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 529770000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 529770000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 529770000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 529770000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86584168 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86584168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 63539 # number of SoftPFReq accesses(hits+misses) @@ -448,10 +448,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168636843 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168636843 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168700382 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168700382 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168636845 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168636845 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168700384 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168700384 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65829.043225 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 65829.043225 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75041.602907 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75041.602907 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72438.520653 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72438.520653 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72388.850795 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72388.850795 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66175.084993 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66175.084993 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75299.559893 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75299.559893 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72720.658888 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72720.658888 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72670.781893 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72670.781893 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu system.cpu.dcache.writebacks::total 1010 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 421 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2358 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2358 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2779 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2779 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2356 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2356 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2777 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2777 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2777 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2777 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1638 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1638 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4508 system.cpu.dcache.demand_mshr_misses::total 4508 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109498500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 109498500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218637500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 218637500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109975000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109975000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219249000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 219249000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 328136000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 328136000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 328374000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 328374000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329224000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 329224000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329462000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 329462000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -518,26 +518,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66848.901099 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66848.901099 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76180.313589 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76180.313589 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67139.804640 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67139.804640 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76393.379791 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76393.379791 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72789.707187 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72789.707187 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72794.058967 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72794.058967 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73031.055901 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73031.055901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73035.247174 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73035.247174 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 36873 # number of replacements -system.cpu.icache.tags.tagsinuse 1923.841153 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 72548906 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1923.840697 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 72548791 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 38809 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1869.383545 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1869.380582 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1923.841153 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939376 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939376 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1923.840697 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939375 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939375 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id @@ -545,44 +545,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 34 system.cpu.icache.tags.age_task_id_blocks_1024::3 276 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1485 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 145214241 # Number of tag accesses -system.cpu.icache.tags.data_accesses 145214241 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 72548906 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 72548906 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 72548906 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 72548906 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 72548906 # number of overall hits -system.cpu.icache.overall_hits::total 72548906 # number of overall hits +system.cpu.icache.tags.tag_accesses 145214011 # Number of tag accesses +system.cpu.icache.tags.data_accesses 145214011 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 72548791 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 72548791 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 72548791 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 72548791 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 72548791 # number of overall hits +system.cpu.icache.overall_hits::total 72548791 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 38810 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 38810 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 38810 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 38810 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 38810 # number of overall misses system.cpu.icache.overall_misses::total 38810 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 726866500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 726866500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 726866500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 726866500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 726866500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 726866500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 72587716 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 72587716 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 72587716 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 72587716 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 72587716 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 72587716 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 740838000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 740838000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 740838000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 740838000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 740838000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 740838000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 72587601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 72587601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 72587601 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 72587601 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 72587601 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 72587601 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000535 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000535 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000535 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000535 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000535 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000535 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18728.845658 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18728.845658 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18728.845658 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18728.845658 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18728.845658 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18728.845658 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19088.843082 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19088.843082 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19088.843082 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19088.843082 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19088.843082 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19088.843082 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -597,34 +597,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 38810 system.cpu.icache.demand_mshr_misses::total 38810 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 38810 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 38810 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 688057500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 688057500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 688057500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 688057500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 688057500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 688057500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 702029000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 702029000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 702029000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 702029000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 702029000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 702029000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000535 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000535 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000535 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17728.871425 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17728.871425 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17728.871425 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17728.871425 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17728.871425 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17728.871425 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18088.868848 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18088.868848 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18088.868848 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18088.868848 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18088.868848 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18088.868848 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4197.344986 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4197.348676 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 57958 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 10.268958 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 353.814355 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.200376 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 678.330255 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 353.816119 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.200424 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 678.332133 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010798 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.020701 # Average percentage of cache occupancy @@ -664,18 +664,18 @@ system.cpu.l2cache.demand_misses::total 7626 # nu system.cpu.l2cache.overall_misses::cpu.inst 3422 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses system.cpu.l2cache.overall_misses::total 7626 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214130000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 214130000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 258275500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 258275500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104189000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 104189000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 258275500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 318319000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 576594500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 258275500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 318319000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 576594500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214741500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 214741500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 257334000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 257334000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104502500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 104502500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 257334000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 319244000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 576578000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 257334000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 319244000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 576578000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) @@ -702,18 +702,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.176035 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088173 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.176035 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75028.030834 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75028.030834 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75475.014611 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75475.014611 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77177.037037 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77177.037037 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75475.014611 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75718.125595 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75609.034881 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75475.014611 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75718.125595 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75609.034881 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75242.291521 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75242.291521 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75199.883109 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75199.883109 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77409.259259 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77409.259259 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75199.883109 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75938.154139 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75606.871230 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75199.883109 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75938.154139 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75606.871230 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -744,18 +744,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7582 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3420 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7582 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 185590000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 185590000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 223941000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 223941000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88101000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88101000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 223941000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 273691000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 497632000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 223941000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 273691000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 497632000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186201500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186201500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 222999500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 222999500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88418500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88418500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 222999500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 274620000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 497619500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 222999500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 274620000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 497619500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for ReadCleanReq accesses @@ -768,19 +768,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.175019 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.175019 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65028.030834 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65028.030834 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65479.824561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65479.824561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67355.504587 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67355.504587 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65479.824561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65759.490630 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65633.342126 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65479.824561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65759.490630 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65633.342126 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65242.291521 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65242.291521 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65204.532164 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65204.532164 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67598.241590 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67598.241590 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65204.532164 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65982.700625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65631.693485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65204.532164 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65982.700625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65631.693485 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 81548 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 38331 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15017 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 40450 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 22200 # Transaction distribution @@ -796,14 +802,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 2837120 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 81548 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.369574 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.482692 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 81548 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 51410 63.04% 63.04% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 30138 36.96% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 81548 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 41784000 # Layer occupancy (ticks) @@ -831,9 +837,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7582 # Request fanout histogram -system.membus.reqLayer0.occupancy 8861000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8866500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40238250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40241250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index c456278d9..b3c953357 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.112687 # Number of seconds simulated -sim_ticks 112687034500 # Number of ticks simulated -final_tick 112687034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.112728 # Number of seconds simulated +sim_ticks 112728298500 # Number of ticks simulated +final_tick 112728298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 126437 # Simulator instruction rate (inst/s) -host_op_rate 151802 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52182660 # Simulator tick rate (ticks/s) -host_mem_usage 327844 # Number of bytes of host memory used -host_seconds 2159.47 # Real time elapsed on the host +host_inst_rate 116763 # Simulator instruction rate (inst/s) +host_op_rate 140187 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48207604 # Simulator tick rate (ticks/s) +host_mem_usage 330392 # Number of bytes of host memory used +host_seconds 2338.39 # Real time elapsed on the host sim_insts 273037220 # Number of instructions simulated sim_ops 327811602 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 169152 # Number of bytes read from this memory -system.physmem.bytes_read::total 468672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1757 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2643 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7323 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1660102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 997879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1501078 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4159059 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1660102 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1660102 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1660102 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 997879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1501078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4159059 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7323 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 187008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 169408 # Number of bytes read from this memory +system.physmem.bytes_read::total 469184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 187008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 187008 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2922 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1762 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2647 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7331 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1658927 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1000352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1502799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4162078 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1658927 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1658927 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1658927 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1000352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1502799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4162078 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7331 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7323 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7331 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 468672 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 469184 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 468672 # Total read bytes from the system interface side +system.physmem.bytesReadSys 469184 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -50,16 +50,16 @@ system.physmem.perBankRdBursts::1 789 # Pe system.physmem.perBankRdBursts::2 601 # Per bank write bursts system.physmem.perBankRdBursts::3 520 # Per bank write bursts system.physmem.perBankRdBursts::4 444 # Per bank write bursts -system.physmem.perBankRdBursts::5 346 # Per bank write bursts +system.physmem.perBankRdBursts::5 345 # Per bank write bursts system.physmem.perBankRdBursts::6 153 # Per bank write bursts -system.physmem.perBankRdBursts::7 251 # Per bank write bursts +system.physmem.perBankRdBursts::7 255 # Per bank write bursts system.physmem.perBankRdBursts::8 219 # Per bank write bursts system.physmem.perBankRdBursts::9 290 # Per bank write bursts system.physmem.perBankRdBursts::10 315 # Per bank write bursts system.physmem.perBankRdBursts::11 411 # Per bank write bursts system.physmem.perBankRdBursts::12 547 # Per bank write bursts system.physmem.perBankRdBursts::13 678 # Per bank write bursts -system.physmem.perBankRdBursts::14 615 # Per bank write bursts +system.physmem.perBankRdBursts::14 620 # Per bank write bursts system.physmem.perBankRdBursts::15 555 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 112686876000 # Total gap between requests +system.physmem.totGap 112728140000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7323 # Read request sizes (log2) +system.physmem.readPktSize::6 7331 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,20 +94,20 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4012 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1463 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4022 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1455 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 165 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -190,26 +190,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 339.932896 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 197.349943 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 349.457617 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 486 35.45% 35.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 309 22.54% 57.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 132 9.63% 67.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 75 5.47% 73.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 64 4.67% 77.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 48 3.50% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 26 1.90% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 1.82% 84.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 206 15.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1371 # Bytes accessed per row activation -system.physmem.totQLat 95174041 # Total ticks spent queuing -system.physmem.totMemAccLat 232480291 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36615000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12996.59 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1373 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 339.670794 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 197.560456 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 349.691004 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 480 34.96% 34.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 312 22.72% 57.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 141 10.27% 67.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 79 5.75% 73.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 55 4.01% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 48 3.50% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 23 1.68% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 27 1.97% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 208 15.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1373 # Bytes accessed per row activation +system.physmem.totQLat 90206647 # Total ticks spent queuing +system.physmem.totMemAccLat 227662897 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36655000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12304.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31746.59 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31054.82 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.16 # Average system read bandwidth in MiByte/s @@ -218,50 +218,50 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.50 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5943 # Number of row buffer hits during reads +system.physmem.readRowHits 5948 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.13 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15388075.38 # Average gap between requests -system.physmem.pageHitRate 81.16 # Row buffer hit rate, read and write combined +system.physmem.avgGap 15376911.74 # Average gap between requests +system.physmem.pageHitRate 81.13 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 4815720 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 2627625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 28641600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 28618200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3233168820 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 64773630750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 75402764835 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.158858 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 107753956620 # Time in different power states -system.physmem_0.memoryStateTime::REF 3762720000 # Time in different power states +system.physmem_0.refreshEnergy 7362423120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3214163025 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64813639500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 75426287190 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.136639 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 107820696894 # Time in different power states +system.physmem_0.memoryStateTime::REF 3764020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1166688380 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1137632606 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5526360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3015375 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 5511240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3007125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 28126800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3309876000 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 64706325000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 75412749855 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.247655 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 107640832624 # Time in different power states -system.physmem_1.memoryStateTime::REF 3762720000 # Time in different power states +system.physmem_1.refreshEnergy 7362423120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3285750465 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 64750835250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 75435654000 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.219817 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 107714946135 # Time in different power states +system.physmem_1.memoryStateTime::REF 3764020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1279848380 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1243230865 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37743135 # Number of BP lookups -system.cpu.branchPred.condPredicted 20164607 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1746155 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18663607 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17299273 # Number of BTB hits +system.cpu.branchPred.lookups 37743002 # Number of BP lookups +system.cpu.branchPred.condPredicted 20164593 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1746138 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18663724 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17299181 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.689870 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7223670 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.688796 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7223599 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -381,129 +381,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 225374070 # number of cpu cycles simulated +system.cpu.numCycles 225456598 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12439227 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 334051995 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37743135 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24522943 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 210854521 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3510703 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1310 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 2474 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 89092353 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 21704 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 225052883 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.800484 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.229411 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12486047 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 334063522 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37743002 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24522780 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 210891035 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3510673 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1258 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 2507 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 89094273 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 21774 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 225136183 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.799914 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229503 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 51372314 22.83% 22.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42891452 19.06% 41.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30054577 13.35% 55.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100734540 44.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 51412756 22.84% 22.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42958324 19.08% 41.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30027813 13.34% 55.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100737290 44.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 225052883 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.167469 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.482211 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27836779 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63911722 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108618516 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 23065273 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1620593 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6880055 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 135197 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 363544847 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6170021 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1620593 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45199707 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 17872689 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 341815 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 113380410 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46637669 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355768309 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 2890306 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 6609751 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 177931 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7804271 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 21223751 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 2890543 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 403406246 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2534025265 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 350247395 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 194894231 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 225136183 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.167407 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.481720 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27896248 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63927882 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108602791 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 23088664 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1620598 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6880038 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 135173 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 363542969 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6170181 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1620598 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45231914 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 18002517 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 341926 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 113354912 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46584316 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355763735 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 2890412 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 6625666 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 177937 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7803151 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 21129906 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 2817742 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 403401676 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2534003745 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 350242817 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 194894499 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31176195 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 31171625 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 17025 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 55506509 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 92416612 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 88498373 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1661373 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1847329 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 353252571 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 55451024 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 92416595 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 88498352 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1661185 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1846398 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353252669 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 346438287 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2302047 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25468995 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73729207 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 346437634 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2301476 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25469093 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73749076 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 225052883 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.539364 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.099868 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 225136183 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.538791 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.099493 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40665148 18.07% 18.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 78299865 34.79% 52.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 60995131 27.10% 79.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34883362 15.50% 95.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9557615 4.25% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 642958 0.29% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8804 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40701776 18.08% 18.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78366146 34.81% 52.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 60939580 27.07% 79.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34977344 15.54% 95.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9507598 4.22% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 632530 0.28% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11209 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 225052883 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 225136183 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9490613 7.63% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7317 0.01% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 255761 0.21% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 126865 0.10% 7.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 93219 0.07% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 68015 0.05% 8.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 721837 0.58% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 297231 0.24% 8.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 683044 0.55% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53642383 43.14% 52.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58959382 47.42% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9586225 7.69% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7350 0.01% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 255762 0.21% 7.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 132929 0.11% 8.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 93071 0.07% 8.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 61949 0.05% 8.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 719141 0.58% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 303244 0.24% 8.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 683031 0.55% 9.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53752847 43.14% 52.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 59000415 47.35% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 110655137 31.94% 31.94% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148355 0.62% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 110655046 31.94% 31.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148359 0.62% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued @@ -522,93 +522,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6798397 1.96% 34.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6798342 1.96% 34.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8668117 2.50% 37.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8667218 2.50% 37.03% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 3332482 0.96% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592458 0.46% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20930149 6.04% 44.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7182320 2.07% 46.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148962 2.06% 48.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592517 0.46% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20930304 6.04% 44.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7182327 2.07% 46.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148965 2.06% 48.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 91923270 26.53% 75.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85883354 24.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 91923294 26.53% 75.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85883494 24.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 346438287 # Type of FU issued -system.cpu.iq.rate 1.537170 # Inst issue rate -system.cpu.iq.fu_busy_cnt 124345667 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.358926 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 757022758 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 251740405 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 223260402 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 287554413 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 127019437 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 117424930 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 303229780 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 167554174 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5064825 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 346437634 # Type of FU issued +system.cpu.iq.rate 1.536605 # Inst issue rate +system.cpu.iq.fu_busy_cnt 124595964 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.359649 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 757212589 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 251740831 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 223259855 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287696302 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 127019209 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117423886 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 303336303 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 167697295 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5085757 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6684337 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13570 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10254 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6122756 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6684320 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13571 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10256 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6122735 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 155338 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 607759 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 155306 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 607778 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1620593 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2118874 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 332196 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 353281462 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1620598 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2118913 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 332541 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353281560 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 92416612 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 88498373 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 92416595 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 88498352 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8049 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 338656 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10254 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1220664 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 439075 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1659739 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 342448688 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 90703769 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3989599 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 8047 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 339026 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10256 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1220653 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 439070 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1659723 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 342447875 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 90703562 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3989759 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 865 # number of nop insts executed -system.cpu.iew.exec_refs 175291174 # number of memory reference insts executed -system.cpu.iew.exec_branches 31752726 # Number of branches executed -system.cpu.iew.exec_stores 84587405 # Number of stores executed -system.cpu.iew.exec_rate 1.519468 # Inst execution rate -system.cpu.iew.wb_sent 340944051 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 340685332 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153662647 # num instructions producing a value -system.cpu.iew.wb_consumers 266737544 # num instructions consuming a value +system.cpu.iew.exec_refs 175290975 # number of memory reference insts executed +system.cpu.iew.exec_branches 31752712 # Number of branches executed +system.cpu.iew.exec_stores 84587413 # Number of stores executed +system.cpu.iew.exec_rate 1.518908 # Inst execution rate +system.cpu.iew.wb_sent 340942422 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 340683741 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153622639 # num instructions producing a value +system.cpu.iew.wb_consumers 266573014 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.511644 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.576082 # average fanout of values written-back +system.cpu.iew.wb_rate 1.511083 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.576287 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23083260 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23082594 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1611397 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 221327720 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481117 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.050757 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1611400 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 221410973 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.480560 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.051639 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87528718 39.55% 39.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 70478843 31.84% 71.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20814822 9.40% 80.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13433890 6.07% 86.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8801339 3.98% 90.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4513701 2.04% 92.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2986759 1.35% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2449542 1.11% 95.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10320106 4.66% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87667745 39.60% 39.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 70465931 31.83% 71.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20808534 9.40% 80.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13377083 6.04% 86.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8762034 3.96% 90.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4538069 2.05% 92.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3005918 1.36% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2461295 1.11% 95.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10324364 4.66% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 221327720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 221410973 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037832 # Number of instructions committed system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,32 +654,32 @@ system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction -system.cpu.commit.bw_lim_events 10320106 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 561900565 # The number of ROB reads -system.cpu.rob.rob_writes 705520050 # The number of ROB writes -system.cpu.timesIdled 50865 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 321187 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 10324364 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 561978894 # The number of ROB reads +system.cpu.rob.rob_writes 705518745 # The number of ROB writes +system.cpu.timesIdled 51182 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320415 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037220 # Number of Instructions Simulated system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.825434 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.825434 # CPI: Total CPI of All Threads -system.cpu.ipc 1.211485 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.211485 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 331332035 # number of integer regfile reads -system.cpu.int_regfile_writes 136939352 # number of integer regfile writes -system.cpu.fp_regfile_reads 187107868 # number of floating regfile reads -system.cpu.fp_regfile_writes 132178738 # number of floating regfile writes -system.cpu.cc_regfile_reads 1297133606 # number of cc regfile reads -system.cpu.cc_regfile_writes 80241640 # number of cc regfile writes -system.cpu.misc_regfile_reads 1183127847 # number of misc regfile reads +system.cpu.cpi 0.825736 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.825736 # CPI: Total CPI of All Threads +system.cpu.ipc 1.211041 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.211041 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 331331297 # number of integer regfile reads +system.cpu.int_regfile_writes 136939218 # number of integer regfile writes +system.cpu.fp_regfile_reads 187106677 # number of floating regfile reads +system.cpu.fp_regfile_writes 132176732 # number of floating regfile writes +system.cpu.cc_regfile_reads 1297128117 # number of cc regfile reads +system.cpu.cc_regfile_writes 80240781 # number of cc regfile writes +system.cpu.misc_regfile_reads 1183123878 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1533845 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.843427 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 163642817 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1534357 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 106.652374 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 82681000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.843427 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1533840 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.843429 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 163621677 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1534352 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 106.638944 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 82703000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.843429 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999694 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999694 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -688,148 +688,148 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 310 system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336637061 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336637061 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 82609464 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 82609464 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80941053 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80941053 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 70494 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 70494 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 336594804 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336594804 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82588364 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82588364 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80941030 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80941030 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 70477 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 70477 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 163550517 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 163550517 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 163621011 # number of overall hits -system.cpu.dcache.overall_hits::total 163621011 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2796868 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2796868 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1111646 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1111646 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 163529394 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 163529394 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 163599871 # number of overall hits +system.cpu.dcache.overall_hits::total 163599871 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2796859 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2796859 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1111669 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1111669 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3908514 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3908514 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3908532 # number of overall misses -system.cpu.dcache.overall_misses::total 3908532 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22403262000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22403262000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8965991000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8965991000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3908528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3908528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3908546 # number of overall misses +system.cpu.dcache.overall_misses::total 3908546 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22523988500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22523988500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8974716998 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8974716998 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 189000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31369253000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31369253000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31369253000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31369253000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 85406332 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 85406332 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 31498705498 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31498705498 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31498705498 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31498705498 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85385223 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85385223 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 70512 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 70512 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 70495 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 70495 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167459031 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167459031 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167529543 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167529543 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032748 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032748 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 167437922 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167437922 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167508417 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167508417 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032756 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032756 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013548 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013548 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000255 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023340 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023340 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023330 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023330 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8010.124897 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 8010.124897 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8065.509164 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8065.509164 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023343 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023343 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023333 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023333 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8053.315702 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 8053.315702 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8073.191749 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8073.191749 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37800 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37800 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8025.877098 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 8025.877098 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8025.840136 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 8025.840136 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8058.968875 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8058.968875 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8058.931761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8058.931761 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1060412 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1061983 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 134750 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.869477 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.881135 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 966339 # number of writebacks system.cpu.dcache.writebacks::total 966339 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1483175 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1483175 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 890991 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 890991 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1483171 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1483171 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891014 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 891014 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2374166 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2374166 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2374166 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2374166 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313693 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1313693 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2374185 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2374185 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2374185 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2374185 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313688 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1313688 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220655 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 220655 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1534348 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1534348 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1534359 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1534359 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10623648000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10623648000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1826747781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1826747781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 681000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 681000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12450395781 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12450395781 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12451076781 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12451076781 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1534343 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1534343 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1534354 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1534354 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10737741500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10737741500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1828416279 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1828416279 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 682500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 682500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12566157779 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12566157779 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12566840279 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12566840279 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015385 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015385 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002689 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8086.857432 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8086.857432 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8278.750905 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8278.750905 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61909.090909 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61909.090909 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8114.453684 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8114.453684 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8114.839344 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8114.839344 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009164 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.009164 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009160 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.009160 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8173.737980 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8173.737980 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8286.312474 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8286.312474 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62045.454545 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62045.454545 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8189.927402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8189.927402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8190.313499 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8190.313499 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 715635 # number of replacements -system.cpu.icache.tags.tagsinuse 511.829472 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 88370544 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 716147 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 123.397213 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 326419500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.829472 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 715629 # number of replacements +system.cpu.icache.tags.tagsinuse 511.829471 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88372474 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 716141 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 123.400942 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 326432500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.829471 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999667 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999667 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -839,207 +839,208 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 246 system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 178900820 # Number of tag accesses -system.cpu.icache.tags.data_accesses 178900820 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 88370544 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88370544 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88370544 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88370544 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88370544 # number of overall hits -system.cpu.icache.overall_hits::total 88370544 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 721792 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 721792 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 721792 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 721792 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 721792 # number of overall misses -system.cpu.icache.overall_misses::total 721792 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5973239447 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5973239447 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5973239447 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5973239447 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5973239447 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5973239447 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 89092336 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 89092336 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 89092336 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 89092336 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 89092336 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 89092336 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008102 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008102 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008102 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008102 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008102 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008102 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8275.568927 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8275.568927 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8275.568927 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8275.568927 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8275.568927 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8275.568927 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 62302 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 178904656 # Number of tag accesses +system.cpu.icache.tags.data_accesses 178904656 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 88372474 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88372474 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88372474 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88372474 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88372474 # 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average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7785.311370 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7785.311370 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7785.311370 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7785.311370 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7785.311370 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 405270 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 405390 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 107 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 404899 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 404967 # 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average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5937.284846 # average HardPFReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.015617 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5800.587395 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5800.587395 # average HardPFReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68311.901505 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68311.901505 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62490.762915 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62490.762915 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67532.163743 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67532.163743 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62490.762915 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67856.573705 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64505.235043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62490.762915 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67856.573705 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5937.284846 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13744.787820 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68702.300406 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68702.300406 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62035.763176 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62035.763176 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67706.744868 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67706.744868 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62035.763176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68124.290579 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64326.110162 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62035.763176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68124.290579 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5800.587395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13603.546197 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 2029852 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 4499965 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2249489 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 249352 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 27801 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 27801 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 2029841 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 966339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1033896 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 31809 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1033885 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 31840 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 220653 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 220653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 716148 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313704 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2122580 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4377763 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6500343 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45775488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160044544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205820032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 32715 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4531796 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.007019 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.083485 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 716142 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313699 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2122562 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4377748 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6500310 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45775104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160044224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205819328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 32746 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4531805 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.116184 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.320445 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4499987 99.30% 99.30% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 31809 0.70% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4005282 88.38% 88.38% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 526523 11.62% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4531796 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3216332500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4531805 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3216321500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1074486969 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1074578268 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2301554963 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2302086882 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) system.membus.trans_dist::ReadResp 6592 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 731 # Transaction distribution -system.membus.trans_dist::ReadExResp 731 # Transaction distribution +system.membus.trans_dist::ReadExReq 739 # Transaction distribution +system.membus.trans_dist::ReadExResp 739 # Transaction distribution system.membus.trans_dist::ReadSharedReq 6592 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14648 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14648 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 468672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14664 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 469184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 469184 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7324 # Request fanout histogram +system.membus.snoop_fanout::samples 7332 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7324 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7332 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7324 # Request fanout histogram -system.membus.reqLayer0.occupancy 9437390 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7332 # Request fanout histogram +system.membus.reqLayer0.occupancy 9416916 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 38347412 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 38389399 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index b10e642ea..e29d83073 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.517235 # Number of seconds simulated -sim_ticks 517235407500 # Number of ticks simulated -final_tick 517235407500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517243 # Number of seconds simulated +sim_ticks 517243165500 # Number of ticks simulated +final_tick 517243165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 785915 # Simulator instruction rate (inst/s) -host_op_rate 943520 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1490444540 # Simulator tick rate (ticks/s) -host_mem_usage 321320 # Number of bytes of host memory used -host_seconds 347.03 # Real time elapsed on the host +host_inst_rate 702843 # Simulator instruction rate (inst/s) +host_op_rate 843789 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1332923086 # Simulator tick rate (ticks/s) +host_mem_usage 322968 # Number of bytes of host memory used +host_seconds 388.05 # Real time elapsed on the host sim_insts 272739286 # Number of instructions simulated sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 166912 # Nu system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 322700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 522656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 322700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 322700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 322700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 522656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 322695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 522648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 845343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 322695 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 322695 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 322695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 522648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 845343 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1034470815 # number of cpu cycles simulated +system.cpu.numCycles 1034486331 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 272739286 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 168107847 # nu system.cpu.num_load_insts 85732248 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1034470814.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1034486330.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 30563503 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812214 # Class of executed instruction system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.445031 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3078.444355 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445031 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.444355 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id @@ -249,14 +249,14 @@ system.cpu.dcache.demand_misses::cpu.data 4476 # n system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses system.cpu.dcache.overall_misses::total 4479 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78396000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78396000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78469000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78469000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 157423500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 157423500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 235819500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235819500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 235819500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235819500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 235892500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235892500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 235892500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235892500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) @@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48875.311721 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48875.311721 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48920.822943 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48920.822943 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.196379 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.196379 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52685.321716 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52685.321716 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52650.033490 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52650.033490 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52701.630920 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52701.630920 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52666.331770 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52666.331770 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -315,16 +315,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4475 system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76753000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 76753000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76826000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 76826000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 154551500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 154551500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 162000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 162000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 231304500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 231304500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 231466500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 231466500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 231377500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 231377500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 231539500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 231539500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -335,24 +335,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47880.848409 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47880.848409 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47926.388022 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47926.388022 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53813.196379 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53813.196379 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51688.156425 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51688.156425 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51689.705226 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51689.705226 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51704.469274 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51704.469274 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51706.007146 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51706.007146 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1766.007653 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1766.007280 # Cycle average of tags in use system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007653 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007280 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id @@ -376,12 +376,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 312483000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 312483000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 312483000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 312483000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 312483000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 312483000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 320168000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 320168000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 320168000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 320168000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 320168000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 320168000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses @@ -394,12 +394,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20027.110171 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20027.110171 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20027.110171 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20027.110171 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20027.110171 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20027.110171 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20519.643658 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20519.643658 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20519.643658 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20519.643658 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20519.643658 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20519.643658 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -414,34 +414,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 296880000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 296880000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 296880000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 296880000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 296880000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 296880000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 304565000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 304565000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 304565000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 304565000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 304565000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 304565000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19027.110171 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19027.110171 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19027.110171 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19027.110171 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19027.110171 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19027.110171 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19519.643658 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19519.643658 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19519.643658 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19519.643658 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19519.643658 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19519.643658 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.764994 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3487.764139 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.623058 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.427152 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714783 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 341.622938 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.426609 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714591 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073469 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.022544 # Average percentage of cache occupancy @@ -588,6 +588,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42541.219325 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42576.231061 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42562.865925 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6465 # Transaction distribution @@ -603,14 +609,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 35209 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.438041 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.496153 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 35209 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 19786 56.20% 56.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 15423 43.80% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 35209 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 18602500 # Layer occupancy (ticks) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 0cd2c8d2d..dc4595f22 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.560940 # Nu sim_ticks 560939659000 # Number of ticks simulated final_tick 560939659000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 234960 # Simulator instruction rate (inst/s) -host_op_rate 234960 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 141903449 # Simulator tick rate (ticks/s) -host_mem_usage 300504 # Number of bytes of host memory used -host_seconds 3952.97 # Real time elapsed on the host +host_inst_rate 314051 # Simulator instruction rate (inst/s) +host_op_rate 314051 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 189670339 # Simulator tick rate (ticks/s) +host_mem_usage 308244 # Number of bytes of host memory used +host_seconds 2957.45 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -693,6 +693,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65717.636986 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68931.169478 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68899.056478 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1580028 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 787095 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2077 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2077 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 723921 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 155535 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 890983 # Transaction distribution @@ -708,15 +714,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 56434176 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 259423 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1839451 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.141033 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.348056 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001129 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.033584 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1580028 85.90% 85.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 259423 14.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1837374 99.89% 99.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2077 0.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1839451 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 878866000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 4ab8a79d0..4dbf3fd00 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.276406 # Nu sim_ticks 276406029500 # Number of ticks simulated final_tick 276406029500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130885 # Simulator instruction rate (inst/s) -host_op_rate 130885 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42946592 # Simulator tick rate (ticks/s) -host_mem_usage 301528 # Number of bytes of host memory used -host_seconds 6436.04 # Real time elapsed on the host +host_inst_rate 172081 # Simulator instruction rate (inst/s) +host_op_rate 172081 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56464121 # Simulator tick rate (ticks/s) +host_mem_usage 308248 # Number of bytes of host memory used +host_seconds 4895.25 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1000,6 +1000,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68739.058477 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71348.279854 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71323.990701 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1569303 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 781752 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1986 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1986 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 718745 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 155563 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 885494 # Transaction distribution @@ -1015,15 +1021,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 56091520 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 259305 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1828608 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.141805 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.348850 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001086 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.032938 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1569303 85.82% 85.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 259305 14.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1826622 99.89% 99.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1986 0.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1828608 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 873531500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 07561ac8e..f1fff22ed 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.286279 # Nu sim_ticks 1286278511500 # Number of ticks simulated final_tick 1286278511500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1355944 # Simulator instruction rate (inst/s) -host_op_rate 1355944 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1878251411 # Simulator tick rate (ticks/s) -host_mem_usage 303804 # Number of bytes of host memory used -host_seconds 684.83 # Real time elapsed on the host +host_inst_rate 1389844 # Simulator instruction rate (inst/s) +host_op_rate 1389844 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1925210162 # Simulator tick rate (ticks/s) +host_mem_usage 305148 # Number of bytes of host memory used +host_seconds 668.12 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -484,6 +484,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42533.673943 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.207465 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.454765 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1718 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1718 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 155714 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 883916 # Transaction distribution @@ -499,15 +505,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 56046528 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 258580 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1826326 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.141585 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.348624 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000941 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.030656 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1567746 85.84% 85.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 258580 14.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1824608 99.91% 99.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1718 0.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1826326 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 872904000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 53f1e9393..ca22b895a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.542258 # Number of seconds simulated -sim_ticks 542257602500 # Number of ticks simulated -final_tick 542257602500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 542257676500 # Number of ticks simulated +final_tick 542257676500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121737 # Simulator instruction rate (inst/s) -host_op_rate 149875 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 103039759 # Simulator tick rate (ticks/s) -host_mem_usage 317376 # Number of bytes of host memory used -host_seconds 5262.61 # Real time elapsed on the host +host_inst_rate 169610 # Simulator instruction rate (inst/s) +host_op_rate 208813 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 143560034 # Simulator tick rate (ticks/s) +host_mem_usage 325880 # Number of bytes of host memory used +host_seconds 3777.22 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 164672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18470528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 164608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18470592 # Number of bytes read from this memory system.physmem.bytes_read::total 18635200 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 164608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 164608 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2573 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288602 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2572 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288603 # Number of read requests responded to by this memory system.physmem.num_reads::total 291175 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 303679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 34062276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34365954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 303679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 303679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7801222 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7801222 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7801222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 303679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 34062276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42167176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 303560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34062389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34365950 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 303560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 303560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7801221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7801221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7801221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 303560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 34062389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42167171 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 291175 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted system.physmem.readBursts 291175 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18614208 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20992 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 18614336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20864 # Total number of bytes read from write queue system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18635200 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 328 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 326 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 18282 # Per bank write bursts -system.physmem.perBankRdBursts::1 18134 # Per bank write bursts -system.physmem.perBankRdBursts::2 18219 # Per bank write bursts -system.physmem.perBankRdBursts::3 18172 # Per bank write bursts -system.physmem.perBankRdBursts::4 18271 # Per bank write bursts -system.physmem.perBankRdBursts::5 18399 # Per bank write bursts +system.physmem.perBankRdBursts::1 18135 # Per bank write bursts +system.physmem.perBankRdBursts::2 18220 # Per bank write bursts +system.physmem.perBankRdBursts::3 18173 # Per bank write bursts +system.physmem.perBankRdBursts::4 18273 # Per bank write bursts +system.physmem.perBankRdBursts::5 18400 # Per bank write bursts system.physmem.perBankRdBursts::6 18176 # Per bank write bursts -system.physmem.perBankRdBursts::7 17991 # Per bank write bursts -system.physmem.perBankRdBursts::8 18028 # Per bank write bursts +system.physmem.perBankRdBursts::7 17989 # Per bank write bursts +system.physmem.perBankRdBursts::8 18030 # Per bank write bursts system.physmem.perBankRdBursts::9 18057 # Per bank write bursts system.physmem.perBankRdBursts::10 18104 # Per bank write bursts system.physmem.perBankRdBursts::11 18195 # Per bank write bursts -system.physmem.perBankRdBursts::12 18215 # Per bank write bursts -system.physmem.perBankRdBursts::13 18268 # Per bank write bursts -system.physmem.perBankRdBursts::14 18078 # Per bank write bursts -system.physmem.perBankRdBursts::15 18258 # Per bank write bursts +system.physmem.perBankRdBursts::12 18214 # Per bank write bursts +system.physmem.perBankRdBursts::13 18267 # Per bank write bursts +system.physmem.perBankRdBursts::14 18077 # Per bank write bursts +system.physmem.perBankRdBursts::15 18257 # Per bank write bursts system.physmem.perBankWrBursts::0 4171 # Per bank write bursts system.physmem.perBankWrBursts::1 4098 # Per bank write bursts system.physmem.perBankWrBursts::2 4134 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 542257509000 # Total gap between requests +system.physmem.totGap 542257582000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290458 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 377 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -193,24 +193,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 111041 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 205.695554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.912944 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.637901 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45880 41.32% 41.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43577 39.24% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9434 8.50% 89.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1633 1.47% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 111013 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 205.748588 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.953680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.656452 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45849 41.30% 41.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43580 39.26% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9433 8.50% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1634 1.47% 90.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 691 0.62% 91.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 667 0.60% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 515 0.46% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 515 0.46% 92.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 550 0.50% 92.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 8094 7.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 111041 # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 111013 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.509833 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.246439 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.588678 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.510331 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.246707 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.588684 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 4015 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes @@ -224,12 +224,12 @@ system.physmem.wrPerTurnAround::17 1 0.02% 77.65% # Wr system.physmem.wrPerTurnAround::18 897 22.33% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads -system.physmem.totQLat 2871354000 # Total ticks spent queuing -system.physmem.totMemAccLat 8324735250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1454235000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9872.39 # Average queueing delay per DRAM burst +system.physmem.totQLat 2868100000 # Total ticks spent queuing +system.physmem.totMemAccLat 8321518750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1454245000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9861.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28622.39 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28611.13 # Average memory access latency per DRAM burst system.physmem.avgRdBW 34.33 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 34.37 # Average system read bandwidth in MiByte/s @@ -240,47 +240,47 @@ system.physmem.busUtilRead 0.27 # Da system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 26.15 # Average write queue length when enqueuing -system.physmem.readRowHits 194229 # Number of row buffer hits during reads -system.physmem.writeRowHits 51633 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.12 # Row buffer hit rate for writes -system.physmem.avgGap 1517767.95 # Average gap between requests -system.physmem.pageHitRate 68.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 420124320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 229234500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1135836000 # Energy for read commands per rank (pJ) +system.physmem.readRowHits 194250 # Number of row buffer hits during reads +system.physmem.writeRowHits 51642 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.79 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes +system.physmem.avgGap 1517768.15 # Average gap between requests +system.physmem.pageHitRate 68.89 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 419905080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 229114875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1135859400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 215518320 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 35417135520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 107502461415 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 231049769250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 375970079325 # Total energy per rank (pJ) -system.physmem_0.averagePower 693.351550 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 383670371250 # Time in different power states +system.physmem_0.actBackEnergy 107383469355 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 231154143750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 375955146300 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.324021 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 383844481500 # Time in different power states system.physmem_0.memoryStateTime::REF 18106920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 140473012000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 140298894750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 419247360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 228756000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1132271400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 419254920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 228760125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1132255800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 212615280 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 35417135520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 108055650690 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 230564511000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 376030187250 # Total energy per rank (pJ) -system.physmem_1.averagePower 693.462409 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 382864555750 # Time in different power states +system.physmem_1.actBackEnergy 107988829875 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 230623125750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 376021977270 # Total energy per rank (pJ) +system.physmem_1.averagePower 693.447269 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 382962347750 # Time in different power states system.physmem_1.memoryStateTime::REF 18106920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 141281958750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 141184235750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 154805772 # Number of BP lookups +system.cpu.branchPred.lookups 154805770 # Number of BP lookups system.cpu.branchPred.condPredicted 105138293 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 12875884 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90693369 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 90693367 # Number of BTB lookups system.cpu.branchPred.BTBHits 83089320 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.615651 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 91.615653 # BTB Hit Percentage system.cpu.branchPred.usedRAS 19277594 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -401,24 +401,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1084515205 # number of cpu cycles simulated +system.cpu.numCycles 1084515353 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed -system.cpu.discardedOps 23906785 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 23906784 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.692822 # CPI: cycles per instruction +system.cpu.cpi 1.692823 # CPI: cycles per instruction system.cpu.ipc 0.590729 # IPC: instructions per cycle -system.cpu.tickCycles 1025899032 # Number of cycles that the object actually ticked -system.cpu.idleCycles 58616173 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 1025899498 # Number of cycles that the object actually ticked +system.cpu.idleCycles 58615855 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 778339 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.484062 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4092.484054 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378456435 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782435 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.690575 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 792553500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484062 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484054 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999142 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999142 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -454,14 +454,14 @@ system.cpu.dcache.demand_misses::cpu.data 851588 # n system.cpu.dcache.demand_misses::total 851588 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 851729 # number of overall misses system.cpu.dcache.overall_misses::total 851729 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24762813000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24762813000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105718500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10105718500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34868531500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34868531500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34868531500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34868531500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24762143500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24762143500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105570000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10105570000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34867713500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34867713500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34867713500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34867713500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250341582 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250341582 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -486,14 +486,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002246 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002246 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34687.835142 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34687.835142 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73382.991315 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73382.991315 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40945.306298 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40945.306298 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40938.527982 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40938.527982 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34686.897304 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34686.897304 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73381.912978 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73381.912978 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40944.345740 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40944.345740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40937.567583 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40937.567583 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -522,16 +522,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782296 system.cpu.dcache.demand_mshr_misses::total 782296 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782435 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782435 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24034165000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24034165000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067912500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067912500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24033231500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24033231500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067791500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067791500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1855000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1855000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29102077500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29102077500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29103932500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29103932500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29101023000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29101023000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29102878000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29102878000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -542,24 +542,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002063 system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33709.735558 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33709.735558 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73106.841984 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73106.841984 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33708.426254 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33708.426254 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73105.096506 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73105.096506 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13345.323741 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13345.323741 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37200.851724 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37200.851724 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37196.613776 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37196.613776 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37199.503768 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37199.503768 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37195.266060 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37195.266060 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 23591 # number of replacements -system.cpu.icache.tags.tagsinuse 1713.095623 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 291576498 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1713.095615 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 291576499 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 25342 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11505.662458 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11505.662497 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095623 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095615 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.836472 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.836472 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id @@ -567,44 +567,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 58 system.cpu.icache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1600 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 583229024 # Number of tag accesses -system.cpu.icache.tags.data_accesses 583229024 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 291576498 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 291576498 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 291576498 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 291576498 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 291576498 # number of overall hits -system.cpu.icache.overall_hits::total 291576498 # number of overall hits +system.cpu.icache.tags.tag_accesses 583229026 # Number of tag accesses +system.cpu.icache.tags.data_accesses 583229026 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 291576499 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 291576499 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 291576499 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 291576499 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 291576499 # number of overall hits +system.cpu.icache.overall_hits::total 291576499 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 25343 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 25343 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 25343 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 25343 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 25343 # number of overall misses system.cpu.icache.overall_misses::total 25343 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 498098000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 498098000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 498098000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 498098000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 498098000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 498098000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 291601841 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 291601841 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 291601841 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 291601841 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 291601841 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 291601841 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 499290500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 499290500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 499290500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 499290500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 499290500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 499290500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 291601842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 291601842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 291601842 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 291601842 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 291601842 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 291601842 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19654.263505 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19654.263505 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19654.263505 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19654.263505 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19654.263505 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19654.263505 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19701.317918 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19701.317918 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19701.317918 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19701.317918 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19701.317918 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19701.317918 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -619,37 +619,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 25343 system.cpu.icache.demand_mshr_misses::total 25343 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 25343 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 25343 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 472756000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 472756000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 472756000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 472756000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 472756000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 472756000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 473948500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 473948500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 473948500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 473948500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 473948500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 473948500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18654.302963 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18654.302963 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18654.302963 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18654.302963 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18654.302963 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18654.302963 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18701.357377 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18701.357377 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18701.357377 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18701.357377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18701.357377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18701.357377 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 258395 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32574.709364 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32574.709394 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1245326 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 291139 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.277428 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2589.156166 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.700113 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29894.853085 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2589.156414 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.726448 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29895.826532 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.079015 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002768 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.912319 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.912348 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.994101 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id @@ -686,18 +686,18 @@ system.cpu.l2cache.demand_misses::total 291208 # nu system.cpu.l2cache.overall_misses::cpu.inst 2578 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 288630 # number of overall misses system.cpu.l2cache.overall_misses::total 291208 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4930001500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4930001500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195708000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 195708000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17815243000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 17815243000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 195708000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22745244500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22940952500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 195708000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22745244500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22940952500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4929880500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4929880500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195624000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 195624000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17812302500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 17812302500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 195624000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22742183000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22937807000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 195624000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22742183000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22937807000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 88920 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 88920 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) @@ -724,18 +724,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.360505 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101724 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.368887 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.360505 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74594.142924 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78778.579229 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74592.312115 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74592.312115 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75882.079131 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75882.079131 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80041.262430 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80041.262430 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75882.079131 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78793.552299 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78767.777671 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75882.079131 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78793.552299 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78767.777671 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -746,69 +746,75 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 28 # 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number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 376 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 376 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2574 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2574 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222511 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222511 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2574 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65937.451437 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65937.451437 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70056.345529 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70056.345529 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65937.451437 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68805.479519 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68780.126109 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65937.451437 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68805.479519 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68780.126109 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64592.312115 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64592.312115 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65908.666926 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65908.666926 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70043.074081 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70043.074081 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65908.666926 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68794.832348 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68769.328516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65908.666926 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68794.832348 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68769.328516 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1609708 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 801990 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3351 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2028 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2013 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 738455 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 155018 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 901956 # Transaction distribution @@ -824,21 +830,21 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 57388608 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 258395 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1868103 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.138319 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.345235 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004713 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.068609 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1609708 86.17% 86.17% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 258395 13.83% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1859313 99.53% 99.53% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8775 0.47% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1868103 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 893774000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 38014996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 38015495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1173666472 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1173665973 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.trans_dist::ReadResp 225084 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution @@ -861,9 +867,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 547917 # Request fanout histogram -system.membus.reqLayer0.occupancy 917948500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 917954000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1554418250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1554429500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 85998f5be..8ea31b650 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.410670 # Number of seconds simulated -sim_ticks 410669815000 # Number of ticks simulated -final_tick 410669815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.410968 # Number of seconds simulated +sim_ticks 410968419000 # Number of ticks simulated +final_tick 410968419000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94058 # Simulator instruction rate (inst/s) -host_op_rate 115798 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60293323 # Simulator tick rate (ticks/s) -host_mem_usage 320128 # Number of bytes of host memory used -host_seconds 6811.20 # Real time elapsed on the host +host_inst_rate 85599 # Simulator instruction rate (inst/s) +host_op_rate 105384 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54910730 # Simulator tick rate (ticks/s) +host_mem_usage 322152 # Number of bytes of host memory used +host_seconds 7484.30 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 232448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7026304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12953152 # Number of bytes read from this memory -system.physmem.bytes_read::total 20211904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 232448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 232448 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4244928 # Number of bytes written to this memory -system.physmem.bytes_written::total 4244928 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3632 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 109786 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 202393 # Number of read requests responded to by this memory -system.physmem.num_reads::total 315811 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66327 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66327 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 566022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17109375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 31541524 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 49216921 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 566022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 566022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 10336596 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10336596 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 10336596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 566022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17109375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 31541524 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59553517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 315811 # Number of read requests accepted -system.physmem.writeReqs 66327 # Number of write requests accepted -system.physmem.readBursts 315811 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66327 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 20192576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue -system.physmem.bytesWritten 4239424 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 20211904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4244928 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 58 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 18 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19865 # Per bank write bursts -system.physmem.perBankRdBursts::1 19533 # Per bank write bursts -system.physmem.perBankRdBursts::2 19787 # Per bank write bursts -system.physmem.perBankRdBursts::3 19881 # Per bank write bursts -system.physmem.perBankRdBursts::4 19767 # Per bank write bursts -system.physmem.perBankRdBursts::5 20312 # Per bank write bursts -system.physmem.perBankRdBursts::6 19558 # Per bank write bursts -system.physmem.perBankRdBursts::7 19499 # Per bank write bursts -system.physmem.perBankRdBursts::8 19473 # Per bank write bursts -system.physmem.perBankRdBursts::9 19475 # Per bank write bursts -system.physmem.perBankRdBursts::10 19453 # Per bank write bursts -system.physmem.perBankRdBursts::11 19704 # Per bank write bursts -system.physmem.perBankRdBursts::12 19596 # Per bank write bursts -system.physmem.perBankRdBursts::13 20052 # Per bank write bursts -system.physmem.perBankRdBursts::14 19574 # Per bank write bursts -system.physmem.perBankRdBursts::15 19980 # Per bank write bursts -system.physmem.perBankWrBursts::0 4265 # Per bank write bursts -system.physmem.perBankWrBursts::1 4106 # Per bank write bursts -system.physmem.perBankWrBursts::2 4140 # Per bank write bursts -system.physmem.perBankWrBursts::3 4153 # Per bank write bursts -system.physmem.perBankWrBursts::4 4250 # Per bank write bursts -system.physmem.perBankWrBursts::5 4230 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 226432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7007424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12927040 # Number of bytes read from this memory +system.physmem.bytes_read::total 20160896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 226432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 226432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4244672 # Number of bytes written to this memory +system.physmem.bytes_written::total 4244672 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3538 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 109491 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 201985 # Number of read requests responded to by this memory +system.physmem.num_reads::total 315014 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66323 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66323 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 550972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17051004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 31455069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 49057044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 550972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 550972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 10328463 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10328463 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 10328463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 550972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17051004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 31455069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59385507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 315014 # Number of read requests accepted +system.physmem.writeReqs 66323 # Number of write requests accepted +system.physmem.readBursts 315014 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66323 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 20141440 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19456 # Total number of bytes read from write queue +system.physmem.bytesWritten 4238400 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 20160896 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4244672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 304 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 67 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 16 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19880 # Per bank write bursts +system.physmem.perBankRdBursts::1 19436 # Per bank write bursts +system.physmem.perBankRdBursts::2 19769 # Per bank write bursts +system.physmem.perBankRdBursts::3 19866 # Per bank write bursts +system.physmem.perBankRdBursts::4 19687 # Per bank write bursts +system.physmem.perBankRdBursts::5 20154 # Per bank write bursts +system.physmem.perBankRdBursts::6 19548 # Per bank write bursts +system.physmem.perBankRdBursts::7 19410 # Per bank write bursts +system.physmem.perBankRdBursts::8 19409 # Per bank write bursts +system.physmem.perBankRdBursts::9 19464 # Per bank write bursts +system.physmem.perBankRdBursts::10 19401 # Per bank write bursts +system.physmem.perBankRdBursts::11 19757 # Per bank write bursts +system.physmem.perBankRdBursts::12 19512 # Per bank write bursts +system.physmem.perBankRdBursts::13 19953 # Per bank write bursts +system.physmem.perBankRdBursts::14 19499 # Per bank write bursts +system.physmem.perBankRdBursts::15 19965 # Per bank write bursts +system.physmem.perBankWrBursts::0 4261 # Per bank write bursts +system.physmem.perBankWrBursts::1 4104 # Per bank write bursts +system.physmem.perBankWrBursts::2 4143 # Per bank write bursts +system.physmem.perBankWrBursts::3 4151 # Per bank write bursts +system.physmem.perBankWrBursts::4 4243 # Per bank write bursts +system.physmem.perBankWrBursts::5 4228 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4096 # Per bank write bursts +system.physmem.perBankWrBursts::8 4095 # Per bank write bursts +system.physmem.perBankWrBursts::9 4094 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4095 # Per bank write bursts -system.physmem.perBankWrBursts::14 4093 # Per bank write bursts -system.physmem.perBankWrBursts::15 4156 # Per bank write bursts +system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::14 4096 # Per bank write bursts +system.physmem.perBankWrBursts::15 4153 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 410669760500 # Total gap between requests +system.physmem.totGap 410968364500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 315811 # Read request sizes (log2) +system.physmem.readPktSize::6 315014 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66327 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 122285 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9282 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66323 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 121710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120019 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14305 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7602 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 9380 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 8107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3822 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2905 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 942 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2934 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1023 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,165 +148,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 75 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4657 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 136666 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.756150 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.878617 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 198.405742 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 53923 39.46% 39.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57606 42.15% 81.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14740 10.79% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1412 1.03% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1397 1.02% 94.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1387 1.01% 95.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1267 0.93% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1142 0.84% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3792 2.77% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 136666 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4031 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 73.293227 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.720611 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 661.085009 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4010 99.48% 99.48% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 10 0.25% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 2 0.05% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 2 0.05% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-6143 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 1 0.02% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::11264-12287 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::19456-20479 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::26624-27647 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4031 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4031 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.432895 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.394232 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.238105 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3399 84.32% 84.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3 0.07% 84.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 453 11.24% 95.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 84 2.08% 97.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 29 0.72% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 17 0.42% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 10 0.25% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 13 0.32% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 10 0.25% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.05% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 3 0.07% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.05% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 3 0.07% 99.95% # Writes before turning the bus around for reads +system.physmem.bytesPerActivate::samples 136515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.576479 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 128.708862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.239774 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54117 39.64% 39.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57190 41.89% 81.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14847 10.88% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1353 0.99% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1460 1.07% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1428 1.05% 95.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1211 0.89% 96.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1099 0.81% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3810 2.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 136515 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4034 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 69.350768 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.698276 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 557.584511 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4013 99.48% 99.48% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 9 0.22% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 4 0.10% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.07% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::11264-12287 2 0.05% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4034 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4034 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.416708 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.380496 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.197000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3413 84.61% 84.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 10 0.25% 84.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 440 10.91% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 77 1.91% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 36 0.89% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 18 0.45% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 14 0.35% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.25% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 4 0.10% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.07% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.10% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.02% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::31 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4031 # Writes before turning the bus around for reads -system.physmem.totQLat 8703208249 # Total ticks spent queuing -system.physmem.totMemAccLat 14619001999 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1577545000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27584.66 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::36 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4034 # Writes before turning the bus around for reads +system.physmem.totQLat 8815753021 # Total ticks spent queuing +system.physmem.totMemAccLat 14716565521 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1573550000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28012.31 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46334.66 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 49.17 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 10.32 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 49.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 10.34 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46762.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 49.01 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 10.31 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 49.06 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 10.33 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.46 # Data bus utilization in percentage system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.17 # Average write queue length when enqueuing -system.physmem.readRowHits 218486 # Number of row buffer hits during reads -system.physmem.writeRowHits 26585 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.12 # Row buffer hit rate for writes -system.physmem.avgGap 1074663.50 # Average gap between requests -system.physmem.pageHitRate 64.19 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 519334200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 283366875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1233694800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216522720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26822471520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96824469870 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 161463849000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 287363708985 # Total energy per rank (pJ) -system.physmem_0.averagePower 699.756123 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 267972811336 # Time in different power states -system.physmem_0.memoryStateTime::REF 13712920000 # Time in different power states +system.physmem.avgWrQLen 25.40 # Average write queue length when enqueuing +system.physmem.readRowHits 218109 # Number of row buffer hits during reads +system.physmem.writeRowHits 26303 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.70 # Row buffer hit rate for writes +system.physmem.avgGap 1077703.88 # Average gap between requests +system.physmem.pageHitRate 64.16 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 518041440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 282661500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1230403200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216432000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26842305360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96374724480 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 162040566750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 287505134730 # Total energy per rank (pJ) +system.physmem_0.averagePower 699.583184 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 268934392735 # Time in different power states +system.physmem_0.memoryStateTime::REF 13723060000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 128976939914 # Time in different power states +system.physmem_0.memoryStateTime::ACT 128308892015 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 513679320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 280281375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1226604600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212718960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26822471520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96486689295 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 161760147750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 287302592820 # Total energy per rank (pJ) -system.physmem_1.averagePower 699.607300 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 268468666587 # Time in different power states -system.physmem_1.memoryStateTime::REF 13712920000 # Time in different power states +system.physmem_1.actEnergy 513943920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 280425750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1224030600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26842305360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96023770920 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 162348426750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 287445609300 # Total energy per rank (pJ) +system.physmem_1.averagePower 699.438325 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 269449023468 # Time in different power states +system.physmem_1.memoryStateTime::REF 13723060000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 128482733413 # Time in different power states +system.physmem_1.memoryStateTime::ACT 127794271282 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 234660907 # Number of BP lookups -system.cpu.branchPred.condPredicted 161885632 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15514558 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 122787051 # Number of BTB lookups -system.cpu.branchPred.BTBHits 109471469 # Number of BTB hits +system.cpu.branchPred.lookups 234596987 # Number of BP lookups +system.cpu.branchPred.condPredicted 161823961 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15514568 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 122849584 # Number of BTB lookups +system.cpu.branchPred.BTBHits 109536151 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.155549 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25674321 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300177 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.162818 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25674290 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300140 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -425,95 +421,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 821339631 # number of cpu cycles simulated +system.cpu.numCycles 821936839 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 85359172 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200831144 # Number of instructions fetch has processed -system.cpu.fetch.Branches 234660907 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 135145790 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 720108706 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31063537 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2772 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 85359069 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1200718249 # Number of instructions fetch has processed +system.cpu.fetch.Branches 234596987 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135210441 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 720713354 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31063509 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2336 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3327 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 371279487 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652622 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 821005776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.826136 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.165203 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3414 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 371348285 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652804 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 821609958 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.824964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.165392 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 139284134 16.97% 16.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 223266821 27.19% 44.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 99362992 12.10% 56.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 359091829 43.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 139667844 17.00% 17.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 223418217 27.19% 44.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 99581089 12.12% 56.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 358942808 43.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 821005776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285705 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.462040 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 121274951 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 160921163 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484660075 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38631496 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518091 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 25119096 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13828 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248135517 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39967011 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518091 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 178281745 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 80150846 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 211317 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464319561 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 82524216 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190646555 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 25420306 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24957441 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2267221 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 41531798 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1705173 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1225452951 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5812557102 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358174955 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876459 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 821609958 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285420 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.460840 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 121271680 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 161528221 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484660379 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38631604 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518074 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 25181978 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13827 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248136929 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39965779 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518074 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 178276857 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 80769172 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 209944 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464321622 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 82514289 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190649625 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 25545503 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24955076 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2266892 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 41524383 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1701930 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1225389846 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5812446196 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358179405 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876479 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 350674721 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 7267 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 350611616 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 7266 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108777970 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 366242931 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236095379 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1613389 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5371796 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1168681315 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12359 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017114082 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18565562 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 379968716 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1032836656 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 205 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 821005776 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.238863 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.084756 # Number of insts issued each cycle +system.cpu.rename.skidInsts 108773290 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 366116518 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236097454 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1660812 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5332652 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1168559259 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12361 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1017121345 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18467813 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 379846662 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1032147150 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 207 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 821609958 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.237961 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.084868 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 263349245 32.08% 32.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 227125536 27.66% 59.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 217733280 26.52% 86.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 96668881 11.77% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16128827 1.96% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 263952395 32.13% 32.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 227112360 27.64% 59.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 217754382 26.50% 86.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96663071 11.77% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16127742 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 821005776 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 821609958 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 63875016 18.90% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18146 0.01% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 63877670 18.90% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18143 0.01% 18.90% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 18.90% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.90% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.90% # attempts to use FU when none available @@ -541,13 +537,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.09% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 157510134 46.60% 65.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 115986364 34.31% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 157438093 46.58% 65.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116037067 34.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456370249 44.87% 44.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5195831 0.51% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456371832 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5195828 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued @@ -571,88 +567,88 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 2550148 0.25% 46.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478997 1.13% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322123387 31.67% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215570268 21.19% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322111232 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215588105 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017114082 # Type of FU issued -system.cpu.iq.rate 1.238360 # Inst issue rate -system.cpu.iq.fu_busy_cnt 338026549 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.332339 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3149949023 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1505114950 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934262178 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61877028 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565833 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 26152444 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1321330304 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33810327 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9960611 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1017121345 # Type of FU issued +system.cpu.iq.rate 1.237469 # Inst issue rate +system.cpu.iq.fu_busy_cnt 338007862 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.332318 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3150451328 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1504870795 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934275536 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61876995 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565857 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 26152450 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1321318894 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 33810313 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9960669 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 114001993 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1099 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18396 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107114883 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 113875580 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1094 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18373 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 107116958 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065819 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19975 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065804 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 20149 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518091 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35326945 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 43224 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1168699230 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 15518074 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35327155 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 46316 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1168577176 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 366242931 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236095379 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6619 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 99 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 46833 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18396 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437302 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784553 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19221855 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974739392 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303297512 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42374690 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 366116518 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236097454 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6621 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 106 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 49932 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18373 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15437332 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784565 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19221897 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 974752675 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303297711 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42368670 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 5556 # number of nop insts executed -system.cpu.iew.exec_refs 497752889 # number of memory reference insts executed -system.cpu.iew.exec_branches 150613606 # Number of branches executed -system.cpu.iew.exec_stores 194455377 # Number of stores executed -system.cpu.iew.exec_rate 1.186768 # Inst execution rate -system.cpu.iew.wb_sent 963712681 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960414622 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536046271 # num instructions producing a value -system.cpu.iew.wb_consumers 893280305 # num instructions consuming a value +system.cpu.iew.exec_refs 497765117 # number of memory reference insts executed +system.cpu.iew.exec_branches 150613949 # Number of branches executed +system.cpu.iew.exec_stores 194467406 # Number of stores executed +system.cpu.iew.exec_rate 1.185922 # Inst execution rate +system.cpu.iew.wb_sent 963726327 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960427986 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536047777 # num instructions producing a value +system.cpu.iew.wb_consumers 893284950 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.169327 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600087 # average fanout of values written-back +system.cpu.iew.wb_rate 1.168494 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600086 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 357416983 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357420302 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15500881 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 770184473 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.024079 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.777435 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15500888 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 770788105 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.023277 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.776928 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 431571304 56.03% 56.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174376243 22.64% 78.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72936565 9.47% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 32893073 4.27% 92.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8539337 1.11% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14258396 1.85% 95.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7274917 0.94% 96.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5974456 0.78% 97.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22360182 2.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 432159906 56.07% 56.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174391468 22.63% 78.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72936790 9.46% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 32897876 4.27% 92.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8538896 1.11% 93.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14258442 1.85% 95.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7269703 0.94% 96.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5974810 0.78% 97.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22360214 2.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 770184473 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 770788105 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -698,80 +694,80 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 22360182 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1893962593 # The number of ROB reads -system.cpu.rob.rob_writes 2343119332 # The number of ROB writes -system.cpu.timesIdled 647411 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 333855 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 22360214 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1894569512 # The number of ROB reads +system.cpu.rob.rob_writes 2343126520 # The number of ROB writes +system.cpu.timesIdled 647387 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 326881 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.282043 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.282043 # CPI: Total CPI of All Threads -system.cpu.ipc 0.780005 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.780005 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995778090 # number of integer regfile reads -system.cpu.int_regfile_writes 567907785 # number of integer regfile writes -system.cpu.fp_regfile_reads 31889840 # number of floating regfile reads +system.cpu.cpi 1.282975 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.282975 # CPI: Total CPI of All Threads +system.cpu.ipc 0.779439 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.779439 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995803218 # number of integer regfile reads +system.cpu.int_regfile_writes 567908989 # number of integer regfile writes +system.cpu.fp_regfile_reads 31889842 # number of floating regfile reads system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794401386 # number of cc regfile reads -system.cpu.cc_regfile_writes 384898061 # number of cc regfile writes -system.cpu.misc_regfile_reads 715805814 # number of misc regfile reads +system.cpu.cc_regfile_reads 3794442903 # number of cc regfile reads +system.cpu.cc_regfile_writes 384898512 # number of cc regfile writes +system.cpu.misc_regfile_reads 715818410 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2756185 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.933524 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414216512 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756697 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.258266 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 256787000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.933524 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999870 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999870 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2756184 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.933181 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414216914 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756696 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.258467 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 257783000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.933181 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999869 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839346679 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839346679 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286293684 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286293684 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127908123 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127908123 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 839346712 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839346712 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286294274 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286294274 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127907939 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127907939 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414201807 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414201807 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414204964 # number of overall hits -system.cpu.dcache.overall_hits::total 414204964 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3034548 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3034548 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1043354 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1043354 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 414202213 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414202213 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414205370 # number of overall hits +system.cpu.dcache.overall_hits::total 414205370 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3033975 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3033975 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1043538 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1043538 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4077902 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4077902 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4078548 # number of overall misses -system.cpu.dcache.overall_misses::total 4078548 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35018337000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35018337000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10025314350 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10025314350 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 188000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 188000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45043651350 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45043651350 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45043651350 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45043651350 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289328232 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289328232 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4077513 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4077513 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4078159 # number of overall misses +system.cpu.dcache.overall_misses::total 4078159 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35335718000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35335718000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10020788350 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10020788350 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 187500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45356506350 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45356506350 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45356506350 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45356506350 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289328249 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289328249 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3803 # number of SoftPFReq accesses(hits+misses) @@ -780,72 +776,72 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418279709 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418279709 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418283512 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418283512 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010488 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010488 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008091 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008091 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 418279726 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418279726 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418283529 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418283529 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010486 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010486 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008092 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008092 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169866 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.169866 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009749 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009749 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009751 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009751 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11539.885677 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11539.885677 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9608.737159 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9608.737159 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11045.790544 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11045.790544 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11044.041004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11044.041004 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009748 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009748 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009750 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009750 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11646.674083 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11646.674083 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9602.705747 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9602.705747 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11123.571243 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11123.571243 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11121.809216 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11121.809216 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 356457 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 355417 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4730 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4792 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 75.360888 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 74.168823 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 735102 # number of writebacks -system.cpu.dcache.writebacks::total 735102 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999338 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 999338 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322490 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 322490 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 735485 # number of writebacks +system.cpu.dcache.writebacks::total 735485 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 998769 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 998769 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322672 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 322672 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30092528850 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30092528850 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses @@ -856,231 +852,233 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11703.506763 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11703.506763 # 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number of cycles access was blocked @@ -1089,153 +1087,159 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66327 # number of writebacks -system.cpu.l2cache.writebacks::total 66327 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1069 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1069 # number of ReadExReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 66323 # number of writebacks +system.cpu.l2cache.writebacks::total 66323 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1105 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1105 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 9 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7934847500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 244477000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7690370500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16906807287 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24841654787 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 2080 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 2089 # number of overall MSHR hits +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 8868 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 8868 # number of CleanEvict MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202062 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 202062 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1377 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1377 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3538 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3538 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 108114 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 108114 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3538 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 109491 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 139099000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 240756500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 240756500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7531984000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7531984000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 240756500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7671083000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7911839500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 240756500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7671083000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17000279164 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24912118664 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001913 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001913 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000703 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000703 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.053249 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.053249 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000703 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039825 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014308 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000703 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039825 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000684 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.053105 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.053105 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039718 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014260 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039718 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.039851 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83502.777137 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83502.777137 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16777.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16777.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 103645.757796 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 103645.757796 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67311.949339 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67311.949339 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69621.362089 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69621.362089 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67311.949339 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70048.735722 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69961.095241 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67311.949339 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70048.735722 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83502.777137 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78640.704259 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.039751 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84133.974542 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84133.974542 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17187.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17187.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 101015.976761 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 101015.976761 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68048.756360 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68048.756360 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69667.055145 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69667.055145 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68048.756360 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70061.310975 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69998.314592 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68048.756360 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70061.310975 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84133.974542 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79063.250502 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 7205861 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 801429 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6779490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 246291 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5170011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035851 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508607 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626218 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23134825 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330879552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223475136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 554354688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 545836 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 16398212 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.033285 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.179381 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 15852127 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 7925581 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644320 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 9549 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 9495 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 54 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 7205725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 801808 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6778141 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 245737 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5169879 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035847 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508216 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626183 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23134399 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330871168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223499584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 554370752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 544470 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 16396581 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.079179 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.270031 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 15852393 96.67% 96.67% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 545819 3.33% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 15098363 92.08% 92.08% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1298164 7.92% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 54 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 16398212 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 8661298500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 16396581 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 8661548500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7755038952 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7754847439 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135066975 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4135063977 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 314432 # Transaction distribution -system.membus.trans_dist::Writeback 66327 # Transaction distribution -system.membus.trans_dist::CleanEvict 232586 # Transaction distribution -system.membus.trans_dist::UpgradeReq 18 # Transaction distribution -system.membus.trans_dist::UpgradeResp 18 # Transaction distribution -system.membus.trans_dist::ReadExReq 1379 # Transaction distribution -system.membus.trans_dist::ReadExResp 1379 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 314432 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 930571 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 930571 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24456832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24456832 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 313637 # Transaction distribution +system.membus.trans_dist::Writeback 66323 # Transaction distribution +system.membus.trans_dist::CleanEvict 231789 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16 # Transaction distribution +system.membus.trans_dist::UpgradeResp 16 # Transaction distribution +system.membus.trans_dist::ReadExReq 1377 # Transaction distribution +system.membus.trans_dist::ReadExResp 1377 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 313637 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 928172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 928172 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24405568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24405568 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 614742 # Request fanout histogram +system.membus.snoop_fanout::samples 613142 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 614742 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 613142 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 614742 # Request fanout histogram -system.membus.reqLayer0.occupancy 978145707 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 613142 # Request fanout histogram +system.membus.reqLayer0.occupancy 975944720 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1654146686 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1649749525 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 627fd964a..24851d5c1 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.043722 # Number of seconds simulated -sim_ticks 1043722398500 # Number of ticks simulated -final_tick 1043722398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.043724 # Number of seconds simulated +sim_ticks 1043723537500 # Number of ticks simulated +final_tick 1043723537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 921530 # Simulator instruction rate (inst/s) -host_op_rate 1132156 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1504334297 # Simulator tick rate (ticks/s) -host_mem_usage 320916 # Number of bytes of host memory used -host_seconds 693.81 # Real time elapsed on the host +host_inst_rate 832063 # Simulator instruction rate (inst/s) +host_op_rate 1022241 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1358287943 # Simulator tick rate (ticks/s) +host_mem_usage 323064 # Number of bytes of host memory used +host_seconds 768.41 # Real time elapsed on the host sim_insts 639366787 # Number of instructions simulated sim_ops 785501035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,16 +26,16 @@ system.physmem.num_reads::total 290359 # Nu system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 108473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17696046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17804520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17696027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17804500 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 108473 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 108473 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4053062 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4053062 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4053062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 4053058 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4053058 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4053058 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 108473 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17696046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21857582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17696027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21857558 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 2087444797 # number of cpu cycles simulated +system.cpu.numCycles 2087447075 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 639366787 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 381221435 # nu system.cpu.num_load_insts 252240938 # Number of load instructions system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 2087444796.998000 # Number of busy cycles +system.cpu.num_busy_cycles 2087447074.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 137364860 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.640641 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4093.640237 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 996416500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640641 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 996538500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640237 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 782004 # n system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses system.cpu.dcache.overall_misses::total 782143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18609964000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18609964000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18611031000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18611031000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677169000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 3677169000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22287133000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22287133000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22287133000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22287133000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22288200000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22288200000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22288200000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22288200000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26112.614199 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26112.614199 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26114.111363 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26114.111363 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.996942 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.996942 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28500.024297 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28500.024297 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28494.959362 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28494.959362 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28501.388740 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28501.388740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28496.323562 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28496.323562 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003 system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17897244000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17897244000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17898311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17898311000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3607846000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3607846000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1752000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1752000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21505090000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21505090000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21506842000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21506842000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21506157000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21506157000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21507909000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21507909000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -342,24 +342,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25112.594713 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25112.594713 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25114.091879 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25114.091879 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52043.996942 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52043.996942 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12604.316547 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27500.009591 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27500.009591 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27497.362372 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27497.362372 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27501.374036 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27501.374036 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27498.726574 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27498.726574 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 8769 # number of replacements -system.cpu.icache.tags.tagsinuse 1391.464534 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1391.464458 # Cycle average of tags in use system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464534 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464458 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id @@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst 10208 # n system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses system.cpu.icache.overall_misses::total 10208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 207153000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 207153000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 207153000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 207153000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 207153000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 207153000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 207225000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 207225000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 207225000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 207225000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 207225000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 207225000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses @@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20293.201411 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20293.201411 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20293.201411 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20293.201411 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20293.201411 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20293.201411 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20300.254702 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20300.254702 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20300.254702 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20300.254702 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,34 +419,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10208 system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 196945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 196945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196945000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 196945000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 197017000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 197017000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 197017000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 197017000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 197017000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 197017000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19293.201411 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19293.201411 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19293.201411 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19293.201411 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19293.201411 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19293.201411 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19300.254702 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19300.254702 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 257579 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32626.732272 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32626.728627 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1218059 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 290322 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.195545 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2506.606006 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754528 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.371738 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2506.605810 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754609 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.368207 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.076496 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001488 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.917705 # Average percentage of cache occupancy @@ -490,14 +490,14 @@ system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3469946000 system.cpu.l2cache.ReadExReq_miss_latency::total 3469946000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 93021000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 93021000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11681386500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 11681386500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11681407500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 11681407500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 93021000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15151332500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15244353500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15151353500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15244374500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 93021000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15151332500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15244353500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15151353500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15244374500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 89072 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 89072 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses) @@ -528,14 +528,14 @@ system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.960767 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.960767 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52583.945732 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52583.945732 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.321366 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.321366 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.415749 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.415749 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52583.945732 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.238782 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.742670 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.814995 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52583.945732 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.238782 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.742670 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.814995 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -564,14 +564,14 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2809016000 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2809016000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 75331000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 75331000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456416500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456416500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456437500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456437500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75331000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265432500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12340763500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265453500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12340784500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75331000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265432500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12340763500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265453500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12340784500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses @@ -590,15 +590,21 @@ system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.960767 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.960767 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42583.945732 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42583.945732 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.321366 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.321366 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.415749 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.415749 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.238782 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.742670 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.238782 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.742670 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 155170 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 888114 # Transaction distribution @@ -614,14 +620,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 56411008 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 257579 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1836744 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.140237 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.347233 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002089 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045741 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1579165 85.98% 85.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 257579 14.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1832914 99.79% 99.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3823 0.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1836744 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 878654500 # Layer occupancy (ticks) diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index c8b76a216..15844baba 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.059549 # Nu sim_ticks 59549031000 # Number of ticks simulated final_tick 59549031000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 231283 # Simulator instruction rate (inst/s) -host_op_rate 231283 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 155732739 # Simulator tick rate (ticks/s) -host_mem_usage 299636 # Number of bytes of host memory used -host_seconds 382.38 # Real time elapsed on the host +host_inst_rate 320796 # Simulator instruction rate (inst/s) +host_op_rate 320796 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 216005540 # Simulator tick rate (ticks/s) +host_mem_usage 307628 # Number of bytes of host memory used +host_seconds 275.68 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -696,6 +696,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69204.949482 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71145.404318 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71054.207489 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 713379 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 353617 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4025 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4025 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 216203 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 282838 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 203224 # Transaction distribution @@ -711,15 +717,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 33805696 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 132445 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 845824 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.156587 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.363411 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004759 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.068819 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 713379 84.34% 84.34% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 132445 15.66% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 841799 99.52% 99.52% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4025 0.48% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 845824 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 525142500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 92f71955f..bea1e6fc8 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.022357 # Nu sim_ticks 22356634500 # Number of ticks simulated final_tick 22356634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 154709 # Simulator instruction rate (inst/s) -host_op_rate 154709 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43456447 # Simulator tick rate (ticks/s) -host_mem_usage 300660 # Number of bytes of host memory used -host_seconds 514.46 # Real time elapsed on the host +host_inst_rate 213363 # Simulator instruction rate (inst/s) +host_op_rate 213363 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59931818 # Simulator tick rate (ticks/s) +host_mem_usage 308400 # Number of bytes of host memory used +host_seconds 373.03 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -994,6 +994,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71321.278328 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94900.154472 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 93853.287262 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 591735 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 292795 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4025 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4025 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 155540 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 283136 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 141723 # Transaction distribution @@ -1009,15 +1015,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 29934528 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 132064 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 723799 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.182459 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.386223 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005561 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.074364 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 591735 81.75% 81.75% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 132064 18.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 719774 99.44% 99.44% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4025 0.56% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 723799 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 464655500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 227ff6a79..67f744153 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.056986 # Number of seconds simulated -sim_ticks 56986224500 # Number of ticks simulated -final_tick 56986224500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.056991 # Number of seconds simulated +sim_ticks 56991022500 # Number of ticks simulated +final_tick 56991022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135704 # Simulator instruction rate (inst/s) -host_op_rate 173546 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 109049636 # Simulator tick rate (ticks/s) -host_mem_usage 317176 # Number of bytes of host memory used -host_seconds 522.57 # Real time elapsed on the host +host_inst_rate 186679 # Simulator instruction rate (inst/s) +host_op_rate 238735 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 150024942 # Simulator tick rate (ticks/s) +host_mem_usage 325676 # Number of bytes of host memory used +host_seconds 379.88 # Real time elapsed on the host sim_insts 70915128 # Number of instructions simulated sim_ops 90690084 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,24 +25,24 @@ system.physmem.num_reads::cpu.data 123811 # Nu system.physmem.num_reads::total 128791 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86157 # Number of write requests responded to by this memory system.physmem.num_writes::total 86157 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5592931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 139049464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 144642395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5592931 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5592931 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 96761069 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 96761069 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 96761069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5592931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 139049464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 241403464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 5592460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 139037758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 144630218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5592460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5592460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 96752923 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 96752923 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 96752923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5592460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 139037758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 241383141 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 128791 # Number of read requests accepted system.physmem.writeReqs 86157 # Number of write requests accepted system.physmem.readBursts 128791 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 86157 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 8242176 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 5512000 # Total number of bytes written to DRAM +system.physmem.bytesWritten 5512640 # Total number of bytes written to DRAM system.physmem.bytesReadSys 8242624 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5514048 # Total written bytes from the system interface side system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue @@ -66,15 +66,15 @@ system.physmem.perBankRdBursts::14 7975 # Pe system.physmem.perBankRdBursts::15 7995 # Per bank write bursts system.physmem.perBankWrBursts::0 5393 # Per bank write bursts system.physmem.perBankWrBursts::1 5541 # Per bank write bursts -system.physmem.perBankWrBursts::2 5463 # Per bank write bursts -system.physmem.perBankWrBursts::3 5328 # Per bank write bursts +system.physmem.perBankWrBursts::2 5464 # Per bank write bursts +system.physmem.perBankWrBursts::3 5326 # Per bank write bursts system.physmem.perBankWrBursts::4 5352 # Per bank write bursts -system.physmem.perBankWrBursts::5 5545 # Per bank write bursts -system.physmem.perBankWrBursts::6 5246 # Per bank write bursts +system.physmem.perBankWrBursts::5 5547 # Per bank write bursts +system.physmem.perBankWrBursts::6 5252 # Per bank write bursts system.physmem.perBankWrBursts::7 5180 # Per bank write bursts system.physmem.perBankWrBursts::8 5155 # Per bank write bursts system.physmem.perBankWrBursts::9 5101 # Per bank write bursts -system.physmem.perBankWrBursts::10 5289 # Per bank write bursts +system.physmem.perBankWrBursts::10 5292 # Per bank write bursts system.physmem.perBankWrBursts::11 5270 # Per bank write bursts system.physmem.perBankWrBursts::12 5531 # Per bank write bursts system.physmem.perBankWrBursts::13 5597 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 5703 # Pe system.physmem.perBankWrBursts::15 5431 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 56986193500 # Total gap between requests +system.physmem.totGap 56990990500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 86157 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 116650 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,26 +144,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5464 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 5299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -193,98 +193,98 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38656 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 355.735099 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 216.399320 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.915140 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12161 31.46% 31.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8166 21.12% 52.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4096 10.60% 63.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2818 7.29% 70.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2687 6.95% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1672 4.33% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1300 3.36% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1153 2.98% 88.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4603 11.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38656 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5291 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.313362 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 352.121472 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5289 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38662 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 355.683203 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 216.343519 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.125731 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12148 31.42% 31.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8177 21.15% 52.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4090 10.58% 63.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2852 7.38% 70.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2693 6.97% 77.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1623 4.20% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1296 3.35% 85.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1161 3.00% 88.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4622 11.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38662 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5293 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.322124 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 352.056892 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5291 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5291 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5291 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.277641 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.260577 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.779844 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4640 87.70% 87.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 6 0.11% 87.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 513 9.70% 97.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 107 2.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 18 0.34% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 4 0.08% 99.94% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5293 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5293 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.273380 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.256688 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.768255 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4654 87.93% 87.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 4 0.08% 88.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 500 9.45% 97.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 109 2.06% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 18 0.34% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 5 0.09% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5291 # Writes before turning the bus around for reads -system.physmem.totQLat 1688662500 # Total ticks spent queuing -system.physmem.totMemAccLat 4103362500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrPerTurnAround::23 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5293 # Writes before turning the bus around for reads +system.physmem.totQLat 1683428000 # Total ticks spent queuing +system.physmem.totMemAccLat 4098128000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 643920000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13112.36 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13071.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31862.36 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 144.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31821.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 144.62 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 96.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 144.64 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 96.76 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 144.63 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 96.75 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.89 # Data bus utilization in percentage system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.57 # Average write queue length when enqueuing -system.physmem.readRowHits 112105 # Number of row buffer hits during reads -system.physmem.writeRowHits 64137 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.44 # Row buffer hit rate for writes -system.physmem.avgGap 265116.18 # Average gap between requests +system.physmem.avgWrQLen 23.51 # Average write queue length when enqueuing +system.physmem.readRowHits 112096 # Number of row buffer hits during reads +system.physmem.writeRowHits 64153 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.46 # Row buffer hit rate for writes +system.physmem.avgGap 265138.50 # Average gap between requests system.physmem.pageHitRate 82.00 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 152069400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 82974375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512194800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 278951040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3721642080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11693696490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 23930394000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 40371922185 # Total energy per rank (pJ) -system.physmem_0.averagePower 708.527477 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 39682710000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1902680000 # Time in different power states +system.physmem_0.actEnergy 151963560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 82916625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512397600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 278957520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3722150640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11726025750 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 23906742000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40381153695 # Total energy per rank (pJ) +system.physmem_0.averagePower 708.591931 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 39643767750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1902940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15394661250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15441187500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 140086800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76436250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 491673000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 140313600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76560000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 491751000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 279138960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3721642080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11090732535 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24459309750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 40259019375 # Total energy per rank (pJ) -system.physmem_1.averagePower 706.546032 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40563908250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1902680000 # Time in different power states +system.physmem_1.refreshEnergy 3722150640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11059172775 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24491665500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40260752475 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.479908 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40617302250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1902940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14513554250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14467595250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14800511 # Number of BP lookups -system.cpu.branchPred.condPredicted 9905691 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 381680 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9439152 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6732150 # Number of BTB hits +system.cpu.branchPred.lookups 14800541 # Number of BP lookups +system.cpu.branchPred.condPredicted 9905717 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 381681 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9438549 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6732145 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.321555 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1714112 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 71.326059 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1714124 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -404,67 +404,67 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 113972449 # number of cpu cycles simulated +system.cpu.numCycles 113982045 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915128 # Number of instructions committed system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1144886 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1144890 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.607167 # CPI: cycles per instruction -system.cpu.ipc 0.622213 # IPC: instructions per cycle -system.cpu.tickCycles 95596263 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18376186 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.607302 # CPI: cycles per instruction +system.cpu.ipc 0.622161 # IPC: instructions per cycle +system.cpu.tickCycles 95587829 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18394216 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 156435 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.140403 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42624247 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4067.142814 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42624094 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 160531 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.520348 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 822680500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.140403 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992954 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992954 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 265.519395 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 822760500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.142814 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992955 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992955 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1113 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2936 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1110 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2940 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86016733 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86016733 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22866807 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22866807 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642189 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642189 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83413 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83413 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86016729 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86016729 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22866654 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22866654 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642187 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642187 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83415 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83415 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42508996 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42508996 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42592409 # number of overall hits -system.cpu.dcache.overall_hits::total 42592409 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 51550 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 51550 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207712 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207712 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 44592 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 44592 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 259262 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 259262 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 303854 # number of overall misses -system.cpu.dcache.overall_misses::total 303854 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1489104500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1489104500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16802314000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16802314000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18291418500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18291418500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18291418500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18291418500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22918357 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22918357 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42508841 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42508841 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42592256 # number of overall hits +system.cpu.dcache.overall_hits::total 42592256 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 51701 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 51701 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207714 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207714 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44590 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44590 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 259415 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 259415 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 304005 # number of overall misses +system.cpu.dcache.overall_misses::total 304005 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1492164500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1492164500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16804934500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16804934500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18297099000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18297099000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18297099000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18297099000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22918355 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22918355 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 128005 # number of SoftPFReq accesses(hits+misses) @@ -473,28 +473,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42768258 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42768258 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42896263 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42896263 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002249 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002249 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 42768256 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42768256 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42896261 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42896261 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002256 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002256 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348361 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.348361 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006062 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007083 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007083 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28886.605238 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28886.605238 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80892.360576 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80892.360576 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70551.868380 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70551.868380 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60198.050709 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60198.050709 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348346 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.348346 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007087 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007087 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28861.424344 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28861.424344 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80904.197599 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80904.197599 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70532.155041 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70532.155041 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60186.835743 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60186.835743 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -505,14 +505,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 128400 # number of writebacks system.cpu.dcache.writebacks::total 128400 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22032 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 22032 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100684 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100684 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 122716 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 122716 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 122716 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 122716 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22183 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22183 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100686 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100686 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 122869 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 122869 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 122869 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 122869 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29518 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 29518 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107028 # number of WriteReq MSHR misses @@ -523,16 +523,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136546 system.cpu.dcache.demand_mshr_misses::total 136546 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 160531 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 160531 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 574723500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 574723500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8485443000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8485443000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1719503000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1719503000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9060166500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9060166500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10779669500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10779669500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 578376000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 578376000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8484284000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8484284000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1716349500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1716349500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9062660000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9062660000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10779009500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10779009500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -543,70 +543,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19470.272376 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19470.272376 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79282.458796 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79282.458796 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71690.765061 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71690.765061 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66352.485609 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66352.485609 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67150.080047 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67150.080047 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19594.010434 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19594.010434 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79271.629854 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79271.629854 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71559.287054 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71559.287054 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66370.746855 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66370.746855 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67145.968691 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67145.968691 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42865 # number of replacements -system.cpu.icache.tags.tagsinuse 1852.538301 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24941041 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44907 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 555.393168 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 42866 # number of replacements +system.cpu.icache.tags.tagsinuse 1852.547846 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24941084 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44908 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 555.381758 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1852.538301 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.904560 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.904560 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1852.547846 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904564 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904564 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50016805 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50016805 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24941041 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24941041 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24941041 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24941041 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24941041 # number of overall hits -system.cpu.icache.overall_hits::total 24941041 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44908 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44908 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44908 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 44908 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 44908 # number of overall misses -system.cpu.icache.overall_misses::total 44908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 926324500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 926324500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 926324500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 926324500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 926324500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 926324500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24985949 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24985949 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24985949 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24985949 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24985949 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24985949 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 50016894 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50016894 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24941084 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24941084 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24941084 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24941084 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24941084 # number of overall hits +system.cpu.icache.overall_hits::total 24941084 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 44909 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 44909 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 44909 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 44909 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 44909 # number of overall misses +system.cpu.icache.overall_misses::total 44909 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 929470000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 929470000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 929470000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 929470000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 929470000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 929470000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24985993 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24985993 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24985993 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24985993 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24985993 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24985993 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001797 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001797 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001797 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001797 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001797 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001797 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20627.159971 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20627.159971 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20627.159971 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20627.159971 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20627.159971 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20627.159971 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20696.742301 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20696.742301 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20696.742301 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20696.742301 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20696.742301 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20696.742301 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,67 +615,67 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44908 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 44908 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 44908 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 44908 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 44908 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 44908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 881417500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 881417500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 881417500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 881417500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 881417500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 881417500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44909 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 44909 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 44909 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 44909 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 44909 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 44909 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 884562000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 884562000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 884562000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 884562000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 884562000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 884562000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001797 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001797 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001797 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19627.182239 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19627.182239 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19627.182239 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19627.182239 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19627.182239 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19627.182239 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19696.764568 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19696.764568 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19696.764568 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19696.764568 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19696.764568 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19696.764568 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 95654 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29860.809495 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 161643 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 29860.905704 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 161645 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 126772 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.275069 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.275084 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26579.265460 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1620.835593 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1660.708442 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.811135 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049464 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.050681 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.911280 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 26579.253739 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1620.855600 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1660.796365 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.811134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049465 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.050683 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.911283 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1806 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12714 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15870 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1809 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12704 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15880 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 604 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3409200 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3409200 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 3409216 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3409216 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 128400 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 128400 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 39917 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 39917 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 39918 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 39918 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31903 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 31903 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 39917 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 39918 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 36655 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 76572 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 39917 # number of overall hits +system.cpu.l2cache.demand_hits::total 76573 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 39918 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 36655 # number of overall hits -system.cpu.l2cache.overall_hits::total 76572 # number of overall hits +system.cpu.l2cache.overall_hits::total 76573 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 102276 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 102276 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4991 # number of ReadCleanReq misses @@ -688,56 +688,56 @@ system.cpu.l2cache.demand_misses::total 128867 # nu system.cpu.l2cache.overall_misses::cpu.inst 4991 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 123876 # number of overall misses system.cpu.l2cache.overall_misses::total 128867 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8274960000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8274960000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 394876000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 394876000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1878573500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1878573500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 394876000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10153533500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10548409500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 394876000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10153533500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10548409500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8273802000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8273802000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 394300500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 394300500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1875098000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1875098000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 394300500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10148900000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10543200500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 394300500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10148900000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10543200500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 128400 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 128400 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107028 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107028 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 44908 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 44908 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 44909 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 44909 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53503 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 53503 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 44908 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 44909 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 160531 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 205439 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 44908 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 205440 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 44909 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 160531 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 205439 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 205440 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955600 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.955600 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.111138 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.111138 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.111136 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.111136 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403716 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403716 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.111138 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.111136 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.771664 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.627276 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.111138 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.627273 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.111136 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.771664 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.627276 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80908.130940 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80908.130940 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79117.611701 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79117.611701 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86970.995370 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86970.995370 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79117.611701 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81965.299977 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81855.009428 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79117.611701 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81965.299977 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81855.009428 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.627273 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80896.808635 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80896.808635 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79002.304147 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79002.304147 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86810.092593 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86810.092593 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79002.304147 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81927.895638 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81814.587908 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79002.304147 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81927.895638 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81814.587908 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -772,75 +772,81 @@ system.cpu.l2cache.demand_mshr_misses::total 128792 system.cpu.l2cache.overall_mshr_misses::cpu.inst 4981 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 123811 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128792 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7252200000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7252200000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 344388000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 344388000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1658643500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1658643500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 344388000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8910843500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9255231500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 344388000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8910843500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9255231500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7251042000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7251042000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 343845500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 343845500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1655136500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1655136500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 343845500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8906178500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9250024000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 343845500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8906178500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9250024000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955600 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955600 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.110916 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110916 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110913 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402501 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402501 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.110916 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.626911 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.110916 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.626908 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.626911 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70908.130940 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70908.130940 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69140.333266 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69140.333266 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77020.826561 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77020.826561 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69140.333266 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71971.339380 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71861.850891 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69140.333266 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71971.339380 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71861.850891 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.626908 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70896.808635 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70896.808635 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69031.419394 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69031.419394 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76857.975389 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76857.975389 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69031.419394 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71933.660983 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71821.417479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69031.419394 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71933.660983 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71821.417479 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 98410 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 404741 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 199337 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7814 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3360 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 98411 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 214557 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 72583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 72584 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 44908 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 44909 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 53503 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129101 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129104 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473262 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 602363 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2874048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 602366 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2874112 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21365632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 21365696 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 95654 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 500393 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.191158 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.393213 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 500395 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.038076 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.191682 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 404739 80.88% 80.88% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 95654 19.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 481371 96.20% 96.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 18995 3.80% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 500393 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 330769500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 500395 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 330770500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 67366488 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 67369485 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 240828935 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 240829933 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) system.membus.trans_dist::ReadResp 26515 # Transaction distribution system.membus.trans_dist::Writeback 86157 # Transaction distribution @@ -863,9 +869,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 222458 # Request fanout histogram -system.membus.reqLayer0.occupancy 591536000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 591531500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 679701000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 679686000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index c156cc0a5..4fc60452d 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033333 # Number of seconds simulated -sim_ticks 33333078000 # Number of ticks simulated -final_tick 33333078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033346 # Number of seconds simulated +sim_ticks 33346420000 # Number of ticks simulated +final_tick 33346420000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125008 # Simulator instruction rate (inst/s) -host_op_rate 159871 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58765299 # Simulator tick rate (ticks/s) -host_mem_usage 325044 # Number of bytes of host memory used -host_seconds 567.22 # Real time elapsed on the host +host_inst_rate 116263 # Simulator instruction rate (inst/s) +host_op_rate 148687 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54676178 # Simulator tick rate (ticks/s) +host_mem_usage 326572 # Number of bytes of host memory used +host_seconds 609.89 # Real time elapsed on the host sim_insts 70907630 # Number of instructions simulated sim_ops 90682585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 591360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2521216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6195328 # Number of bytes read from this memory -system.physmem.bytes_read::total 9307904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 591360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 591360 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6264192 # Number of bytes written to this memory -system.physmem.bytes_written::total 6264192 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9240 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 39394 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96802 # Number of read requests responded to by this memory -system.physmem.num_reads::total 145436 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97878 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97878 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 17740936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75637059 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 185861264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 279239259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 17740936 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 17740936 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 187927200 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 187927200 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 187927200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 17740936 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75637059 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 185861264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 467166458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 145436 # Number of read requests accepted -system.physmem.writeReqs 97878 # Number of write requests accepted -system.physmem.readBursts 145436 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97878 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9300544 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 6263104 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9307904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6264192 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 581760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2519040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6191552 # Number of bytes read from this memory +system.physmem.bytes_read::total 9292352 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 581760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 581760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6257152 # Number of bytes written to this memory +system.physmem.bytes_written::total 6257152 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9090 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 39360 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96743 # Number of read requests responded to by this memory +system.physmem.num_reads::total 145193 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97768 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97768 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 17445951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75541542 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 185673665 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 278661158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 17445951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 17445951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 187640892 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 187640892 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 187640892 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 17445951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75541542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 185673665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 466302050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 145193 # Number of read requests accepted +system.physmem.writeReqs 97768 # Number of write requests accepted +system.physmem.readBursts 145193 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97768 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9285376 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue +system.physmem.bytesWritten 6255360 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9292352 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6257152 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9151 # Per bank write bursts -system.physmem.perBankRdBursts::1 9416 # Per bank write bursts -system.physmem.perBankRdBursts::2 9264 # Per bank write bursts -system.physmem.perBankRdBursts::3 9524 # Per bank write bursts -system.physmem.perBankRdBursts::4 9728 # Per bank write bursts -system.physmem.perBankRdBursts::5 9774 # Per bank write bursts -system.physmem.perBankRdBursts::6 9086 # Per bank write bursts -system.physmem.perBankRdBursts::7 9016 # Per bank write bursts -system.physmem.perBankRdBursts::8 9170 # Per bank write bursts -system.physmem.perBankRdBursts::9 8620 # Per bank write bursts -system.physmem.perBankRdBursts::10 8843 # Per bank write bursts -system.physmem.perBankRdBursts::11 8715 # Per bank write bursts -system.physmem.perBankRdBursts::12 8697 # Per bank write bursts -system.physmem.perBankRdBursts::13 8672 # Per bank write bursts -system.physmem.perBankRdBursts::14 8700 # Per bank write bursts -system.physmem.perBankRdBursts::15 8945 # Per bank write bursts -system.physmem.perBankWrBursts::0 6002 # Per bank write bursts -system.physmem.perBankWrBursts::1 6227 # Per bank write bursts -system.physmem.perBankWrBursts::2 6156 # Per bank write bursts -system.physmem.perBankWrBursts::3 6165 # Per bank write bursts -system.physmem.perBankWrBursts::4 6066 # Per bank write bursts -system.physmem.perBankWrBursts::5 6338 # Per bank write bursts -system.physmem.perBankWrBursts::6 6039 # Per bank write bursts -system.physmem.perBankWrBursts::7 6021 # Per bank write bursts -system.physmem.perBankWrBursts::8 6032 # Per bank write bursts -system.physmem.perBankWrBursts::9 6183 # Per bank write bursts -system.physmem.perBankWrBursts::10 6239 # Per bank write bursts -system.physmem.perBankWrBursts::11 5928 # Per bank write bursts -system.physmem.perBankWrBursts::12 6101 # Per bank write bursts -system.physmem.perBankWrBursts::13 6124 # Per bank write bursts -system.physmem.perBankWrBursts::14 6211 # Per bank write bursts -system.physmem.perBankWrBursts::15 6029 # Per bank write bursts +system.physmem.perBankRdBursts::0 9137 # Per bank write bursts +system.physmem.perBankRdBursts::1 9395 # Per bank write bursts +system.physmem.perBankRdBursts::2 9161 # Per bank write bursts +system.physmem.perBankRdBursts::3 9548 # Per bank write bursts +system.physmem.perBankRdBursts::4 9715 # Per bank write bursts +system.physmem.perBankRdBursts::5 9765 # Per bank write bursts +system.physmem.perBankRdBursts::6 9098 # Per bank write bursts +system.physmem.perBankRdBursts::7 9032 # Per bank write bursts +system.physmem.perBankRdBursts::8 9205 # Per bank write bursts +system.physmem.perBankRdBursts::9 8593 # Per bank write bursts +system.physmem.perBankRdBursts::10 8826 # Per bank write bursts +system.physmem.perBankRdBursts::11 8653 # Per bank write bursts +system.physmem.perBankRdBursts::12 8623 # Per bank write bursts +system.physmem.perBankRdBursts::13 8667 # Per bank write bursts +system.physmem.perBankRdBursts::14 8699 # Per bank write bursts +system.physmem.perBankRdBursts::15 8967 # Per bank write bursts +system.physmem.perBankWrBursts::0 5976 # Per bank write bursts +system.physmem.perBankWrBursts::1 6230 # Per bank write bursts +system.physmem.perBankWrBursts::2 6094 # Per bank write bursts +system.physmem.perBankWrBursts::3 6205 # Per bank write bursts +system.physmem.perBankWrBursts::4 6124 # Per bank write bursts +system.physmem.perBankWrBursts::5 6340 # Per bank write bursts +system.physmem.perBankWrBursts::6 6054 # Per bank write bursts +system.physmem.perBankWrBursts::7 6041 # Per bank write bursts +system.physmem.perBankWrBursts::8 6001 # Per bank write bursts +system.physmem.perBankWrBursts::9 6103 # Per bank write bursts +system.physmem.perBankWrBursts::10 6248 # Per bank write bursts +system.physmem.perBankWrBursts::11 5916 # Per bank write bursts +system.physmem.perBankWrBursts::12 6074 # Per bank write bursts +system.physmem.perBankWrBursts::13 6102 # Per bank write bursts +system.physmem.perBankWrBursts::14 6204 # Per bank write bursts +system.physmem.perBankWrBursts::15 6028 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33332792500 # Total gap between requests +system.physmem.totGap 33346162500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 145436 # Read request sizes (log2) +system.physmem.readPktSize::6 145193 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97878 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 41531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 55128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5987 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4599 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97768 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 41267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 55036 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14561 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,32 +148,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7862 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 6877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -197,102 +197,102 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88939 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 174.992388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 110.439382 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 239.025071 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 52267 58.77% 58.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22760 25.59% 84.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4436 4.99% 89.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1732 1.95% 91.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1066 1.20% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 777 0.87% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 661 0.74% 94.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 818 0.92% 95.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4422 4.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88939 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5911 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.584503 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 21.105941 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 187.238550 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5910 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 88566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.437436 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 110.610569 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 239.212794 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52129 58.86% 58.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22374 25.26% 84.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4601 5.19% 89.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1696 1.91% 91.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1069 1.21% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 812 0.92% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 692 0.78% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 790 0.89% 95.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4403 4.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88566 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5908 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.550271 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 21.061813 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 186.955752 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5907 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5911 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5911 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.555744 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.512900 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.266741 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4704 79.58% 79.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 36 0.61% 80.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 781 13.21% 93.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 157 2.66% 96.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 88 1.49% 97.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 64 1.08% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 47 0.80% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 14 0.24% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 17 0.29% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5908 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5908 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.543670 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.503041 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.228970 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4711 79.74% 79.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 35 0.59% 80.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 768 13.00% 93.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 163 2.76% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 108 1.83% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 61 1.03% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 38 0.64% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.17% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 10 0.17% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.05% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5911 # Writes before turning the bus around for reads -system.physmem.totQLat 7028707749 # Total ticks spent queuing -system.physmem.totMemAccLat 9753476499 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 726605000 # Total ticks spent in databus transfers -system.physmem.avgQLat 48366.77 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5908 # Writes before turning the bus around for reads +system.physmem.totQLat 7011292666 # Total ticks spent queuing +system.physmem.totMemAccLat 9731617666 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 725420000 # Total ticks spent in databus transfers +system.physmem.avgQLat 48325.75 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 67116.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 279.02 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 187.89 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 279.24 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 187.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 67075.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 278.45 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 187.59 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 278.66 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 187.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.65 # Data bus utilization in percentage +system.physmem.busUtil 3.64 # Data bus utilization in percentage system.physmem.busUtilRead 2.18 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.47 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.82 # Average write queue length when enqueuing -system.physmem.readRowHits 118079 # Number of row buffer hits during reads -system.physmem.writeRowHits 36164 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.95 # Row buffer hit rate for writes -system.physmem.avgGap 136994.96 # Average gap between requests -system.physmem.pageHitRate 63.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 343934640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 187662750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 584680200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 317610720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2177145360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11782825965 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 9664105500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25057965135 # Total energy per rank (pJ) -system.physmem_0.averagePower 751.742046 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 15979863754 # Time in different power states -system.physmem_0.memoryStateTime::REF 1112800000 # Time in different power states +system.physmem.avgRdQLen 1.62 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.60 # Average write queue length when enqueuing +system.physmem.readRowHits 118088 # Number of row buffer hits during reads +system.physmem.writeRowHits 36158 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.39 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 36.98 # Row buffer hit rate for writes +system.physmem.avgGap 137249.03 # Average gap between requests +system.physmem.pageHitRate 63.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 342241200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 186738750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 583385400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 317818080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2177653920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11790659475 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 9661917750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25060414575 # Total energy per rank (pJ) +system.physmem_0.averagePower 751.639504 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 15978647517 # Time in different power states +system.physmem_0.memoryStateTime::REF 1113320000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16240286246 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16249048233 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 328444200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179210625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 548823600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 316528560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2177145360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11298113640 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 10089291750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 24937557735 # Total energy per rank (pJ) -system.physmem_1.averagePower 748.129809 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 16691408912 # Time in different power states -system.physmem_1.memoryStateTime::REF 1112800000 # Time in different power states +system.physmem_1.actEnergy 326909520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 178373250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 547528800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 315329760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2177653920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11234568330 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 10149705000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 24930068580 # Total energy per rank (pJ) +system.physmem_1.averagePower 747.730472 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 16793127980 # Time in different power states +system.physmem_1.memoryStateTime::REF 1113320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15528741088 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15434548270 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17206633 # Number of BP lookups -system.cpu.branchPred.condPredicted 11518078 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 648316 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9346074 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7675410 # Number of BTB hits +system.cpu.branchPred.lookups 17208509 # Number of BP lookups +system.cpu.branchPred.condPredicted 11519539 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 648302 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9342884 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7675123 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.124430 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1873047 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101552 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.149398 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1872388 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101556 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,129 +411,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 66666157 # number of cpu cycles simulated +system.cpu.numCycles 66692841 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5010938 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88191821 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17206633 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9548457 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60137734 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1322663 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 6978 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 23 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13644 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22767110 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69105 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 65830648 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.695372 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.296604 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5046776 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88195647 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17208509 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9547511 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60140641 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1322595 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 6428 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 25 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13633 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22763338 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69414 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 65868800 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.694437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.296898 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20050738 30.46% 30.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8265796 12.56% 43.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9200690 13.98% 56.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28313424 43.01% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20089005 30.50% 30.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8265359 12.55% 43.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9198123 13.96% 57.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28316313 42.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 65830648 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258101 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.322887 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8588438 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 19545167 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31574635 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5630215 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 492193 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3180012 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171001 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101409826 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3046686 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 492193 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13345278 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5337889 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 804170 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32233077 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13618041 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99203464 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 983266 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3848076 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 66970 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4316860 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5302934 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103925476 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457709098 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115412648 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 65868800 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258026 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.322416 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8616725 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 19555814 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31576285 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5627882 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 492094 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3179727 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171045 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101400911 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3043244 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 492094 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13372904 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5353130 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 801467 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32232883 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13616322 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99196979 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 981006 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3848899 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 63135 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4311075 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5311261 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103921430 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457681852 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115406862 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10296250 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18661 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18653 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12703257 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24321959 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21992794 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1408685 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2344134 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98166936 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34525 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94895750 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 693672 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7518876 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20249831 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 65830648 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.441513 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.149732 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 10292204 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18659 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18650 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12699652 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24320213 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21993792 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1400092 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2341142 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98161647 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34523 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94891012 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 695609 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7513585 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20245943 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 737 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 65868800 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.440606 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.149928 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17559708 26.67% 26.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17428340 26.47% 53.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17111473 25.99% 79.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11681013 17.74% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2049145 3.11% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 969 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17598833 26.72% 26.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17429188 26.46% 53.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17113322 25.98% 79.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11675618 17.73% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2050869 3.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 970 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 65830648 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 65868800 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6713649 22.39% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 39 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11199453 37.36% 59.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12066123 40.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6712111 22.40% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 39 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11183885 37.33% 59.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12062879 40.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49496629 52.16% 52.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89874 0.09% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49494737 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89878 0.09% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued @@ -561,84 +561,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.25% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24067515 25.36% 77.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21241694 22.38% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24064392 25.36% 77.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21241967 22.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94895750 # Type of FU issued -system.cpu.iq.rate 1.423447 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29979264 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315918 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 286294877 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105731606 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93465380 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 94891012 # Type of FU issued +system.cpu.iq.rate 1.422807 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29958914 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315719 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 286305140 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105721004 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93462242 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124874896 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 124849808 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1362273 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 1363438 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1455697 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2068 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11776 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1437056 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1453951 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2082 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11760 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1438054 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 140882 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 184054 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 138729 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 184462 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 492193 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 620956 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 467696 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98211315 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 492094 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 624554 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 468032 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98206039 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24321959 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21992794 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18605 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1621 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 463138 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11776 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 302825 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221559 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 524384 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93978064 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23759823 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 917686 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24320213 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21993792 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18603 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1634 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 463552 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11760 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 302690 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221650 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 524340 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93974044 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23757485 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 916968 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9854 # number of nop insts executed -system.cpu.iew.exec_refs 44744798 # number of memory reference insts executed -system.cpu.iew.exec_branches 14251807 # Number of branches executed -system.cpu.iew.exec_stores 20984975 # Number of stores executed -system.cpu.iew.exec_rate 1.409682 # Inst execution rate -system.cpu.iew.wb_sent 93587077 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93465437 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44977935 # num instructions producing a value -system.cpu.iew.wb_consumers 76555853 # num instructions consuming a value +system.cpu.iew.exec_nop 9869 # number of nop insts executed +system.cpu.iew.exec_refs 44742217 # number of memory reference insts executed +system.cpu.iew.exec_branches 14251815 # Number of branches executed +system.cpu.iew.exec_stores 20984732 # Number of stores executed +system.cpu.iew.exec_rate 1.409057 # Inst execution rate +system.cpu.iew.wb_sent 93584291 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93462299 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44972986 # num instructions producing a value +system.cpu.iew.wb_consumers 76550519 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.401992 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587518 # average fanout of values written-back +system.cpu.iew.wb_rate 1.401384 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587494 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6538600 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6533064 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 479178 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 64771963 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.400114 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.164673 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 479099 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 64811353 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.399263 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.164401 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31176340 48.13% 48.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16804620 25.94% 74.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4339366 6.70% 80.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4157771 6.42% 87.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1944331 3.00% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1263277 1.95% 92.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 736800 1.14% 93.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 578701 0.89% 94.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3770757 5.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31214732 48.16% 48.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16807105 25.93% 74.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4339311 6.70% 80.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4161583 6.42% 87.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1937068 2.99% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1261836 1.95% 92.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 738743 1.14% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 580049 0.89% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3770926 5.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 64771963 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 64811353 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913182 # Number of instructions committed system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -684,386 +684,386 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction -system.cpu.commit.bw_lim_events 3770757 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 158202644 # The number of ROB reads -system.cpu.rob.rob_writes 195513856 # The number of ROB writes -system.cpu.timesIdled 23729 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 835509 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3770926 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 158236329 # The number of ROB reads +system.cpu.rob.rob_writes 195501562 # The number of ROB writes +system.cpu.timesIdled 24613 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 824041 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907630 # Number of Instructions Simulated system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.940183 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.940183 # CPI: Total CPI of All Threads -system.cpu.ipc 1.063623 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.063623 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102275291 # number of integer regfile reads -system.cpu.int_regfile_writes 56793629 # number of integer regfile writes +system.cpu.cpi 0.940559 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.940559 # CPI: Total CPI of All Threads +system.cpu.ipc 1.063197 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.063197 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102271310 # number of integer regfile reads +system.cpu.int_regfile_writes 56791274 # number of integer regfile writes system.cpu.fp_regfile_reads 36 # number of floating regfile reads system.cpu.fp_regfile_writes 21 # number of floating regfile writes -system.cpu.cc_regfile_reads 346102642 # number of cc regfile reads -system.cpu.cc_regfile_writes 38804681 # number of cc regfile writes -system.cpu.misc_regfile_reads 44209969 # number of misc regfile reads +system.cpu.cc_regfile_reads 346086877 # number of cc regfile reads +system.cpu.cc_regfile_writes 38805113 # number of cc regfile writes +system.cpu.misc_regfile_reads 44208470 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.replacements 485047 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.741433 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40420740 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485559 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.245785 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 153056500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.741433 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997542 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997542 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 485016 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.742621 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40419295 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485528 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.248124 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 152905500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.742621 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997544 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997544 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84615723 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84615723 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21498446 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21498446 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18830779 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18830779 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60221 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60221 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15346 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15346 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84611982 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84611982 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21497006 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21497006 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18830802 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18830802 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60196 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60196 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15349 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15349 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40329225 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40329225 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40389446 # number of overall hits -system.cpu.dcache.overall_hits::total 40389446 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 556041 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 556041 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1019122 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1019122 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68628 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68628 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 580 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 580 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1575163 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1575163 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1643791 # number of overall misses -system.cpu.dcache.overall_misses::total 1643791 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8960046000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8960046000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14598887903 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14598887903 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5237000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5237000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23558933903 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23558933903 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23558933903 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23558933903 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22054487 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22054487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40327808 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40327808 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40388004 # number of overall hits +system.cpu.dcache.overall_hits::total 40388004 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 555640 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 555640 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1019099 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1019099 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68639 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68639 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 577 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 577 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1574739 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1574739 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1643378 # number of overall misses +system.cpu.dcache.overall_misses::total 1643378 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9002363000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9002363000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14580629410 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14580629410 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5329000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5329000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23582992410 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23582992410 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23582992410 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23582992410 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22052646 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22052646 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128849 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128849 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128835 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128835 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41904388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41904388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42033237 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42033237 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025212 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025212 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051341 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051341 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532623 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532623 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036418 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036418 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037589 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037589 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039107 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039107 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16114.002385 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16114.002385 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14324.965905 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14324.965905 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9029.310345 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9029.310345 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14956.505392 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14956.505392 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14332.073787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14332.073787 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 55 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3099418 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41902547 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41902547 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42031382 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42031382 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025196 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025196 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051340 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051340 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532767 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532767 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036230 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036230 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037581 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037581 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039099 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039099 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16201.790728 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16201.790728 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14307.372895 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14307.372895 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9235.701906 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9235.701906 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14975.810220 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14975.810220 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14350.315271 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14350.315271 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3096615 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 130265 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.166667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23.793175 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 130248 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.833333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 23.774760 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 261117 # number of writebacks -system.cpu.dcache.writebacks::total 261117 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 256598 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 256598 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870592 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 870592 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 580 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 580 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1127190 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1127190 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1127190 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1127190 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299443 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299443 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148530 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2013580000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2013580000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5545966465 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5545966465 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7559546465 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7559546465 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013577 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013577 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # 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number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3220458500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3220458500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2349684961 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2349684961 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2014368500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2014368500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5570143461 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5570143461 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7584511961 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7584511961 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013578 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013578 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291807 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291807 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010690 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.010690 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011552 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.011552 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10664.154781 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10664.154781 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15839.628122 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15839.628122 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53556.932734 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53556.932734 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12380.135555 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12380.135555 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15568.396863 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15568.396863 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10755.512250 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10755.512250 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15820.770144 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15820.770144 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53580.755420 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53580.755420 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12434.938064 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12434.938064 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15620.841131 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15620.841131 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # 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Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 323114 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 69.416150 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1108313500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.289801 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996660 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996660 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 353 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 350 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45857337 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45857337 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22432857 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22432857 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22432857 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22432857 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22432857 # number of overall hits -system.cpu.icache.overall_hits::total 22432857 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 334131 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 334131 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 334131 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 334131 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 334131 # number of overall misses -system.cpu.icache.overall_misses::total 334131 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3372669901 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3372669901 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3372669901 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3372669901 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3372669901 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3372669901 # 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number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22763216 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22763216 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22763216 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014668 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014668 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014668 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014668 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014668 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014668 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10145.567343 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10145.567343 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10145.567343 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10145.567343 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10145.567343 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10145.567343 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 275055 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 50 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16465 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.705436 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 10770 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 10770 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 10770 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 10770 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 10770 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 10770 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323361 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 323361 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 323361 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 323361 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 323361 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 323361 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3089767447 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 3089767447 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3089767447 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 3089767447 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3089767447 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 3089767447 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014203 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014203 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014203 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014203 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014203 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014203 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9555.164188 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9555.164188 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9555.164188 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 9555.164188 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9555.164188 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 9555.164188 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 10762 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 10762 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 10762 # 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number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10622734578 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 104000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 104000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 672201000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 672201000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 652903000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 652903000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2499575500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2499575500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 652903000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3171776500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3824679500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 652903000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3171776500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10622734578 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14447414078 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.545455 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.545455 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056446 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056446 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.028576 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.028576 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.092014 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.092014 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028576 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.081131 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060123 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028576 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.081131 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056032 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056032 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.028133 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.028133 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.092103 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.092103 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028133 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.081066 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059915 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028133 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.081066 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.199213 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94583.344449 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 94583.344449 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16750 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16750 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80819.341760 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80819.341760 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71844.480519 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71844.480519 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80457.656089 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80457.656089 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71844.480519 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80534.649947 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78883.599951 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71844.480519 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80534.649947 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94583.344449 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89845.089386 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.198976 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94466.292379 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 94466.292379 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17333.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17333.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80754.565113 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80754.565113 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71826.512651 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71826.512651 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80537.939812 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80537.939812 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71826.512651 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80583.752541 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78940.753354 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71826.512651 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80583.752541 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94466.292379 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89791.262138 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 660352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 358995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 498597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 141207 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148568 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148568 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 323361 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336991 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 938997 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406890 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2345887 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20694144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47787264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 68481408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 270774 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1887575 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.143443 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.350524 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 1616280 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 807659 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 20376 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 20194 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 182 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 660093 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 351517 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 505600 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 141126 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148559 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148559 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 323124 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336969 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 938319 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406791 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2345110 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20679232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47313728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 67992960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 270457 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1886726 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.095537 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.294284 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1616816 85.66% 85.66% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 270759 14.34% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1706655 90.46% 90.46% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 179889 9.53% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 182 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1887575 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1069525000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1886726 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1061889000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485192198 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 485111148 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728416355 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 728499095 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 137050 # Transaction distribution -system.membus.trans_dist::Writeback 97878 # Transaction distribution -system.membus.trans_dist::CleanEvict 30539 # Transaction distribution +system.membus.trans_dist::ReadResp 136869 # Transaction distribution +system.membus.trans_dist::Writeback 97768 # Transaction distribution +system.membus.trans_dist::CleanEvict 30364 # Transaction distribution system.membus.trans_dist::UpgradeReq 6 # Transaction distribution system.membus.trans_dist::UpgradeResp 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 8386 # Transaction distribution -system.membus.trans_dist::ReadExResp 8386 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 137050 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 419301 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 419301 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15572096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15572096 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 8324 # Transaction distribution +system.membus.trans_dist::ReadExResp 8324 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 136869 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 418530 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 418530 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15549504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15549504 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 273859 # Request fanout histogram +system.membus.snoop_fanout::samples 273331 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 273859 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 273331 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 273859 # Request fanout histogram -system.membus.reqLayer0.occupancy 740935905 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 273331 # Request fanout histogram +system.membus.reqLayer0.occupancy 739892708 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 757820949 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 756443702 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 46df80677..617d9f369 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.208801 # Nu sim_ticks 1208800797500 # Number of ticks simulated final_tick 1208800797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239332 # Simulator instruction rate (inst/s) -host_op_rate 239332 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158403619 # Simulator tick rate (ticks/s) -host_mem_usage 291552 # Number of bytes of host memory used -host_seconds 7631.14 # Real time elapsed on the host +host_inst_rate 309355 # Simulator instruction rate (inst/s) +host_op_rate 309355 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 204748768 # Simulator tick rate (ticks/s) +host_mem_usage 299532 # Number of bytes of host memory used +host_seconds 5903.82 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -703,6 +703,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68146.812957 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77658.597897 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77653.938429 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 18249028 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121989 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1267 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1267 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7239716 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 4708732 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6334139 # Transaction distribution @@ -718,15 +724,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 820072320 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1920882 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 20169910 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.095235 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.293539 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000063 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.007925 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18249028 90.48% 90.48% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1920882 9.52% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 20168643 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1267 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 20169910 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12811105000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index cb7ba764c..bb4922b1c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.669557 # Nu sim_ticks 669556582000 # Number of ticks simulated final_tick 669556582000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125035 # Simulator instruction rate (inst/s) -host_op_rate 125035 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48223337 # Simulator tick rate (ticks/s) -host_mem_usage 292576 # Number of bytes of host memory used -host_seconds 13884.49 # Real time elapsed on the host +host_inst_rate 160543 # Simulator instruction rate (inst/s) +host_op_rate 160543 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61918292 # Simulator tick rate (ticks/s) +host_mem_usage 299292 # Number of bytes of host memory used +host_seconds 10813.55 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1026,6 +1026,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72271.293375 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79676.114069 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79672.524401 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 18419494 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207224 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1279 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7333064 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 4752054 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6384201 # Transaction distribution @@ -1041,15 +1047,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 828161152 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1929031 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 20348525 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.094800 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.292938 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000063 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.007928 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18419494 90.52% 90.52% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1929031 9.48% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 20347246 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1279 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 20348525 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12937495000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 018ebe8b0..d971ffdfc 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.623057 # Nu sim_ticks 2623057163500 # Number of ticks simulated final_tick 2623057163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1251674 # Simulator instruction rate (inst/s) -host_op_rate 1251674 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1804181213 # Simulator tick rate (ticks/s) -host_mem_usage 294596 # Number of bytes of host memory used -host_seconds 1453.88 # Real time elapsed on the host +host_inst_rate 1405944 # Simulator instruction rate (inst/s) +host_op_rate 1405944 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2026548224 # Simulator tick rate (ticks/s) +host_mem_usage 297224 # Number of bytes of host memory used +host_seconds 1294.35 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -478,6 +478,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42556.733167 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42505.042430 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.063665 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 4701388 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6325775 # Transaction distribution @@ -493,15 +499,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 818685568 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1919524 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 20139699 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.095310 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.293643 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000056 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.007464 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18220175 90.47% 90.47% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1919524 9.53% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 20138577 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1122 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 20139699 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12789513500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index bd1131ae5..766f60b6c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.116876 # Number of seconds simulated -sim_ticks 1116876142500 # Number of ticks simulated -final_tick 1116876142500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.116866 # Number of seconds simulated +sim_ticks 1116865669500 # Number of ticks simulated +final_tick 1116865669500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161785 # Simulator instruction rate (inst/s) -host_op_rate 174299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116987267 # Simulator tick rate (ticks/s) -host_mem_usage 309392 # Number of bytes of host memory used -host_seconds 9546.99 # Real time elapsed on the host +host_inst_rate 226280 # Simulator instruction rate (inst/s) +host_op_rate 243783 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 163622006 # Simulator tick rate (ticks/s) +host_mem_usage 317884 # Number of bytes of host memory used +host_seconds 6825.89 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 50368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 130931520 # Number of bytes read from this memory -system.physmem.bytes_read::total 130981888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130931456 # Number of bytes read from this memory +system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67207936 # Number of bytes written to this memory -system.physmem.bytes_written::total 67207936 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory +system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 787 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2045805 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2046592 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050124 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050124 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 45097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117230116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 117275213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 45097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 45097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 60174923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 60174923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 60174923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 45097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117230116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 177450137 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2046592 # Number of read requests accepted -system.physmem.writeReqs 1050124 # Number of write requests accepted -system.physmem.readBursts 2046592 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1050124 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 130897216 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 84672 # Total number of bytes read from write queue -system.physmem.bytesWritten 67206464 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130981888 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67207936 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1323 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 2045804 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2046591 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050123 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050123 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 45098 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117231158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 117276256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 45098 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 45098 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 60175430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 60175430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 60175430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 45098 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117231158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 177451686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2046591 # Number of read requests accepted +system.physmem.writeReqs 1050123 # Number of write requests accepted +system.physmem.readBursts 2046591 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1050123 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 130897024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 84800 # Total number of bytes read from write queue +system.physmem.bytesWritten 67206400 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130981824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1325 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127284 # Per bank write bursts -system.physmem.perBankRdBursts::1 124662 # Per bank write bursts -system.physmem.perBankRdBursts::2 121597 # Per bank write bursts +system.physmem.perBankRdBursts::0 127282 # Per bank write bursts +system.physmem.perBankRdBursts::1 124660 # Per bank write bursts +system.physmem.perBankRdBursts::2 121599 # Per bank write bursts system.physmem.perBankRdBursts::3 123658 # Per bank write bursts -system.physmem.perBankRdBursts::4 122617 # Per bank write bursts +system.physmem.perBankRdBursts::4 122616 # Per bank write bursts system.physmem.perBankRdBursts::5 122675 # Per bank write bursts system.physmem.perBankRdBursts::6 123246 # Per bank write bursts -system.physmem.perBankRdBursts::7 123759 # Per bank write bursts +system.physmem.perBankRdBursts::7 123764 # Per bank write bursts system.physmem.perBankRdBursts::8 131397 # Per bank write bursts -system.physmem.perBankRdBursts::9 133511 # Per bank write bursts -system.physmem.perBankRdBursts::10 132080 # Per bank write bursts -system.physmem.perBankRdBursts::11 133309 # Per bank write bursts -system.physmem.perBankRdBursts::12 133252 # Per bank write bursts -system.physmem.perBankRdBursts::13 133368 # Per bank write bursts -system.physmem.perBankRdBursts::14 129308 # Per bank write bursts -system.physmem.perBankRdBursts::15 129546 # Per bank write bursts +system.physmem.perBankRdBursts::9 133514 # Per bank write bursts +system.physmem.perBankRdBursts::10 132084 # Per bank write bursts +system.physmem.perBankRdBursts::11 133304 # Per bank write bursts +system.physmem.perBankRdBursts::12 133248 # Per bank write bursts +system.physmem.perBankRdBursts::13 133365 # Per bank write bursts +system.physmem.perBankRdBursts::14 129309 # Per bank write bursts +system.physmem.perBankRdBursts::15 129545 # Per bank write bursts system.physmem.perBankWrBursts::0 66136 # Per bank write bursts system.physmem.perBankWrBursts::1 64410 # Per bank write bursts system.physmem.perBankWrBursts::2 62576 # Per bank write bursts @@ -71,34 +71,34 @@ system.physmem.perBankWrBursts::3 63006 # Pe system.physmem.perBankWrBursts::4 63000 # Per bank write bursts system.physmem.perBankWrBursts::5 63100 # Per bank write bursts system.physmem.perBankWrBursts::6 64443 # Per bank write bursts -system.physmem.perBankWrBursts::7 65435 # Per bank write bursts -system.physmem.perBankWrBursts::8 67311 # Per bank write bursts -system.physmem.perBankWrBursts::9 67795 # Per bank write bursts -system.physmem.perBankWrBursts::10 67548 # Per bank write bursts -system.physmem.perBankWrBursts::11 67883 # Per bank write bursts -system.physmem.perBankWrBursts::12 67328 # Per bank write bursts +system.physmem.perBankWrBursts::7 65436 # Per bank write bursts +system.physmem.perBankWrBursts::8 67310 # Per bank write bursts +system.physmem.perBankWrBursts::9 67797 # Per bank write bursts +system.physmem.perBankWrBursts::10 67549 # Per bank write bursts +system.physmem.perBankWrBursts::11 67882 # Per bank write bursts +system.physmem.perBankWrBursts::12 67326 # Per bank write bursts system.physmem.perBankWrBursts::13 67793 # Per bank write bursts -system.physmem.perBankWrBursts::14 66483 # Per bank write bursts +system.physmem.perBankWrBursts::14 66482 # Per bank write bursts system.physmem.perBankWrBursts::15 65854 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1116876049000 # Total gap between requests +system.physmem.totGap 1116865575000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2046592 # Read request sizes (log2) +system.physmem.readPktSize::6 2046591 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1050124 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1916546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128705 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1050123 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1916631 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 128617 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 34054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 34018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 78 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see @@ -193,24 +193,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1910492 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.692259 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.833601 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.494474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1485528 77.76% 77.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305524 15.99% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52470 2.75% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20903 1.09% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13406 0.70% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7575 0.40% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5481 0.29% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5100 0.27% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 14505 0.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1910492 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61132 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.413630 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 160.636391 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61087 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1910448 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.693777 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.830782 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.503425 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1485607 77.76% 77.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305343 15.98% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52494 2.75% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20883 1.09% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13429 0.70% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7609 0.40% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5497 0.29% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5095 0.27% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14491 0.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1910448 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61128 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.415767 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 160.633753 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 61083 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 20 0.03% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes @@ -220,76 +220,76 @@ system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61132 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61132 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.177599 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.142637 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.096979 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 26963 44.11% 44.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1122 1.84% 45.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28754 47.04% 92.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3885 6.36% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 352 0.58% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 46 0.08% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 61128 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61128 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.178707 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.143614 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.099153 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 26983 44.14% 44.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1095 1.79% 45.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28688 46.93% 92.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3942 6.45% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 361 0.59% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 49 0.08% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 8 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61132 # Writes before turning the bus around for reads -system.physmem.totQLat 38139021250 # Total ticks spent queuing -system.physmem.totMemAccLat 76487815000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10226345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18647.44 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 61128 # Writes before turning the bus around for reads +system.physmem.totQLat 38113681000 # Total ticks spent queuing +system.physmem.totMemAccLat 76462418500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10226330000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18635.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37397.44 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 37385.07 # Average memory access latency per DRAM burst system.physmem.avgRdBW 117.20 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 60.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 117.28 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 60.17 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 60.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.39 # Data bus utilization in percentage system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing -system.physmem.readRowHits 773003 # Number of row buffer hits during reads -system.physmem.writeRowHits 411872 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.79 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.22 # Row buffer hit rate for writes -system.physmem.avgGap 360664.67 # Average gap between requests +system.physmem.readRowHits 773150 # Number of row buffer hits during reads +system.physmem.writeRowHits 411758 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.80 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.21 # Row buffer hit rate for writes +system.physmem.avgGap 360661.52 # Average gap between requests system.physmem.pageHitRate 38.28 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7041119400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3841880625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7718053200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3318446880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 72948863520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 420554384415 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 301217964750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 816640712790 # Total energy per rank (pJ) -system.physmem_0.averagePower 731.183278 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 498392390000 # Time in different power states -system.physmem_0.memoryStateTime::REF 37294920000 # Time in different power states +system.physmem_0.actEnergy 7040439000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3841509375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7717788000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3318453360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 420410239110 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 301335056250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 816611331495 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.167175 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 498591665750 # Time in different power states +system.physmem_0.memoryStateTime::REF 37294400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 581188236250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 580976292250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7402200120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4038898875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8234990400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3486207600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 72948863520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 429475728015 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 293392224750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 818979113280 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.276976 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 485326311500 # Time in different power states -system.physmem_1.memoryStateTime::REF 37294920000 # Time in different power states +system.physmem_1.actEnergy 7402532760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4039080375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8234920200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3486194640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 429557025690 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 293311559250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 818979159315 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.287251 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 485194866750 # Time in different power states +system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 594254742500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 594372992750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 239639069 # Number of BP lookups -system.cpu.branchPred.condPredicted 186342280 # Number of conditional branches predicted +system.cpu.branchPred.lookups 239639075 # Number of BP lookups +system.cpu.branchPred.condPredicted 186342287 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14526140 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 130646098 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122079384 # Number of BTB hits +system.cpu.branchPred.BTBLookups 130646101 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122079387 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 93.442809 # BTB Hit Percentage system.cpu.branchPred.usedRAS 15657029 # Number of times the RAS was used to get a target. @@ -412,68 +412,68 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2233752285 # number of cpu cycles simulated +system.cpu.numCycles 2233731339 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41470092 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41470082 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.446203 # CPI: cycles per instruction -system.cpu.ipc 0.691466 # IPC: instructions per cycle -system.cpu.tickCycles 1834122948 # Number of cycles that the object actually ticked -system.cpu.idleCycles 399629337 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.446190 # CPI: cycles per instruction +system.cpu.ipc 0.691472 # IPC: instructions per cycle +system.cpu.tickCycles 1834124286 # Number of cycles that the object actually ticked +system.cpu.idleCycles 399607053 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 9221039 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.616333 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624218905 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4085.616235 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624218894 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9225135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.665016 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.665015 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616333 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616235 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 245 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 253 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1229 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276841915 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276841915 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 453887721 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453887721 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170331061 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170331061 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1276841917 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276841917 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 453887722 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453887722 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170331049 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170331049 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624218782 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624218782 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624218783 # number of overall hits -system.cpu.dcache.overall_hits::total 624218783 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 624218771 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624218771 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624218772 # number of overall hits +system.cpu.dcache.overall_hits::total 624218772 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7334497 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7334497 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2254986 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2254986 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2254998 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2254998 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9589483 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9589483 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9589485 # number of overall misses -system.cpu.dcache.overall_misses::total 9589485 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 190949826000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 190949826000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 109060330000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 109060330000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 300010156000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 300010156000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 300010156000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 300010156000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461222218 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461222218 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9589495 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9589495 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9589497 # number of overall misses +system.cpu.dcache.overall_misses::total 9589497 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 190935436500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 190935436500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 109060065500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 109060065500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 299995502000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 299995502000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 299995502000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 299995502000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461222219 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461222219 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -482,10 +482,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 633808265 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633808265 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 633808268 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633808268 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 633808266 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633808266 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633808269 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633808269 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015902 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015902 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses @@ -496,14 +496,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26034.481438 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26034.481438 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48364.082970 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48364.082970 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31285.331649 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31285.331649 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.325124 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31285.325124 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26032.519544 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26032.519544 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48363.708305 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48363.708305 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31283.764369 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31283.764369 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31283.757845 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31283.757845 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -516,12 +516,12 @@ system.cpu.dcache.writebacks::writebacks 3684564 # nu system.cpu.dcache.writebacks::total 3684564 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364134 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 364134 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 364349 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 364349 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 364349 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 364349 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364146 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 364146 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 364361 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 364361 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 364361 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 364361 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334282 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7334282 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890852 # number of WriteReq MSHR misses @@ -532,16 +532,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9225134 system.cpu.dcache.demand_mshr_misses::total 9225134 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9225135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9225135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183609818500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 183609818500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84766639000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84766639000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183595384500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 183595384500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84757207500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84757207500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268376457500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 268376457500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268376531500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 268376531500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268352592000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 268352592000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268352666000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 268352666000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015902 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -552,24 +552,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014555 system.cpu.dcache.demand_mshr_miss_rate::total 0.014555 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014555 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25034.463973 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25034.463973 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44829.864527 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44829.864527 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25032.495955 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25032.495955 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44824.876564 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44824.876564 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29091.876335 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29091.876335 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29091.881203 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29091.881203 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29089.289326 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29089.289326 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29089.294195 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29089.294195 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.tagsinuse 661.386126 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 465281345 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 661.385274 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 465281545 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 567416.274390 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 567416.518293 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 661.386126 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 661.385274 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.322942 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.322942 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id @@ -577,44 +577,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 32 system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 930565150 # Number of tag accesses -system.cpu.icache.tags.data_accesses 930565150 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 465281345 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 465281345 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 465281345 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 465281345 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 465281345 # number of overall hits -system.cpu.icache.overall_hits::total 465281345 # number of overall hits +system.cpu.icache.tags.tag_accesses 930565550 # Number of tag accesses +system.cpu.icache.tags.data_accesses 930565550 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 465281545 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 465281545 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 465281545 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 465281545 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 465281545 # number of overall hits +system.cpu.icache.overall_hits::total 465281545 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses system.cpu.icache.overall_misses::total 820 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62363500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62363500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62363500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62363500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62363500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62363500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 465282165 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 465282165 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 465282165 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 465282165 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 465282165 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 465282165 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62174000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62174000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62174000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62174000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62174000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62174000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 465282365 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 465282365 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 465282365 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 465282365 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 465282365 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 465282365 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76053.048780 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76053.048780 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76053.048780 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76053.048780 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76053.048780 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76053.048780 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75821.951220 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75821.951220 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75821.951220 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75821.951220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75821.951220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75821.951220 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -629,35 +629,35 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 820 system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61543500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 61543500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61543500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 61543500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61543500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 61543500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61354000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 61354000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61354000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 61354000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61354000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 61354000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75053.048780 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75053.048780 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75053.048780 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75053.048780 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75053.048780 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75053.048780 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74821.951220 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74821.951220 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74821.951220 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74821.951220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74821.951220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74821.951220 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2013891 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31258.308104 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14509189 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2043666 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.099589 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 2013890 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31258.297879 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14509190 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2043665 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.099593 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14832.412998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.588444 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.306662 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.452649 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 14832.420356 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.588666 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.288857 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.452650 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000811 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.500467 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.953928 # Average percentage of cache occupancy @@ -668,46 +668,46 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1247 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15557 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 151497950 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 151497950 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 151497949 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 151497949 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 3684564 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 3684564 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1089696 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1089696 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1089697 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1089697 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 32 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 32 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089630 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 6089630 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7179326 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7179358 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7179327 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7179359 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7179326 # number of overall hits -system.cpu.l2cache.overall_hits::total 7179358 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 801156 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 801156 # number of ReadExReq misses +system.cpu.l2cache.overall_hits::cpu.data 7179327 # number of overall hits +system.cpu.l2cache.overall_hits::total 7179359 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 801155 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 801155 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 788 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 788 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1244653 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 1244653 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 788 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2045809 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2046597 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2045808 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2046596 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 788 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2045809 # number of overall misses -system.cpu.l2cache.overall_misses::total 2046597 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70430633500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 70430633500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59976000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 59976000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108661637000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 108661637000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 59976000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 179092270500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 179152246500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 59976000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 179092270500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 179152246500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 2045808 # number of overall misses +system.cpu.l2cache.overall_misses::total 2046596 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70421216500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 70421216500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59756500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 59756500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108645799000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 108645799000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 59756500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 179067015500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 179126772000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 59756500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 179067015500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 179126772000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 3684564 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 3684564 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890852 # number of ReadExReq accesses(hits+misses) @@ -734,18 +734,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.221830 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960976 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.221765 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.221830 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87911.260104 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87911.260104 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76111.675127 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76111.675127 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87302.755869 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87302.755869 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76111.675127 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87541.051242 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 87536.650596 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76111.675127 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87541.051242 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 87536.650596 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87899.615555 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87899.615555 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75833.121827 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75833.121827 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87290.031037 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87290.031037 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75833.121827 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87528.749277 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87524.246114 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75833.121827 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87528.749277 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87524.246114 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -754,8 +754,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1050124 # number of writebacks -system.cpu.l2cache.writebacks::total 1050124 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1050123 # number of writebacks +system.cpu.l2cache.writebacks::total 1050123 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4 # number of ReadSharedReq MSHR hits @@ -768,30 +768,30 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 4 system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 243 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 243 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801156 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 801156 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801155 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 801155 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 787 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 787 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1244649 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1244649 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2045805 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2046592 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2045804 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2046591 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2045805 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2046592 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62419073500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62419073500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52090500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52090500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96214883500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96214883500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52090500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158633957000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 158686047500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52090500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158633957000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 158686047500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 2045804 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2046591 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62409666500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62409666500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 51871000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 51871000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96199045500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96199045500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51871000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158608712000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158660583000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51871000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158608712000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158660583000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423701 # mshr miss rate for ReadExReq accesses @@ -806,21 +806,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.221830 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221764 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.221830 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77911.260104 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77911.260104 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66188.691233 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66188.691233 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77302.824732 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77302.824732 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66188.691233 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77541.093604 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77536.728131 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66188.691233 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77541.093604 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77536.728131 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77899.615555 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77899.615555 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65909.783990 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65909.783990 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77290.099859 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77290.099859 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65909.783990 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77528.791614 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77524.323619 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65909.783990 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77528.791614 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77524.323619 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 18447023 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221080 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1287 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1281 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4734688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4734687 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6498677 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1890852 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1890852 # Transaction distribution @@ -832,18 +838,18 @@ system.cpu.toL2Bus.pkt_count::total 27671384 # Pa system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826220736 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 826273216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2013891 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20460914 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.098426 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.297890 # Request fanout histogram +system.cpu.toL2Bus.snoops 2013890 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 20460913 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000220 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.014837 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18447023 90.16% 90.16% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2013891 9.84% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 20456426 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4481 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20460914 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 20460913 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12908075500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1230499 # Layer occupancy (ticks) @@ -851,29 +857,29 @@ system.cpu.toL2Bus.respLayer0.utilization 0.0 # L system.cpu.toL2Bus.respLayer1.occupancy 13837704496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.membus.trans_dist::ReadResp 1245436 # Transaction distribution -system.membus.trans_dist::Writeback 1050124 # Transaction distribution +system.membus.trans_dist::Writeback 1050123 # Transaction distribution system.membus.trans_dist::CleanEvict 962723 # Transaction distribution -system.membus.trans_dist::ReadExReq 801156 # Transaction distribution -system.membus.trans_dist::ReadExResp 801156 # Transaction distribution +system.membus.trans_dist::ReadExReq 801155 # Transaction distribution +system.membus.trans_dist::ReadExResp 801155 # Transaction distribution system.membus.trans_dist::ReadSharedReq 1245436 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106031 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6106031 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198189824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106028 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6106028 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198189696 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4059439 # Request fanout histogram +system.membus.snoop_fanout::samples 4059437 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4059439 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4059437 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4059439 # Request fanout histogram -system.membus.reqLayer0.occupancy 8663029500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4059437 # Request fanout histogram +system.membus.reqLayer0.occupancy 8662977500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11191724000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11191643250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index d6d64bb1d..09d71d56d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.770368 # Number of seconds simulated -sim_ticks 770368138000 # Number of ticks simulated -final_tick 770368138000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.770336 # Number of seconds simulated +sim_ticks 770336310500 # Number of ticks simulated +final_tick 770336310500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139680 # Simulator instruction rate (inst/s) -host_op_rate 150484 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69667014 # Simulator tick rate (ticks/s) -host_mem_usage 312136 # Number of bytes of host memory used -host_seconds 11057.86 # Real time elapsed on the host +host_inst_rate 130811 # Simulator instruction rate (inst/s) +host_op_rate 140929 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65240720 # Simulator tick rate (ticks/s) +host_mem_usage 314688 # Number of bytes of host memory used +host_seconds 11807.60 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 65792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 238160448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63905024 # Number of bytes read from this memory -system.physmem.bytes_read::total 302131264 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104870272 # Number of bytes written to this memory -system.physmem.bytes_written::total 104870272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1028 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3721257 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 998516 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4720801 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1638598 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1638598 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 85403 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309151477 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 82953877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 392190758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 85403 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 85403 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136130074 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136130074 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136130074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 85403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309151477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 82953877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 528320833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4720801 # Number of read requests accepted -system.physmem.writeReqs 1638598 # Number of write requests accepted -system.physmem.readBursts 4720801 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1638598 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 301683008 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448256 # Total number of bytes read from write queue -system.physmem.bytesWritten 104867648 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 302131264 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104870272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7004 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 12 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 66496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 238054976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63977600 # Number of bytes read from this memory +system.physmem.bytes_read::total 302099072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 66496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 66496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104804160 # Number of bytes written to this memory +system.physmem.bytes_written::total 104804160 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1039 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3719609 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 999650 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4720298 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1637565 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1637565 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 86321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309027334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 83051518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 392165172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 86321 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86321 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136049877 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136049877 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136049877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 86321 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309027334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 83051518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 528215049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4720298 # Number of read requests accepted +system.physmem.writeReqs 1637565 # Number of write requests accepted +system.physmem.readBursts 4720298 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1637565 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 301639360 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 459712 # Total number of bytes read from write queue +system.physmem.bytesWritten 104801536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 302099072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104804160 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7183 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 296472 # Per bank write bursts -system.physmem.perBankRdBursts::1 294660 # Per bank write bursts -system.physmem.perBankRdBursts::2 288575 # Per bank write bursts -system.physmem.perBankRdBursts::3 292960 # Per bank write bursts -system.physmem.perBankRdBursts::4 290749 # Per bank write bursts -system.physmem.perBankRdBursts::5 289530 # Per bank write bursts -system.physmem.perBankRdBursts::6 284828 # Per bank write bursts -system.physmem.perBankRdBursts::7 280913 # Per bank write bursts -system.physmem.perBankRdBursts::8 297084 # Per bank write bursts -system.physmem.perBankRdBursts::9 304004 # Per bank write bursts -system.physmem.perBankRdBursts::10 295272 # Per bank write bursts -system.physmem.perBankRdBursts::11 301446 # Per bank write bursts -system.physmem.perBankRdBursts::12 303554 # Per bank write bursts -system.physmem.perBankRdBursts::13 302544 # Per bank write bursts -system.physmem.perBankRdBursts::14 297853 # Per bank write bursts -system.physmem.perBankRdBursts::15 293353 # Per bank write bursts -system.physmem.perBankWrBursts::0 103842 # Per bank write bursts -system.physmem.perBankWrBursts::1 101847 # Per bank write bursts -system.physmem.perBankWrBursts::2 99335 # Per bank write bursts -system.physmem.perBankWrBursts::3 100097 # Per bank write bursts -system.physmem.perBankWrBursts::4 99287 # Per bank write bursts -system.physmem.perBankWrBursts::5 99035 # Per bank write bursts -system.physmem.perBankWrBursts::6 102669 # Per bank write bursts -system.physmem.perBankWrBursts::7 104576 # Per bank write bursts -system.physmem.perBankWrBursts::8 105230 # Per bank write bursts -system.physmem.perBankWrBursts::9 104522 # Per bank write bursts -system.physmem.perBankWrBursts::10 102176 # Per bank write bursts -system.physmem.perBankWrBursts::11 103126 # Per bank write bursts -system.physmem.perBankWrBursts::12 103102 # Per bank write bursts -system.physmem.perBankWrBursts::13 102725 # Per bank write bursts -system.physmem.perBankWrBursts::14 104361 # Per bank write bursts -system.physmem.perBankWrBursts::15 102627 # Per bank write bursts +system.physmem.perBankRdBursts::0 296850 # Per bank write bursts +system.physmem.perBankRdBursts::1 294498 # Per bank write bursts +system.physmem.perBankRdBursts::2 288916 # Per bank write bursts +system.physmem.perBankRdBursts::3 292682 # Per bank write bursts +system.physmem.perBankRdBursts::4 290729 # Per bank write bursts +system.physmem.perBankRdBursts::5 289596 # Per bank write bursts +system.physmem.perBankRdBursts::6 284483 # Per bank write bursts +system.physmem.perBankRdBursts::7 281209 # Per bank write bursts +system.physmem.perBankRdBursts::8 297427 # Per bank write bursts +system.physmem.perBankRdBursts::9 303552 # Per bank write bursts +system.physmem.perBankRdBursts::10 295336 # Per bank write bursts +system.physmem.perBankRdBursts::11 302232 # Per bank write bursts +system.physmem.perBankRdBursts::12 303231 # Per bank write bursts +system.physmem.perBankRdBursts::13 302345 # Per bank write bursts +system.physmem.perBankRdBursts::14 297342 # Per bank write bursts +system.physmem.perBankRdBursts::15 292687 # Per bank write bursts +system.physmem.perBankWrBursts::0 104014 # Per bank write bursts +system.physmem.perBankWrBursts::1 101992 # Per bank write bursts +system.physmem.perBankWrBursts::2 99263 # Per bank write bursts +system.physmem.perBankWrBursts::3 99947 # Per bank write bursts +system.physmem.perBankWrBursts::4 99433 # Per bank write bursts +system.physmem.perBankWrBursts::5 98879 # Per bank write bursts +system.physmem.perBankWrBursts::6 102579 # Per bank write bursts +system.physmem.perBankWrBursts::7 104318 # Per bank write bursts +system.physmem.perBankWrBursts::8 105363 # Per bank write bursts +system.physmem.perBankWrBursts::9 104471 # Per bank write bursts +system.physmem.perBankWrBursts::10 102169 # Per bank write bursts +system.physmem.perBankWrBursts::11 102930 # Per bank write bursts +system.physmem.perBankWrBursts::12 102920 # Per bank write bursts +system.physmem.perBankWrBursts::13 102581 # Per bank write bursts +system.physmem.perBankWrBursts::14 104115 # Per bank write bursts +system.physmem.perBankWrBursts::15 102550 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 770367991500 # Total gap between requests +system.physmem.totGap 770336158500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4720801 # Read request sizes (log2) +system.physmem.readPktSize::6 4720298 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1638598 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2785137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1045602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 327608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 232677 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 151173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 83865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 38451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23803 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18009 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 821 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1637565 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2783946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1045590 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 328353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 232144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 151285 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 83614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 38578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23869 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1738 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 814 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 23398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 25057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 60199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 75747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 106151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 106693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 111353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 114123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 105280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 101866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 23160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 60100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 75642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 99663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 106074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 106708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 111119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 114322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 105421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 102034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -197,115 +197,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4291005 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.744514 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.906714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 101.391830 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3416666 79.62% 79.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 676199 15.76% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96816 2.26% 97.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35217 0.82% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22960 0.54% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11971 0.28% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7013 0.16% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5097 0.12% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19066 0.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4291005 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 98697 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.759952 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 32.369236 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 98.446894 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 96231 97.50% 97.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1192 1.21% 98.71% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 746 0.76% 99.47% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 392 0.40% 99.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 102 0.10% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 22 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2559 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 4289513 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.751761 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.903148 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 101.431882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3416049 79.64% 79.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 675171 15.74% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 96645 2.25% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35451 0.83% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 23003 0.54% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12074 0.28% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6995 0.16% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5025 0.12% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19100 0.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4289513 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 98662 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.769871 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 32.372187 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 98.540692 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 96215 97.52% 97.52% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1195 1.21% 98.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 729 0.74% 99.47% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 403 0.41% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 87 0.09% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-2047 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2304-2559 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2815 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-3327 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-3839 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 98697 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 98697 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.601893 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.567781 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.107607 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 72640 73.60% 73.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1756 1.78% 75.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18593 18.84% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3904 3.96% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1031 1.04% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 392 0.40% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 184 0.19% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 91 0.09% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 55 0.06% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 31 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 17 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::3584-3839 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-5375 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 98662 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 98662 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.597312 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.563431 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.103098 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 72815 73.80% 73.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1780 1.80% 75.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18354 18.60% 94.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3927 3.98% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 986 1.00% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 404 0.41% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 201 0.20% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 116 0.12% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 44 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 22 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 12 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 98697 # Writes before turning the bus around for reads -system.physmem.totQLat 131099404549 # Total ticks spent queuing -system.physmem.totMemAccLat 219483098299 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23568985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27811.85 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 98662 # Writes before turning the bus around for reads +system.physmem.totQLat 131160021238 # Total ticks spent queuing +system.physmem.totMemAccLat 219530927488 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23565575000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27828.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46561.85 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 391.61 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 136.13 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 392.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 136.13 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46578.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 391.57 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 136.05 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 392.17 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 136.05 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.12 # Data bus utilization in percentage system.physmem.busUtilRead 3.06 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing -system.physmem.readRowHits 1707890 # Number of row buffer hits during reads -system.physmem.writeRowHits 353447 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.57 # Row buffer hit rate for writes -system.physmem.avgGap 121138.49 # Average gap between requests -system.physmem.pageHitRate 32.45 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 16077957840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8772695250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18085189200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5253161040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50316417840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 410294660580 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 102310835250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 611110917000 # Total energy per rank (pJ) -system.physmem_0.averagePower 793.275483 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 167665323859 # Time in different power states -system.physmem_0.memoryStateTime::REF 25724140000 # Time in different power states +system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing +system.physmem.readRowHits 1707273 # Number of row buffer hits during reads +system.physmem.writeRowHits 353841 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.22 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 21.61 # Row buffer hit rate for writes +system.physmem.avgGap 121162.75 # Average gap between requests +system.physmem.pageHitRate 32.46 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 16082924760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8775405375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18087474600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5251508640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50314383600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 409609386630 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 102893262750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 611014346355 # Total energy per rank (pJ) +system.physmem_0.averagePower 793.182199 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 168633417027 # Time in different power states +system.physmem_0.memoryStateTime::REF 25723100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 576975365641 # Time in different power states +system.physmem_0.memoryStateTime::ACT 575976400473 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16361828280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8927584875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18681803400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5364480960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50316417840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 411044339970 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 101653218750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 612349674075 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.883504 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 166565047661 # Time in different power states -system.physmem_1.memoryStateTime::REF 25724140000 # Time in different power states +system.physmem_1.actEnergy 16345687680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8918778000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18674323200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5359543200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50314383600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 410844304170 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 101810001750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 612267021600 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.808347 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 166829398639 # Time in different power states +system.physmem_1.memoryStateTime::REF 25723100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 578076556839 # Time in different power states +system.physmem_1.memoryStateTime::ACT 577780670361 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 286273758 # Number of BP lookups -system.cpu.branchPred.condPredicted 223402774 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14629982 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157694112 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150348271 # Number of BTB hits +system.cpu.branchPred.lookups 286278310 # Number of BP lookups +system.cpu.branchPred.condPredicted 223407435 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14630059 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158227088 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150348964 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.341715 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16640713 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.021002 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16641238 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -424,128 +424,128 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1540736277 # number of cpu cycles simulated +system.cpu.numCycles 1540672622 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13925194 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067435227 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286273758 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166988984 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1512088964 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29284609 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 664 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 1031 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656921798 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 960 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1540658157 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.437628 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228937 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13926355 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067514794 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286278310 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166990202 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1512022873 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29284737 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 188 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 1021 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656940964 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 966 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1540592805 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.437738 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228920 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 458280922 29.75% 29.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465413379 30.21% 59.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101412163 6.58% 66.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515551693 33.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 458181319 29.74% 29.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465421558 30.21% 59.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101422593 6.58% 66.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515567335 33.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1540658157 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185803 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.341849 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74641640 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 543291473 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849963258 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58120186 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14641600 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42202380 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 756 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037144212 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52474408 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14641600 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139712786 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 462567620 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14938 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837837029 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 85884184 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976322026 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26747258 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45146985 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 125259 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1471751 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25027790 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985779948 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9127891240 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432801848 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 139 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1540592805 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185814 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.341956 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74646858 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 543216907 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849967493 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58119883 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14641664 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42201795 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 757 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037179352 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52470113 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14641664 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139717275 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 462450514 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13916 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837848883 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 85920553 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976355004 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26745374 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45156757 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 125486 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1486003 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25049006 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985823032 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128033727 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432836892 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 151 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310881003 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 157 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 151 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111429534 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542545285 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199304809 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26862690 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28866621 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947900293 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 216 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857514523 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13512332 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283868093 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647012526 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1540658157 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.205663 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150942 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 310924087 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 156 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 148 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111428528 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542554069 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199305704 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26941972 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29270810 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947933260 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 215 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857474146 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13497185 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283901059 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647116126 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1540592805 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.205688 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150881 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 587771265 38.15% 38.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326011747 21.16% 59.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378176386 24.55% 83.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219651217 14.26% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29041357 1.88% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6185 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 587702275 38.15% 38.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 325996808 21.16% 59.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378232244 24.55% 83.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219639231 14.26% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29016078 1.88% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6169 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1540658157 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1540592805 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166072420 40.95% 40.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2002 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191493456 47.22% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47936528 11.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166081126 41.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1996 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191505284 47.27% 88.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47530605 11.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138226056 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 801017 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138242397 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 801060 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -567,90 +567,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 30 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 32 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532163815 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186323583 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532116023 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186314612 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857514523 # Type of FU issued -system.cpu.iq.rate 1.205602 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405504406 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218305 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5674703700 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2231781287 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805692489 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 241 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 242 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 71 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2263018794 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17823551 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857474146 # Type of FU issued +system.cpu.iq.rate 1.205625 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405119011 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218102 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5674157044 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2231847189 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805703414 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 266 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 72 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262593018 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 139 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17811740 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84238951 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66626 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13177 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24457764 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84247735 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66708 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13149 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24458659 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4548930 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4887285 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4504401 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4884981 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14641600 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25334604 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1297189 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947900591 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14641664 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25329983 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1325123 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947933556 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542545285 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199304809 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 154 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159299 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1136868 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13177 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7700706 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8703944 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16404650 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827845280 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516985272 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29669243 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542554069 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199305704 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 153 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159005 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1165002 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13149 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7699177 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8705456 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16404633 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827812064 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516937908 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29662082 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 82 # number of nop insts executed -system.cpu.iew.exec_refs 698740184 # number of memory reference insts executed -system.cpu.iew.exec_branches 229542491 # Number of branches executed -system.cpu.iew.exec_stores 181754912 # Number of stores executed -system.cpu.iew.exec_rate 1.186345 # Inst execution rate -system.cpu.iew.wb_sent 1808718850 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805692560 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169243952 # num instructions producing a value -system.cpu.iew.wb_consumers 1689620594 # num instructions consuming a value +system.cpu.iew.exec_nop 81 # number of nop insts executed +system.cpu.iew.exec_refs 698690935 # number of memory reference insts executed +system.cpu.iew.exec_branches 229542500 # Number of branches executed +system.cpu.iew.exec_stores 181753027 # Number of stores executed +system.cpu.iew.exec_rate 1.186373 # Inst execution rate +system.cpu.iew.wb_sent 1808734068 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805703486 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169239698 # num instructions producing a value +system.cpu.iew.wb_consumers 1689624086 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.171967 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692016 # average fanout of values written-back +system.cpu.iew.wb_rate 1.172023 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692012 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 257974948 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 258007667 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14629278 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1501179372 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.108483 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.025812 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14629355 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1501111622 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.108533 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.025633 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 920919616 61.35% 61.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250623048 16.70% 78.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110074231 7.33% 85.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55314266 3.68% 89.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29240414 1.95% 91.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34051194 2.27% 93.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24724968 1.65% 94.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18102388 1.21% 96.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58129247 3.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 920819202 61.34% 61.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250634053 16.70% 78.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110061016 7.33% 85.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55281373 3.68% 89.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29321487 1.95% 91.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34081425 2.27% 93.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24716781 1.65% 94.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18131809 1.21% 96.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58064476 3.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1501179372 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1501111622 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -696,76 +696,76 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58129247 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3365056908 # The number of ROB reads -system.cpu.rob.rob_writes 3883498749 # The number of ROB writes -system.cpu.timesIdled 826 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 78120 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58064476 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3365086648 # The number of ROB reads +system.cpu.rob.rob_writes 3883566462 # The number of ROB writes +system.cpu.timesIdled 859 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 79817 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.997522 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.997522 # CPI: Total CPI of All Threads -system.cpu.ipc 1.002484 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.002484 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175832090 # number of integer regfile reads -system.cpu.int_regfile_writes 1261554579 # number of integer regfile writes -system.cpu.fp_regfile_reads 42 # number of floating regfile reads -system.cpu.fp_regfile_writes 53 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965806989 # number of cc regfile reads -system.cpu.cc_regfile_writes 551858746 # number of cc regfile writes -system.cpu.misc_regfile_reads 675847493 # number of misc regfile reads +system.cpu.cpi 0.997481 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.997481 # CPI: Total CPI of All Threads +system.cpu.ipc 1.002525 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.002525 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175803949 # number of integer regfile reads +system.cpu.int_regfile_writes 1261568723 # number of integer regfile writes +system.cpu.fp_regfile_reads 40 # number of floating regfile reads +system.cpu.fp_regfile_writes 54 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965710140 # number of cc regfile reads +system.cpu.cc_regfile_writes 551865181 # number of cc regfile writes +system.cpu.misc_regfile_reads 675846539 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.replacements 17004655 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964606 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638048144 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17005167 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.520840 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 78823500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964606 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 17004606 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964973 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638063275 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17005118 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.521838 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 77839500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964973 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999932 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 419 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 420 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335675523 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335675523 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469328921 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469328921 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168719105 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168719105 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335698850 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335698850 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469343498 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469343498 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168719659 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168719659 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638048026 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638048026 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638048026 # number of overall hits -system.cpu.dcache.overall_hits::total 638048026 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17420086 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17420086 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3866942 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3866942 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638063157 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638063157 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638063157 # number of overall hits +system.cpu.dcache.overall_hits::total 638063157 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17417197 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17417197 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3866388 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3866388 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21287028 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21287028 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21287030 # number of overall misses -system.cpu.dcache.overall_misses::total 21287030 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 415615381500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 415615381500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 149888945711 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 149888945711 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 398000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 398000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 565504327211 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 565504327211 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 565504327211 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 565504327211 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486749007 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486749007 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21283585 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21283585 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21283587 # number of overall misses +system.cpu.dcache.overall_misses::total 21283587 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 415522893500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 415522893500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 149855935942 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 149855935942 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 216000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 216000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 565378829442 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 565378829442 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 565378829442 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 565378829442 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486760695 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486760695 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -774,74 +774,74 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659335054 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659335054 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659335056 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659335056 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035789 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035789 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022406 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022406 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659346742 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659346742 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659346744 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659346744 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035782 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035782 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022403 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022403 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032286 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032286 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032286 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032286 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23858.400096 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23858.400096 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38761.622417 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38761.622417 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 99500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 99500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26565.677802 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26565.677802 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26565.675306 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26565.675306 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20779473 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3451346 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 944816 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67198 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.993143 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51.360844 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.032280 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032280 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032280 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032280 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23857.047348 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23857.047348 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38758.638797 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38758.638797 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 54000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 54000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26564.078817 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26564.078817 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26564.076320 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26564.076320 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20755892 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3446894 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 946527 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67143 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.928473 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51.336610 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 4837348 # number of writebacks -system.cpu.dcache.writebacks::total 4837348 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3152457 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3152457 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129405 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1129405 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 4835415 # number of writebacks +system.cpu.dcache.writebacks::total 4835415 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3149636 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3149636 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1128832 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1128832 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4281862 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4281862 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4281862 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4281862 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14267629 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14267629 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737537 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737537 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4278468 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4278468 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4278468 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4278468 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14267561 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14267561 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737556 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737556 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17005166 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17005166 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17005167 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17005167 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335438494000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 335438494000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116411117573 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 116411117573 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17005117 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17005117 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17005118 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17005118 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335383172000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 335383172000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116381847286 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 116381847286 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451849611573 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 451849611573 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451849679573 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 451849679573 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029312 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029312 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451765019286 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 451765019286 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451765087286 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 451765087286 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029311 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029311 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses @@ -850,361 +850,364 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025791 system.cpu.dcache.demand_mshr_miss_rate::total 0.025791 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025791 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23510.458115 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23510.458115 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42524.034405 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42524.034405 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23506.692700 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23506.692700 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42513.047144 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42513.047144 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26571.314363 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26571.314363 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26571.316799 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26571.316799 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26566.416408 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26566.416408 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26566.418844 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26566.418844 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 582 # number of replacements -system.cpu.icache.tags.tagsinuse 445.815002 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656920172 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1070 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 613944.085981 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 592 # number of replacements +system.cpu.icache.tags.tagsinuse 446.127099 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656939322 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1080 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 608277.150000 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 445.815002 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.870732 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.870732 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 446.127099 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.871342 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.871342 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313844660 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313844660 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656920172 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656920172 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656920172 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656920172 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656920172 # number of overall hits -system.cpu.icache.overall_hits::total 656920172 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1623 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1623 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1623 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1623 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1623 # number of overall misses -system.cpu.icache.overall_misses::total 1623 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 104193985 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 104193985 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 104193985 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 104193985 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 104193985 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 104193985 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656921795 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656921795 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656921795 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656921795 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656921795 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656921795 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 1313883006 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313883006 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656939322 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656939322 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656939322 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656939322 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656939322 # number of overall hits +system.cpu.icache.overall_hits::total 656939322 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1641 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1641 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1641 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1641 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1641 # number of overall misses +system.cpu.icache.overall_misses::total 1641 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 107375484 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 107375484 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 107375484 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 107375484 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 107375484 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 107375484 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656940963 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656940963 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656940963 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656940963 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656940963 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656940963 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64198.388786 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 64198.388786 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 64198.388786 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 64198.388786 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 64198.388786 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 64198.388786 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 17135 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 748 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 190 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 90.184211 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 68 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65432.957952 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65432.957952 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65432.957952 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65432.957952 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65432.957952 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65432.957952 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 18112 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1654 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 192 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 94.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 165.400000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 553 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 553 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 553 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 553 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 553 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 553 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1070 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1070 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1070 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1070 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1070 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1070 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75689488 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 75689488 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75689488 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 75689488 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75689488 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 75689488 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 561 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 561 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 561 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 561 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 561 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 561 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1080 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1080 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1080 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1080 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1080 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1080 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76771987 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 76771987 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76771987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 76771987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76771987 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 76771987 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70737.839252 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70737.839252 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70737.839252 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70737.839252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70737.839252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70737.839252 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71085.173148 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71085.173148 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71085.173148 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71085.173148 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71085.173148 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71085.173148 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 11618797 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11638031 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 14266 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 11620529 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11640215 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 14721 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4656553 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 4712696 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16129.917520 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 27373018 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4728623 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 5.788793 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 29478535500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 5230.477637 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.698420 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7539.676601 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3341.064863 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.319243 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001141 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.460185 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.203922 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.984492 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 811 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 615 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 195 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 503 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2303 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1194 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9259 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1857 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.049500 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.922607 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 551304223 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 551304223 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 4837348 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 4837348 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1752512 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 312623157999 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 312691326499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68168500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 312623157999 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72748405464 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 385439731963 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1637565 # number of writebacks +system.cpu.l2cache.writebacks::total 1637565 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 4105 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 4105 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45593 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45593 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 49698 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 49698 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 49698 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 49698 # number of overall MSHR hits +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 100082 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 100082 # number of CleanEvict MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1001959 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1001959 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 980506 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 980506 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1039 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1039 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2738435 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2738435 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1039 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3718941 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3719980 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1039 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3718941 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1001959 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4721939 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72923665986 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72923665986 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93548158999 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93548158999 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 69146000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 69146000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 218917649000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 218917649000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 69146000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 312465807999 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 312534953999 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 69146000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 312465807999 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72923665986 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 385458619985 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.960748 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.960748 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.192014 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.192014 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960748 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.218801 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.218848 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960748 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.218801 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358163 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358163 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.962037 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.962037 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.191935 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.191935 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962037 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.218695 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.218743 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962037 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.218695 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.277745 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72631.323770 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 72631.323770 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95406.487057 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95406.487057 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66311.770428 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66311.770428 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79944.046391 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79944.046391 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66311.770428 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84021.520924 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84016.629278 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66311.770428 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84021.520924 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72631.323770 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81602.334417 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.277660 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72781.087835 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 72781.087835 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95408.043397 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95408.043397 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66550.529355 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66550.529355 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79942.612843 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79942.612843 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66550.529355 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84020.103572 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84015.224275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66550.529355 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84020.103572 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72781.087835 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81631.427256 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 14268653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 6475946 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 15220389 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1280497 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1070 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14267583 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50993396 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 50996114 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397921024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1397989504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 5993194 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 40004669 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.149812 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.356887 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 34011398 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17005208 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21592 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 111772 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 111653 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 119 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 14268599 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 6472980 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 15222988 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1281199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737599 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737599 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1080 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14267519 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2748 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50993254 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 50996002 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397794112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1397863232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 5993561 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 40004959 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.003877 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.062190 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 34011476 85.02% 85.02% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 5993193 14.98% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 39849994 99.61% 99.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 154846 0.39% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 119 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 40004669 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 21843087497 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 40004959 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 21841114998 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1500 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1605000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1620000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25507754991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25507681990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3739456 # Transaction distribution -system.membus.trans_dist::Writeback 1638598 # Transaction distribution -system.membus.trans_dist::CleanEvict 3064906 # Transaction distribution -system.membus.trans_dist::ReadExReq 981345 # Transaction distribution -system.membus.trans_dist::ReadExResp 981345 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3739456 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14145106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14145106 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 407001536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 407001536 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3739654 # Transaction distribution +system.membus.trans_dist::Writeback 1637565 # Transaction distribution +system.membus.trans_dist::CleanEvict 3065415 # Transaction distribution +system.membus.trans_dist::ReadExReq 980644 # Transaction distribution +system.membus.trans_dist::ReadExResp 980644 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3739654 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14143576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14143576 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406903232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 406903232 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 9424305 # Request fanout histogram +system.membus.snoop_fanout::samples 9423278 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9424305 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 9423278 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9424305 # Request fanout histogram -system.membus.reqLayer0.occupancy 17323735553 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 9423278 # Request fanout histogram +system.membus.reqLayer0.occupancy 17318873513 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 25676323677 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25673835894 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 939603453..3fad64f8d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.363367 # Number of seconds simulated -sim_ticks 2363367211500 # Number of ticks simulated -final_tick 2363367211500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.363368 # Number of seconds simulated +sim_ticks 2363368369500 # Number of ticks simulated +final_tick 2363368369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1091670 # Simulator instruction rate (inst/s) -host_op_rate 1176427 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1676685643 # Simulator tick rate (ticks/s) -host_mem_usage 312924 # Number of bytes of host memory used -host_seconds 1409.55 # Real time elapsed on the host +host_inst_rate 1008024 # Simulator instruction rate (inst/s) +host_op_rate 1086287 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1548215415 # Simulator tick rate (ticks/s) +host_mem_usage 315828 # Number of bytes of host memory used +host_seconds 1526.51 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,16 +26,16 @@ system.physmem.num_reads::total 1951712 # Nu system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 16681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52835693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52852374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52835667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52852348 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 16681 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 16681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27652126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27652126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27652126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 27652112 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27652112 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27652112 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 16681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52835693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80504500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52835667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80504461 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4726734423 # number of cpu cycles simulated +system.cpu.numCycles 4726736739 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759602 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 633153380 # nu system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 4726734422.998000 # Number of busy cycles +system.cpu.num_busy_cycles 4726736738.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 213462427 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.732137 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4083.732103 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25164659500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732137 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 25164683500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732103 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -254,14 +254,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115235 # n system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143051795500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143051795500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143052931500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143052931500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 57408921000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 57408921000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200460716500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200460716500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200460716500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200460716500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200461852500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200461852500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200461852500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200461852500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) @@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.580818 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.580818 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.738027 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.738027 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.773464 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.773464 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.831971 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21991.831971 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.829559 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21991.829559 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.956598 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21991.956598 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.954185 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21991.954185 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135825709500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 135825709500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135826845500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 135826845500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55519772000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 55519772000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191345481500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191345481500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191345535500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 191345535500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191346617500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 191346617500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191346671500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 191346671500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.580818 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.580818 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.738027 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.738027 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.773464 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.773464 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.831971 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.831971 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.835593 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.835593 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.956598 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.956598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.960219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.960219 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 515.003161 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 515.003151 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 515.003161 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 515.003151 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.251466 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.251466 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id @@ -373,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34212000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34212000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34212000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34212000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34212000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34212000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34234000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34234000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34234000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34234000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34234000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34234000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses @@ -391,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53623.824451 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53623.824451 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53623.824451 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53623.824451 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53623.824451 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53623.824451 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53658.307210 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53658.307210 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53658.307210 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53658.307210 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -411,34 +411,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33574000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33574000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33574000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33574000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33574000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33574000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33596000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33596000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33596000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33596000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33596000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 33596000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52623.824451 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52623.824451 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52623.824451 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52623.824451 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52623.824451 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52623.824451 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52658.307210 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52658.307210 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1919018 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31008.198929 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31008.199290 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14386233 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1948786 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 7.382151 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 150067845000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15515.969324 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.734669 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15468.494937 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 150067869000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15515.970631 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.734659 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15468.494001 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.473510 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000724 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.472061 # Average percentage of cache occupancy @@ -482,14 +482,14 @@ system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41062370000 system.cpu.l2cache.ReadExReq_miss_latency::total 41062370000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 32383000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 32383000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61386841500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 61386841500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61386933500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 61386933500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 32383000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 102449211500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 102481594500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 102449303500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 102481686500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 32383000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 102449211500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 102481594500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102449303500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 102481686500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 3681379 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 3681379 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) @@ -520,14 +520,14 @@ system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.562565 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.562565 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52569.805195 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52569.805195 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.885372 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.885372 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.964074 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.964074 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52569.805195 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.544685 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52508.564020 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52508.611158 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52569.805195 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.544685 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52508.564020 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52508.611158 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -556,14 +556,14 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33241050000 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33241050000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26223000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26223000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697201500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697201500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697293500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697293500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26223000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938251500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 82964474500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938343500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 82964566500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26223000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938251500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 82964474500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938343500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 82964566500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414013 # mshr miss rate for ReadExReq accesses @@ -582,15 +582,21 @@ system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.562565 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.562565 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42569.805195 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42569.805195 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.885372 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.885372 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.964074 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.964074 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.544685 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.564020 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.544685 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.564020 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 4702506 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6326508 # Transaction distribution @@ -606,15 +612,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 819024192 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1919018 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 20146039 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.095255 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.293567 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18227021 90.47% 90.47% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1919018 9.53% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 20142667 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3372 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 20146039 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12794889500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 6d8265542..c34bcec93 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.882285 # Nu sim_ticks 5882284743500 # Number of ticks simulated final_tick 5882284743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 724530 # Simulator instruction rate (inst/s) -host_op_rate 1128884 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1416814365 # Simulator tick rate (ticks/s) -host_mem_usage 314268 # Number of bytes of host memory used -host_seconds 4151.77 # Real time elapsed on the host +host_inst_rate 704974 # Simulator instruction rate (inst/s) +host_op_rate 1098413 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1378571885 # Simulator tick rate (ticks/s) +host_mem_usage 317252 # Number of bytes of host memory used +host_seconds 4266.94 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -449,6 +449,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42523.703704 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.019475 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.027666 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 4705009 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6322744 # Transaction distribution @@ -464,15 +470,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 818948672 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1919162 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 20141105 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.095286 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.293609 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000050 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.007053 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18221943 90.47% 90.47% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1919162 9.53% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 20140103 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1002 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 20141105 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12793692500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 5fb393485..11356e644 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.051911 # Nu sim_ticks 51910606500 # Number of ticks simulated final_tick 51910606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 229005 # Simulator instruction rate (inst/s) -host_op_rate 229005 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 129351336 # Simulator tick rate (ticks/s) -host_mem_usage 295204 # Number of bytes of host memory used -host_seconds 401.31 # Real time elapsed on the host +host_inst_rate 339215 # Simulator instruction rate (inst/s) +host_op_rate 339215 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 191602600 # Simulator tick rate (ticks/s) +host_mem_usage 303192 # Number of bytes of host memory used +host_seconds 270.93 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -663,6 +663,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.343434 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66538.354254 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65434.104155 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 32052 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 14007 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 16300 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 13900 # Transaction distribution @@ -678,15 +684,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 1161728 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 32052 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 32052 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 32052 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 32052 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 16133000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index f7c0c31d6..cc5b93144 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.021919 # Nu sim_ticks 21919473500 # Number of ticks simulated final_tick 21919473500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134628 # Simulator instruction rate (inst/s) -host_op_rate 134628 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35055621 # Simulator tick rate (ticks/s) -host_mem_usage 296224 # Number of bytes of host memory used -host_seconds 625.28 # Real time elapsed on the host +host_inst_rate 199769 # Simulator instruction rate (inst/s) +host_op_rate 199769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52017673 # Simulator tick rate (ticks/s) +host_mem_usage 302932 # Number of bytes of host memory used +host_seconds 421.39 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -971,6 +971,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66375.776398 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68822.088725 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67389.335631 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 23293 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9635 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 11922 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 9527 # Transaction distribution @@ -986,15 +992,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 881024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 23293 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 23293 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 23293 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 23293 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 11754500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 396e2f8dd..13ae4452a 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.130773 # Number of seconds simulated -sim_ticks 130772636500 # Number of ticks simulated -final_tick 130772636500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 130772642500 # Number of ticks simulated +final_tick 130772642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167747 # Simulator instruction rate (inst/s) -host_op_rate 176832 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 127303889 # Simulator tick rate (ticks/s) -host_mem_usage 312696 # Number of bytes of host memory used -host_seconds 1027.25 # Real time elapsed on the host +host_inst_rate 233615 # Simulator instruction rate (inst/s) +host_op_rate 246267 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 177290947 # Simulator tick rate (ticks/s) +host_mem_usage 321196 # Number of bytes of host memory used +host_seconds 737.62 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -22,12 +22,12 @@ system.physmem.num_reads::cpu.inst 2158 # Nu system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 1056123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 835894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 835893 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1892017 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1056123 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1056123 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1056123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 835894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 835893 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1892017 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3866 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 130772543000 # Total gap between requests +system.physmem.totGap 130772548000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 17 1.88% 91.49% # By system.physmem.bytesPerActivate::896-1023 17 1.88% 93.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 60 6.63% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 905 # Bytes accessed per row activation -system.physmem.totQLat 28055750 # Total ticks spent queuing -system.physmem.totMemAccLat 100543250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 27654500 # Total ticks spent queuing +system.physmem.totMemAccLat 100142000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7257.05 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7153.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26007.05 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25903.26 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s @@ -220,35 +220,35 @@ system.physmem.readRowHits 2957 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33826317.38 # Average gap between requests +system.physmem.avgGap 33826318.68 # Average gap between requests system.physmem.pageHitRate 76.49 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 3099600 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 1691250 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3568801635 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75331661250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 87462680535 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.826718 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 125318913500 # Time in different power states +system.physmem_0.actBackEnergy 3568631490 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75331810500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 87462659640 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.826558 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 125319167750 # Time in different power states system.physmem_0.memoryStateTime::REF 4366700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1084715250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1084461000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 3727080 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2033625 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3564422325 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75335511000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 87460741830 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.811822 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 125325774500 # Time in different power states +system.physmem_1.actBackEnergy 3564306900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75335612250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 87460727655 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.811714 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 125325942500 # Time in different power states system.physmem_1.memoryStateTime::REF 4366700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1078159500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1077991500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 49732170 # Number of BP lookups system.cpu.branchPred.condPredicted 39495980 # Number of conditional branches predicted @@ -377,7 +377,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 261545273 # number of cpu cycles simulated +system.cpu.numCycles 261545285 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed @@ -386,15 +386,15 @@ system.cpu.discardedOps 11660914 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.517808 # CPI: cycles per instruction system.cpu.ipc 0.658845 # IPC: instructions per cycle -system.cpu.tickCycles 255251954 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6293319 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 255252020 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6293265 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.707601 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1377.707606 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40756382 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22517.338122 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707601 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707606 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.336354 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.336354 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id @@ -430,14 +430,14 @@ system.cpu.dcache.demand_misses::cpu.data 2442 # n system.cpu.dcache.demand_misses::total 2442 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2443 # number of overall misses system.cpu.dcache.overall_misses::total 2443 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58025500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58025500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 126322500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 126322500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 184348000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 184348000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 184348000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 184348000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58082000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58082000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126294500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126294500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184376500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184376500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184376500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184376500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 28349261 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 28349261 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) @@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73079.974811 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73079.974811 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76652.002427 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76652.002427 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75490.581491 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75490.581491 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75459.680720 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75459.680720 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73151.133501 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73151.133501 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76635.012136 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76635.012136 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75502.252252 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75502.252252 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75471.346705 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75471.346705 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1809 system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51768000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51768000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85075000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85075000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51822500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51822500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85060000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85060000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136843000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 136843000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136913000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 136913000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136882500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 136882500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136952500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 136952500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -518,24 +518,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72810.126582 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72810.126582 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77481.785064 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77481.785064 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72886.779184 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72886.779184 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77468.123862 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77468.123862 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75645.660586 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75645.660586 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75642.541436 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75642.541436 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75667.495854 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75667.495854 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75664.364641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75664.364641 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2888 # number of replacements -system.cpu.icache.tags.tagsinuse 1423.991727 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1423.991712 # Cycle average of tags in use system.cpu.icache.tags.total_refs 71011798 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4684 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15160.503416 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991727 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991712 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.695308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.695308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id @@ -559,12 +559,12 @@ system.cpu.icache.demand_misses::cpu.inst 4685 # n system.cpu.icache.demand_misses::total 4685 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4685 # number of overall misses system.cpu.icache.overall_misses::total 4685 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 199910500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 199910500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 199910500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 199910500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 199910500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 199910500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 199916500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 199916500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 199916500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 199916500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 199916500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 199916500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 71016483 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 71016483 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 71016483 # number of demand (read+write) accesses @@ -577,12 +577,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42670.330843 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42670.330843 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42670.330843 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42670.330843 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42670.330843 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42670.330843 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42671.611526 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42671.611526 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42671.611526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42671.611526 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -597,34 +597,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4685 system.cpu.icache.demand_mshr_misses::total 4685 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4685 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4685 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195226500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 195226500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195226500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 195226500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195226500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 195226500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195232500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 195232500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195232500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 195232500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195232500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 195232500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41670.544290 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41670.544290 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41670.544290 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41670.544290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41670.544290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41670.544290 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41671.824973 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41671.824973 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2000.604150 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2000.604140 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 5191 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2784 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.864583 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.029284 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.756657 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 490.818208 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 3.029285 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.756648 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 490.818207 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045983 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy @@ -664,18 +664,18 @@ system.cpu.l2cache.demand_misses::total 3883 # nu system.cpu.l2cache.overall_misses::cpu.inst 2161 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses system.cpu.l2cache.overall_misses::total 3883 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83342500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 83342500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161697500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 161697500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49918000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 49918000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 161697500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 133260500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 294958000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 161697500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 133260500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 294958000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83327500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 83327500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161329500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 161329500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49900500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 49900500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 161329500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 133228000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 294557500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 161329500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 133228000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 294557500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) @@ -702,18 +702,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.597844 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461259 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.597844 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76461.009174 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76461.009174 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74825.312355 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74825.312355 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78984.177215 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78984.177215 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74825.312355 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77387.049942 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75961.370075 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74825.312355 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77387.049942 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75961.370075 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76447.247706 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76447.247706 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74655.020824 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74655.020824 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78956.487342 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78956.487342 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75858.228174 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75858.228174 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -744,18 +744,18 @@ system.cpu.l2cache.demand_mshr_misses::total 3867 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2159 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3867 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72442500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72442500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139969500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139969500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42776000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42776000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139969500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115218500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 255188000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139969500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115218500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 255188000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72427500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72427500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139601500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139601500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42758500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42758500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139601500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115186000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 254787500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139601500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115186000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 254787500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for ReadCleanReq accesses @@ -768,19 +768,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.595381 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.595381 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66461.009174 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66461.009174 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64830.708661 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64830.708661 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69216.828479 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69216.828479 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64830.708661 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67458.138173 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65991.207655 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64830.708661 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67458.138173 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65991.207655 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66447.247706 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66447.247706 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64660.259379 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64660.259379 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69188.511327 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69188.511327 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 9425 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3064 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 5396 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2586 # Transaction distribution @@ -796,14 +802,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 416640 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 9425 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.083820 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.277132 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 9425 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 8635 91.62% 91.62% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 790 8.38% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 9425 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4728500 # Layer occupancy (ticks) @@ -831,9 +837,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3866 # Request fanout histogram -system.membus.reqLayer0.occupancy 4535000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20543000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20543250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index b0d8b3c34..7a60aaca0 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085022 # Number of seconds simulated -sim_ticks 85021523000 # Number of ticks simulated -final_tick 85021523000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085039 # Number of seconds simulated +sim_ticks 85038866000 # Number of ticks simulated +final_tick 85038866000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136979 # Simulator instruction rate (inst/s) -host_op_rate 144399 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67591393 # Simulator tick rate (ticks/s) -host_mem_usage 315696 # Number of bytes of host memory used -host_seconds 1257.88 # Real time elapsed on the host +host_inst_rate 124768 # Simulator instruction rate (inst/s) +host_op_rate 131526 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61578459 # Simulator tick rate (ticks/s) +host_mem_usage 316956 # Number of bytes of host memory used +host_seconds 1380.98 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 126976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 47808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71104 # Number of bytes read from this memory -system.physmem.bytes_read::total 245888 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 126976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 126976 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1984 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 747 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1111 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3842 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1493457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 562305 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 836306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2892068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1493457 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1493457 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1493457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 562305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 836306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2892068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3842 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 127040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71424 # Number of bytes read from this memory +system.physmem.bytes_read::total 246336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 127040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 127040 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1985 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 748 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1116 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3849 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1493905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 562943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 839898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2896746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1493905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1493905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1493905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 562943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 839898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2896746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3849 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3842 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3849 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 245888 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 246336 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 245888 # Total read bytes from the system interface side +system.physmem.bytesReadSys 246336 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 309 # Per bank write bursts -system.physmem.perBankRdBursts::1 220 # Per bank write bursts +system.physmem.perBankRdBursts::1 223 # Per bank write bursts system.physmem.perBankRdBursts::2 134 # Per bank write bursts -system.physmem.perBankRdBursts::3 310 # Per bank write bursts -system.physmem.perBankRdBursts::4 307 # Per bank write bursts +system.physmem.perBankRdBursts::3 318 # Per bank write bursts +system.physmem.perBankRdBursts::4 300 # Per bank write bursts system.physmem.perBankRdBursts::5 302 # Per bank write bursts system.physmem.perBankRdBursts::6 262 # Per bank write bursts -system.physmem.perBankRdBursts::7 232 # Per bank write bursts +system.physmem.perBankRdBursts::7 237 # Per bank write bursts system.physmem.perBankRdBursts::8 252 # Per bank write bursts system.physmem.perBankRdBursts::9 219 # Per bank write bursts system.physmem.perBankRdBursts::10 292 # Per bank write bursts system.physmem.perBankRdBursts::11 194 # Per bank write bursts -system.physmem.perBankRdBursts::12 193 # Per bank write bursts +system.physmem.perBankRdBursts::12 191 # Per bank write bursts system.physmem.perBankRdBursts::13 211 # Per bank write bursts system.physmem.perBankRdBursts::14 211 # Per bank write bursts system.physmem.perBankRdBursts::15 194 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85021379500 # Total gap between requests +system.physmem.totGap 85038722500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3842 # Read request sizes (log2) +system.physmem.readPktSize::6 3849 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,15 +94,15 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2529 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 872 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 770 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 317.174026 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 198.484323 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 309.262764 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 239 31.04% 31.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 194 25.19% 56.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 82 10.65% 66.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 86 11.17% 78.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 28 3.64% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 38 4.94% 86.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 15 1.95% 88.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 16 2.08% 90.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 72 9.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 770 # Bytes accessed per row activation -system.physmem.totQLat 41378240 # Total ticks spent queuing -system.physmem.totMemAccLat 113415740 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19210000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10769.97 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 773 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 316.357050 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 198.451466 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 308.377497 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 239 30.92% 30.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 194 25.10% 56.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 84 10.87% 66.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 87 11.25% 78.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 29 3.75% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 4.79% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 16 2.07% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13 1.68% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 74 9.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 773 # Bytes accessed per row activation +system.physmem.totQLat 41463141 # Total ticks spent queuing +system.physmem.totMemAccLat 113631891 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19245000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10772.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29519.97 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29522.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.89 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing +system.physmem.avgRdQLen 2.83 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3065 # Number of row buffer hits during reads +system.physmem.readRowHits 3069 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.78 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.73 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 22129458.49 # Average gap between requests -system.physmem.pageHitRate 79.78 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2766960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1509750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 22093718.50 # Average gap between requests +system.physmem.pageHitRate 79.73 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2789640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1522125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16239600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5552966640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2338310430 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 48959844750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 56871567930 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.933066 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81449206260 # Time in different power states -system.physmem_0.memoryStateTime::REF 2838940000 # Time in different power states +system.physmem_0.refreshEnergy 5553983760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2338576335 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48968955000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 56882066460 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.934025 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81466129254 # Time in different power states +system.physmem_0.memoryStateTime::REF 2839460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 731844740 # Time in different power states +system.physmem_0.memoryStateTime::ACT 731738246 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3039120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1658250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13579800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3031560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1654125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13525200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5552966640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2293221150 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 48999396750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 56863861710 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.842424 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 81513735655 # Time in different power states -system.physmem_1.memoryStateTime::REF 2838940000 # Time in different power states +system.physmem_1.refreshEnergy 5553983760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2304071955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 48999213750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56875480350 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.856680 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 81513506905 # Time in different power states +system.physmem_1.memoryStateTime::REF 2839460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 665661845 # Time in different power states +system.physmem_1.memoryStateTime::ACT 681039595 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 85912132 # Number of BP lookups -system.cpu.branchPred.condPredicted 68393043 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6015535 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40101121 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39014567 # Number of BTB hits +system.cpu.branchPred.lookups 85929659 # Number of BP lookups +system.cpu.branchPred.condPredicted 68408036 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6017804 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 40110757 # Number of BTB lookups +system.cpu.branchPred.BTBHits 39021888 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.290465 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3703090 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81902 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.285344 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3703815 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81895 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,96 +381,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 170043047 # number of cpu cycles simulated +system.cpu.numCycles 170077733 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5613517 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349250630 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85912132 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42717657 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158263984 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12044969 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5627528 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349301730 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85929659 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42725703 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158283885 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12049307 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1743 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 2395 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78950646 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18010 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169904018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.150531 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.047148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 2380 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78962015 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18924 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169940212 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.150377 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.047263 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17361437 10.22% 10.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30204201 17.78% 28.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31835536 18.74% 46.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90502844 53.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17375065 10.22% 10.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30210489 17.78% 28.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31838895 18.74% 46.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90515763 53.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169904018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 169940212 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.505238 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.053895 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17563904 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17112948 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122657441 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6722163 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5847562 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11134700 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 190128 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306600022 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27639979 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5847562 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37746058 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8470500 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 579781 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108923622 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8336495 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278650706 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13412569 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3051463 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 842712 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2185705 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 36039 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 26489 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483080897 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1196921555 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297573893 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3006747 # Number of floating rename lookups +system.cpu.fetch.rate 2.053777 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17579546 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17112098 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 122676977 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6721861 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5849730 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11135516 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 190121 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 306633664 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27649172 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5849730 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37767470 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8469466 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 579515 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108936835 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8337196 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 278676031 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13415385 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3051308 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 841767 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2187025 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 37328 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 26465 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 483141060 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1197017326 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 297598208 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3006154 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190103968 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23523 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23430 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13336341 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34142087 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14476532 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2549378 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1793123 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 264810332 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45855 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214902707 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5190620 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 83220233 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219925371 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 639 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169904018 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.264848 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017464 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 190164131 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23534 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23437 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13334158 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 34140467 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14476937 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2547302 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1809047 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 264833552 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45866 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214914716 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5193890 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 83243464 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 219964835 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 650 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169940212 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.264649 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017441 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52834646 31.10% 31.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36093194 21.24% 52.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65784220 38.72% 91.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13574325 7.99% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1570253 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47194 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 186 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52857789 31.10% 31.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36101949 21.24% 52.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65794996 38.72% 91.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13566772 7.98% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1571259 0.92% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47259 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 188 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169904018 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169940212 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35605027 66.11% 66.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 152712 0.28% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35605031 66.12% 66.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 152953 0.28% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.40% # attempts to use FU when none available @@ -489,22 +489,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.40% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1068 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1062 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35741 0.07% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35733 0.07% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 238 0.00% 66.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 1038 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34404 0.06% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 1040 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34389 0.06% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14078476 26.14% 92.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3945873 7.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14077055 26.14% 92.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3945216 7.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167344168 77.87% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918970 0.43% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167357469 77.87% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 918949 0.43% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued @@ -523,93 +523,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33018 0.02% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33022 0.02% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165202 0.08% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245708 0.11% 78.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165195 0.08% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245712 0.11% 78.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460547 0.21% 78.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206694 0.10% 78.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460561 0.21% 78.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206706 0.10% 78.85% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32006913 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13373527 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32005826 14.89% 93.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13373316 6.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214902707 # Type of FU issued -system.cpu.iq.rate 1.263814 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53854783 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.250601 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654801069 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 346070765 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204597399 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3953766 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2012584 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806443 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266623022 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2134468 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1601145 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214914716 # Type of FU issued +system.cpu.iq.rate 1.263626 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53852922 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.250578 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654863168 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 346117768 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204606131 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3953288 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2011882 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806358 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266633604 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2134034 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1600995 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6245943 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7536 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7067 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1831898 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6244323 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7621 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6899 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1832303 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25713 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 795 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25728 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 844 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5847562 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5681846 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37059 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 264872174 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5849730 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5682254 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 37001 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 264895393 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34142087 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14476532 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23447 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3919 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29973 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7067 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3232804 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3246682 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6479486 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207521845 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30720947 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7380862 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 34140467 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14476937 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23458 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3889 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29998 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6899 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3234969 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3247770 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6482739 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207531016 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30721231 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7383700 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15987 # number of nop insts executed -system.cpu.iew.exec_refs 43860767 # number of memory reference insts executed -system.cpu.iew.exec_branches 44934593 # Number of branches executed -system.cpu.iew.exec_stores 13139820 # Number of stores executed -system.cpu.iew.exec_rate 1.220408 # Inst execution rate -system.cpu.iew.wb_sent 206738836 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206403842 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129472696 # num instructions producing a value -system.cpu.iew.wb_consumers 221699614 # num instructions consuming a value +system.cpu.iew.exec_nop 15975 # number of nop insts executed +system.cpu.iew.exec_refs 43860800 # number of memory reference insts executed +system.cpu.iew.exec_branches 44937472 # Number of branches executed +system.cpu.iew.exec_stores 13139569 # Number of stores executed +system.cpu.iew.exec_rate 1.220213 # Inst execution rate +system.cpu.iew.wb_sent 206747617 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206412489 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129477272 # num instructions producing a value +system.cpu.iew.wb_consumers 221702085 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.213833 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584001 # average fanout of values written-back +system.cpu.iew.wb_rate 1.213636 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.584015 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69532937 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69549191 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5840613 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158463001 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.146327 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.646694 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5842881 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158496522 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146084 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.646497 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73683575 46.50% 46.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41276323 26.05% 72.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22553918 14.23% 86.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9626893 6.08% 92.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3550160 2.24% 95.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2147765 1.36% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1281178 0.81% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 986541 0.62% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3356648 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73710350 46.51% 46.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41283484 26.05% 72.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22554549 14.23% 86.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9626760 6.07% 92.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3551822 2.24% 95.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2145509 1.35% 96.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1280291 0.81% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 989155 0.62% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3354602 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158463001 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158496522 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,381 +655,380 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3356648 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 406284431 # The number of ROB reads -system.cpu.rob.rob_writes 513821512 # The number of ROB writes -system.cpu.timesIdled 3435 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 139029 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3354602 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 406336252 # The number of ROB reads +system.cpu.rob.rob_writes 513856795 # The number of ROB writes +system.cpu.timesIdled 3529 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 137521 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.986884 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.986884 # CPI: Total CPI of All Threads -system.cpu.ipc 1.013291 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.013291 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218956389 # number of integer regfile reads -system.cpu.int_regfile_writes 114512069 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904391 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441624 # number of floating regfile writes -system.cpu.cc_regfile_reads 709567724 # number of cc regfile reads -system.cpu.cc_regfile_writes 229536137 # number of cc regfile writes -system.cpu.misc_regfile_reads 59314172 # number of misc regfile reads +system.cpu.cpi 0.987085 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.987085 # CPI: Total CPI of All Threads +system.cpu.ipc 1.013084 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.013084 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218963852 # number of integer regfile reads +system.cpu.int_regfile_writes 114515225 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904259 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441612 # number of floating regfile writes +system.cpu.cc_regfile_reads 709595430 # number of cc regfile reads +system.cpu.cc_regfile_writes 229551730 # number of cc regfile writes +system.cpu.misc_regfile_reads 59313283 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.replacements 72862 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.418427 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41115433 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73374 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.354254 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 72876 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.418230 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41115950 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73388 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 560.254401 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 506092500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.418427 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.418230 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998864 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998864 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 225 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82529738 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82529738 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28729196 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28729196 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341320 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341320 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82530918 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82530918 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28729730 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28729730 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341303 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341303 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22149 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22149 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41070516 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41070516 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41070877 # number of overall hits -system.cpu.dcache.overall_hits::total 41070877 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89406 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89406 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22967 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22967 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 117 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 117 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 41071033 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41071033 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41071394 # number of overall hits +system.cpu.dcache.overall_hits::total 41071394 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89456 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89456 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22984 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22984 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112373 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112373 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112490 # number of overall misses -system.cpu.dcache.overall_misses::total 112490 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 857195000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 857195000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 240069999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 240069999 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 112440 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112440 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112556 # number of overall misses +system.cpu.dcache.overall_misses::total 112556 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 857049000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 857049000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 246637999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 246637999 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2309500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 2309500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1097264999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1097264999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1097264999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1097264999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28818602 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28818602 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1103686999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1103686999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1103686999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1103686999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28819186 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28819186 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 478 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 478 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 477 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 477 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22408 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22408 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41182889 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41182889 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41183367 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41183367 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003102 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003102 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001858 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001858 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.244770 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.244770 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41183473 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41183473 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41183950 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41183950 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003104 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003104 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001859 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001859 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.243187 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.243187 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011558 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011558 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002729 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002729 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002731 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002731 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9587.667494 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9587.667494 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10452.823573 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10452.823573 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9580.676534 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9580.676534 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10730.856204 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10730.856204 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8916.988417 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8916.988417 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9764.489682 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9764.489682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9754.333710 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9754.333710 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9815.786188 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9815.786188 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9805.670058 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9805.670058 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10364 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 11592 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 866 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 859 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 11.967667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 13.494761 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 64850 # number of writebacks -system.cpu.dcache.writebacks::total 64850 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24708 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24708 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14405 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14405 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 64866 # number of writebacks +system.cpu.dcache.writebacks::total 64866 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24759 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24759 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14406 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14406 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39113 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39113 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39113 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39113 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64698 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64698 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8562 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8562 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 114 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 114 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 73260 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 73260 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73374 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73374 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 560329500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 560329500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85295999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85295999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 970000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 970000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 645625499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 645625499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 646595499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 646595499 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 39165 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39165 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39165 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39165 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64697 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64697 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8578 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 73275 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 73275 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73388 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73388 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 560382500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 560382500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86241499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 86241499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 962000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 962000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 646623999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 646623999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 647585999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 647585999 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.238494 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.238494 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000694 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000694 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.236897 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.236897 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001779 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001782 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8660.692757 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8660.692757 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9962.158257 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9962.158257 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8508.771930 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8508.771930 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8812.796874 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8812.796874 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8812.324515 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8812.324515 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8661.645826 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8661.645826 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10053.800303 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10053.800303 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8513.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8513.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8824.619570 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8824.619570 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8824.140173 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8824.140173 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 54433 # number of replacements -system.cpu.icache.tags.tagsinuse 510.603635 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78892635 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54945 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1435.847393 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 84266921500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.603635 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 54478 # number of replacements +system.cpu.icache.tags.tagsinuse 510.603674 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78903878 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54990 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1434.876850 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84285313500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.603674 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997273 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997273 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 275 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157956195 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157956195 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78892635 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78892635 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78892635 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78892635 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78892635 # number of overall hits -system.cpu.icache.overall_hits::total 78892635 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57990 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57990 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57990 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57990 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57990 # number of overall misses -system.cpu.icache.overall_misses::total 57990 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 602731956 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 602731956 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 602731956 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 602731956 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 602731956 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 602731956 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78950625 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78950625 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78950625 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78950625 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78950625 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78950625 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000735 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000735 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000735 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000735 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000735 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000735 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10393.722297 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10393.722297 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10393.722297 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10393.722297 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10393.722297 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10393.722297 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 59431 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 157978976 # Number of tag accesses +system.cpu.icache.tags.data_accesses 157978976 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78903878 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78903878 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78903878 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78903878 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78903878 # number of overall hits +system.cpu.icache.overall_hits::total 78903878 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 58115 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 58115 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 58115 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 58115 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 58115 # number of overall misses +system.cpu.icache.overall_misses::total 58115 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 612004953 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 612004953 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 612004953 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 612004953 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 612004953 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 612004953 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78961993 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78961993 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78961993 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78961993 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78961993 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78961993 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000736 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000736 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000736 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000736 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000736 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000736 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10530.929244 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10530.929244 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10530.929244 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10530.929244 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10530.929244 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10530.929244 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 59295 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2848 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2885 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.867626 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.552860 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # 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number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2293 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.016174 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.202698 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3935898 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3935898 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 64866 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 64866 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8409 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8409 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 52999 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 52999 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 64221 # 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number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1991 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 758 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2749 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1991 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 758 # number of overall misses +system.cpu.l2cache.overall_misses::total 2749 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 19008500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 19008500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 136250000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 136250000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38006500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 38006500 # 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number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 54990 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64740 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 64740 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 54945 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 73374 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 128319 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 54945 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 73374 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 128319 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027102 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.027102 # 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average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77602.564103 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68600.251256 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68600.251256 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 74950.191571 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 74950.191571 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68600.251256 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75771.164021 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70574.471959 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68600.251256 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75771.164021 # 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average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68432.948267 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73230.250482 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73230.250482 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68432.948267 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75217.678100 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70303.746817 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68432.948267 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75217.678100 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70303.746817 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1038,133 +1037,139 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 2 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 2 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 6 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 176401000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 124261000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 52140000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 69341141 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 245742141 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1765 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1765 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 237 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 237 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1985 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1985 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 511 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 511 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1985 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 748 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2733 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1985 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 748 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1765 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4498 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 70524171 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 70524171 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 17163500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 17163500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 124005500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 124005500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34486500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34486500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 124005500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 51650000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 175655500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 124005500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 51650000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 70524171 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 246179671 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.026986 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.026986 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.036109 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.007939 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.007939 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010181 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.021283 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010181 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027405 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027405 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.036097 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.036097 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.007893 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.007893 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036097 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010192 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.021289 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036097 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010192 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.035521 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37953.552819 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37953.552819 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71047.210300 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71047.210300 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62631.552419 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62631.552419 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69233.463035 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69233.463035 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62631.552419 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69799.196787 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64592.090809 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62631.552419 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69799.196787 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37953.552819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53914.467091 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.035037 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39957.037394 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 39957.037394 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72419.831224 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72419.831224 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62471.284635 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62471.284635 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67488.258317 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67488.258317 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62471.284635 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69050.802139 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64272.045371 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62471.284635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69050.802139 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39957.037394 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54730.918408 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 119685 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 64850 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 51933 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2169 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54945 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 255732 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 127373 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 649 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 649 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 119730 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 64866 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 51985 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8648 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8648 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54990 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 64740 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 155974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217447 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 373421 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8846336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 12362816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2169 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 257783 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.008414 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.091342 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 156105 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217502 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 373607 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3519360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8848256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12367616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2111 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 257843 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.084059 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.277477 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 255614 99.16% 99.16% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2169 0.84% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 236169 91.59% 91.59% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 21674 8.41% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 257783 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 192657000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 257843 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 192732000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82431971 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 82511447 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110065491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 110086990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3609 # Transaction distribution -system.membus.trans_dist::ReadExReq 233 # Transaction distribution -system.membus.trans_dist::ReadExResp 233 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3609 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7684 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7684 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 245888 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 245888 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3612 # Transaction distribution +system.membus.trans_dist::ReadExReq 237 # Transaction distribution +system.membus.trans_dist::ReadExResp 237 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3612 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7698 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7698 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 246336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 246336 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3842 # Request fanout histogram +system.membus.snoop_fanout::samples 3849 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3842 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3849 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3842 # Request fanout histogram -system.membus.reqLayer0.occupancy 4994667 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3849 # Request fanout histogram +system.membus.reqLayer0.occupancy 5019167 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20261553 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20293808 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index cd6ba3bb4..fda8a8b37 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.079147 # Number of seconds simulated -sim_ticks 79147317000 # Number of ticks simulated -final_tick 79147317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.079190 # Number of seconds simulated +sim_ticks 79190347500 # Number of ticks simulated +final_tick 79190347500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70947 # Simulator instruction rate (inst/s) -host_op_rate 118914 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42517019 # Simulator tick rate (ticks/s) -host_mem_usage 343896 # Number of bytes of host memory used -host_seconds 1861.54 # Real time elapsed on the host +host_inst_rate 91850 # Simulator instruction rate (inst/s) +host_op_rate 153949 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55073733 # Simulator tick rate (ticks/s) +host_mem_usage 350132 # Number of bytes of host memory used +host_seconds 1437.90 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124928 # Number of bytes read from this memory -system.physmem.bytes_read::total 346304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221376 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3459 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1952 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5411 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2797012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1578424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4375436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2797012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2797012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2797012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1578424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4375436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5413 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125120 # Number of bytes read from this memory +system.physmem.bytes_read::total 345920 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1955 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5405 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2788219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1579991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4368209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2788219 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2788219 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2788219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1579991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4368209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5405 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5413 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5405 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 346304 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 345920 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 346432 # Total read bytes from the system interface side +system.physmem.bytesReadSys 345920 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 303 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 296 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 299 # Per bank write bursts -system.physmem.perBankRdBursts::1 344 # Per bank write bursts +system.physmem.perBankRdBursts::1 345 # Per bank write bursts system.physmem.perBankRdBursts::2 461 # Per bank write bursts -system.physmem.perBankRdBursts::3 354 # Per bank write bursts -system.physmem.perBankRdBursts::4 343 # Per bank write bursts -system.physmem.perBankRdBursts::5 326 # Per bank write bursts -system.physmem.perBankRdBursts::6 401 # Per bank write bursts -system.physmem.perBankRdBursts::7 385 # Per bank write bursts -system.physmem.perBankRdBursts::8 338 # Per bank write bursts +system.physmem.perBankRdBursts::3 350 # Per bank write bursts +system.physmem.perBankRdBursts::4 340 # Per bank write bursts +system.physmem.perBankRdBursts::5 325 # Per bank write bursts +system.physmem.perBankRdBursts::6 403 # Per bank write bursts +system.physmem.perBankRdBursts::7 384 # Per bank write bursts +system.physmem.perBankRdBursts::8 342 # Per bank write bursts system.physmem.perBankRdBursts::9 281 # Per bank write bursts -system.physmem.perBankRdBursts::10 237 # Per bank write bursts -system.physmem.perBankRdBursts::11 285 # Per bank write bursts -system.physmem.perBankRdBursts::12 221 # Per bank write bursts -system.physmem.perBankRdBursts::13 466 # Per bank write bursts -system.physmem.perBankRdBursts::14 386 # Per bank write bursts -system.physmem.perBankRdBursts::15 284 # Per bank write bursts +system.physmem.perBankRdBursts::10 239 # Per bank write bursts +system.physmem.perBankRdBursts::11 284 # Per bank write bursts +system.physmem.perBankRdBursts::12 217 # Per bank write bursts +system.physmem.perBankRdBursts::13 467 # Per bank write bursts +system.physmem.perBankRdBursts::14 385 # Per bank write bursts +system.physmem.perBankRdBursts::15 283 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 79147284500 # Total gap between requests +system.physmem.totGap 79190259000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5413 # Read request sizes (log2) +system.physmem.readPktSize::6 5405 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,313 +186,313 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1109 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 312.266907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.102740 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.449427 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 425 38.32% 38.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 245 22.09% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 103 9.29% 69.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 58 5.23% 74.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 62 5.59% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 52 4.69% 85.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24 2.16% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 18 1.62% 89.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 122 11.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1109 # Bytes accessed per row activation -system.physmem.totQLat 39588000 # Total ticks spent queuing -system.physmem.totMemAccLat 141044250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 27055000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7313.50 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 4998.15 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26056.58 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.bytesPerActivate::samples 1097 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 314.107566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.474477 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.278271 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 419 38.20% 38.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 241 21.97% 60.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 97 8.84% 69.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 63 5.74% 74.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 63 5.74% 80.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 54 4.92% 85.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 22 2.01% 87.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17 1.55% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 121 11.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1097 # Bytes accessed per row activation +system.physmem.totQLat 39419500 # Total ticks spent queuing +system.physmem.totMemAccLat 140763250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 27025000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7293.15 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26043.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.37 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.32 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4302 # Number of row buffer hits during reads +system.physmem.readRowHits 4299 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 14621704.14 # Average gap between requests -system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4951800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2701875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 22721400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 14651296.76 # Average gap between requests +system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4883760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2664750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 22565400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5169512400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2476092825 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 45316483500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 52992463800 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.540663 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 75384383500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2642640000 # Time in different power states +system.physmem_0.refreshEnergy 5172055200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2473079805 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 45342485250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 53017734165 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.530615 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 75427842500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2644200000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1120221500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1114667500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3432240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1872750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19484400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3402000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1856250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19305000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5169512400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2281510215 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 45487170000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 52962982005 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.168172 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 75669637750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2642640000 # Time in different power states +system.physmem_1.refreshEnergy 5172055200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2272318965 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 45518583000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 52987520415 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.149179 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 75723788000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2644200000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 834967250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 820354000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20588400 # Number of BP lookups -system.cpu.branchPred.condPredicted 20588400 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1327971 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12696525 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12013993 # Number of BTB hits +system.cpu.branchPred.lookups 20589195 # Number of BP lookups +system.cpu.branchPred.condPredicted 20589195 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1327817 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12690862 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12013274 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.624261 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1440282 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 16776 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.660820 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1440361 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 16897 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 158294635 # number of cpu cycles simulated +system.cpu.numCycles 158380696 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25247816 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227405263 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20588400 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13454275 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 131222766 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3194613 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 1919 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 20727 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 25245702 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227408017 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20589195 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13453635 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 131309354 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3192879 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 16 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 1952 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 21042 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24255799 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 267811 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 158090598 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.379045 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.324681 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 24254364 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 267325 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 158174565 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.377629 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.324169 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95773120 60.58% 60.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4766421 3.01% 63.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3796193 2.40% 66.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4366321 2.76% 68.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4228924 2.68% 71.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4813507 3.04% 74.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4702194 2.97% 77.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3700875 2.34% 79.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31943043 20.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95855369 60.60% 60.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4772394 3.02% 63.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3794325 2.40% 66.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4370382 2.76% 68.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4226374 2.67% 71.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4818979 3.05% 74.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4692035 2.97% 77.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3702011 2.34% 79.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31942696 20.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 158090598 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.130064 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.436595 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15405711 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96196393 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 23270128 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21621060 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1597306 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336557336 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1597306 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 23296942 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 31816084 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 30705 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35988234 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 65361327 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 328199746 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1272 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 57739687 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7687780 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 164697 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 380395487 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 909798638 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 600491080 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4191135 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 158174565 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.129998 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.435832 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15399565 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96291119 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 23261573 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21625869 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1596439 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336537122 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1596439 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 23302832 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 31798352 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 30486 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35975056 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 65471400 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 328175182 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1530 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 57810134 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7763747 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 166308 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 380366291 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 909731361 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 600445935 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4186121 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 120966037 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1948 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1925 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121028118 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 82726275 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 29782185 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59498195 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 20364114 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 317775977 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4062 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 259339716 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 70716 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 96416655 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 197093622 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2817 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 158090598 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.640450 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.524161 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 120936841 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1921 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1898 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 121141633 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 82738842 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 29779777 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59550134 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 20391789 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 317761802 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 259358612 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 72184 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 96402487 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 196983368 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 158174565 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.639699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523293 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40031018 25.32% 25.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 47550925 30.08% 55.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33058238 20.91% 76.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17999758 11.39% 87.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10966409 6.94% 94.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4755401 3.01% 97.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2459487 1.56% 99.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 881418 0.56% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 387944 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40029224 25.31% 25.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 47620381 30.11% 55.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33114320 20.94% 76.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17999452 11.38% 87.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10926984 6.91% 94.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4757371 3.01% 97.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2459469 1.55% 99.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 879282 0.56% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 388082 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 158090598 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 158174565 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 232409 7.35% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2543467 80.43% 87.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 386453 12.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 231613 7.32% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2544922 80.40% 87.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 388680 12.28% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1213129 0.47% 0.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 161789317 62.39% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 789379 0.30% 63.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7038032 2.71% 65.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1187047 0.46% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 64866508 25.01% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22456304 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1213055 0.47% 0.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 161788642 62.38% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 789415 0.30% 63.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7038152 2.71% 65.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1187589 0.46% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 64884960 25.02% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22456799 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 259339716 # Type of FU issued -system.cpu.iq.rate 1.638335 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3162329 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012194 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 675146049 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 410783686 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 253609186 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4857026 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3709843 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2340813 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 258843472 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2445444 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18733712 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 259358612 # Type of FU issued +system.cpu.iq.rate 1.637565 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3165215 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012204 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 675270057 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 410763185 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 253622616 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4859131 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3700913 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2341090 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 258863930 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2446842 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18717155 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26076688 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12661 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 303068 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9266468 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26089255 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 12841 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 302099 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9264060 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50753 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 50731 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 43 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1597306 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12475143 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 492608 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 317780039 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 92128 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 82726275 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 29782185 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1904 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 385254 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 64210 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 303068 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 551876 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 825683 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1377559 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 257278299 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64049933 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2061417 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1596439 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12482349 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 492760 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 317765871 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 91851 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 82738842 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 29779777 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1874 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 386744 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 63788 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 302099 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 551455 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 825732 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1377187 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 257295592 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64068122 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2063020 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 86328991 # number of memory reference insts executed -system.cpu.iew.exec_branches 14325599 # Number of branches executed -system.cpu.iew.exec_stores 22279058 # Number of stores executed -system.cpu.iew.exec_rate 1.625313 # Inst execution rate -system.cpu.iew.wb_sent 256636877 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 255949999 # cumulative count of insts written-back -system.cpu.iew.wb_producers 204329368 # num instructions producing a value -system.cpu.iew.wb_consumers 369642243 # num instructions consuming a value +system.cpu.iew.exec_refs 86346654 # number of memory reference insts executed +system.cpu.iew.exec_branches 14327856 # Number of branches executed +system.cpu.iew.exec_stores 22278532 # Number of stores executed +system.cpu.iew.exec_rate 1.624539 # Inst execution rate +system.cpu.iew.wb_sent 256649039 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 255963706 # cumulative count of insts written-back +system.cpu.iew.wb_producers 204348842 # num instructions producing a value +system.cpu.iew.wb_consumers 369627181 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.616922 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.552776 # average fanout of values written-back +system.cpu.iew.wb_rate 1.616129 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.552851 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 96424533 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 96410316 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1329745 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 144946815 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.527204 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.957309 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1329636 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 145035845 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.526267 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.955883 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 45502245 31.39% 31.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57364882 39.58% 70.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14168547 9.77% 80.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11990061 8.27% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4061557 2.80% 91.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2847156 1.96% 93.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 903972 0.62% 94.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1081775 0.75% 95.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7026620 4.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 45546155 31.40% 31.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57399506 39.58% 70.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14176238 9.77% 80.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11993202 8.27% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4061532 2.80% 91.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2861406 1.97% 93.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 912773 0.63% 94.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1078264 0.74% 95.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7006769 4.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 144946815 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 145035845 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -538,75 +538,75 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 7026620 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 455708112 # The number of ROB reads -system.cpu.rob.rob_writes 648756933 # The number of ROB writes -system.cpu.timesIdled 2654 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 204037 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 7006769 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 455802776 # The number of ROB reads +system.cpu.rob.rob_writes 648723400 # The number of ROB writes +system.cpu.timesIdled 2658 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 206131 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.198555 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.198555 # CPI: Total CPI of All Threads -system.cpu.ipc 0.834338 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.834338 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 448462774 # number of integer regfile reads -system.cpu.int_regfile_writes 232558570 # number of integer regfile writes -system.cpu.fp_regfile_reads 3214394 # number of floating regfile reads -system.cpu.fp_regfile_writes 1998880 # number of floating regfile writes -system.cpu.cc_regfile_reads 102524460 # number of cc regfile reads -system.cpu.cc_regfile_writes 59518831 # number of cc regfile writes -system.cpu.misc_regfile_reads 132416718 # number of misc regfile reads +system.cpu.cpi 1.199207 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.199207 # CPI: Total CPI of All Threads +system.cpu.ipc 0.833884 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.833884 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 448507967 # number of integer regfile reads +system.cpu.int_regfile_writes 232568909 # number of integer regfile writes +system.cpu.fp_regfile_reads 3215393 # number of floating regfile reads +system.cpu.fp_regfile_writes 1999198 # number of floating regfile writes +system.cpu.cc_regfile_reads 102530516 # number of cc regfile reads +system.cpu.cc_regfile_writes 59523273 # number of cc regfile writes +system.cpu.misc_regfile_reads 132435302 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.replacements 53 # number of replacements -system.cpu.dcache.tags.tagsinuse 1431.895248 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 65702088 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1996 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32916.877756 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 52 # number of replacements +system.cpu.dcache.tags.tagsinuse 1432.092422 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 65736813 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2001 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32851.980510 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1431.895248 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.349584 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.349584 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1943 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1432.092422 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.349632 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.349632 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1949 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 500 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1395 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.474365 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 131411014 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 131411014 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 45187780 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45187780 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513887 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513887 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 65701667 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 65701667 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 65701667 # number of overall hits -system.cpu.dcache.overall_hits::total 65701667 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 998 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 998 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1844 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1844 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2842 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2842 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2842 # number of overall misses -system.cpu.dcache.overall_misses::total 2842 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65947500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65947500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129226000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129226000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 195173500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 195173500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 195173500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 195173500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45188778 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45188778 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.475830 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 131480483 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 131480483 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 45222500 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45222500 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513893 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513893 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 65736393 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 65736393 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 65736393 # number of overall hits +system.cpu.dcache.overall_hits::total 65736393 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1010 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1010 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1838 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1838 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2848 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2848 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2848 # number of overall misses +system.cpu.dcache.overall_misses::total 2848 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65396000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65396000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129164500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129164500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 194560500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 194560500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 194560500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 194560500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45223510 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45223510 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 65704509 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 65704509 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 65704509 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 65704509 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 65739241 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 65739241 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 65739241 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 65739241 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses @@ -615,262 +615,262 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66079.659319 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66079.659319 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70079.175705 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70079.175705 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 68674.700915 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 68674.700915 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 68674.700915 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 68674.700915 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64748.514851 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64748.514851 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70274.483134 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70274.483134 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 68314.782303 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68314.782303 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 68314.782303 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68314.782303 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 697 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 93.714286 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.125000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 12 # number of writebacks -system.cpu.dcache.writebacks::total 12 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 541 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 541 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 10 # number of writebacks +system.cpu.dcache.writebacks::total 10 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 549 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 549 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 543 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 543 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 543 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 543 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 457 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 457 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1842 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1842 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2299 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2299 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2299 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2299 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36552500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36552500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127238000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 127238000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163790500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 163790500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163790500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 163790500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 551 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 551 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 551 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 551 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 461 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 461 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1836 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1836 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2297 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2297 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2297 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2297 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36137000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36137000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127182500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 127182500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163319500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 163319500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163319500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 163319500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000090 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000090 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79983.588621 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79983.588621 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69076.004343 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69076.004343 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71244.236625 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71244.236625 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71244.236625 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71244.236625 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78388.286334 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78388.286334 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69271.514161 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69271.514161 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71101.218981 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71101.218981 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71101.218981 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71101.218981 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5044 # number of replacements -system.cpu.icache.tags.tagsinuse 1638.951309 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24246301 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 7022 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3452.905298 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4970 # number of replacements +system.cpu.icache.tags.tagsinuse 1639.175035 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24244955 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6947 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3489.989204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1638.951309 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.800269 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.800269 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 874 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 48518920 # Number of tag accesses -system.cpu.icache.tags.data_accesses 48518920 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24246303 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24246303 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24246303 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24246303 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24246303 # number of overall hits -system.cpu.icache.overall_hits::total 24246303 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9495 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9495 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9495 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9495 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9495 # number of overall misses -system.cpu.icache.overall_misses::total 9495 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 408233999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 408233999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 408233999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 408233999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 408233999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 408233999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24255798 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24255798 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24255798 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24255798 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24255798 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24255798 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000391 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000391 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000391 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000391 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000391 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000391 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 870 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 793 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.965332 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 48515969 # Number of tag accesses +system.cpu.icache.tags.data_accesses 48515969 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24244955 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24244955 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24244955 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24244955 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24244955 # 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average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73089.073634 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65732.975949 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66710.741688 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66086.570477 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65732.975949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66710.741688 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66086.570477 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 7781 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 4947 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 303 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 303 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7327 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 457 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19253 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4650 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23903 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 449216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 577728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 305 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 14723 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 14563 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5344 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 7704 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 4875 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1540 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1540 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7244 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 461 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19022 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4645 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23667 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 444416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 573120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 299 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 14563 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.061251 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.239799 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 14723 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 13671 93.87% 93.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 892 6.13% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 14723 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7373500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 14563 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7291500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10986000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10864500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3145500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3149999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3877 # Transaction distribution -system.membus.trans_dist::UpgradeReq 303 # Transaction distribution -system.membus.trans_dist::UpgradeResp 303 # Transaction distribution +system.membus.trans_dist::ReadResp 3871 # Transaction distribution +system.membus.trans_dist::UpgradeReq 296 # Transaction distribution +system.membus.trans_dist::UpgradeResp 296 # Transaction distribution system.membus.trans_dist::ReadExReq 1534 # Transaction distribution system.membus.trans_dist::ReadExResp 1534 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3879 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11430 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11430 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11430 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 346304 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 346304 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 346304 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3871 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11402 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11402 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11402 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 345920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 345920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 345920 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5716 # Request fanout histogram +system.membus.snoop_fanout::samples 5701 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5716 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5701 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5716 # Request fanout histogram -system.membus.reqLayer0.occupancy 7099000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5701 # Request fanout histogram +system.membus.reqLayer0.occupancy 6922500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 29276697 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 29231454 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |