diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/se | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/se')
54 files changed, 20390 insertions, 20428 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 4f1cfb81e..2c11d0b34 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061494 # Number of seconds simulated -sim_ticks 61493732000 # Number of ticks simulated -final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061593 # Number of seconds simulated +sim_ticks 61592600500 # Number of ticks simulated +final_tick 61592600500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 144123 # Simulator instruction rate (inst/s) -host_op_rate 144840 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 97818525 # Simulator tick rate (ticks/s) -host_mem_usage 433504 # Number of bytes of host memory used -host_seconds 628.65 # Real time elapsed on the host +host_inst_rate 271325 # Simulator instruction rate (inst/s) +host_op_rate 272676 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 184448880 # Simulator tick rate (ticks/s) +host_mem_usage 445184 # Number of bytes of host memory used +host_seconds 333.93 # Real time elapsed on the host sim_insts 90602849 # Number of instructions simulated sim_ops 91054080 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 49600 # Nu system.physmem.num_reads::cpu.inst 775 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 806586 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15403196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16209782 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 806586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 806586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 806586 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15403196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 16209782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 805292 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15378471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16183762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 805292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 805292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 805292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15378471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16183762 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15575 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61493643500 # Total gap between requests +system.physmem.totGap 61592506000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 15453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1534 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 648.594524 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 444.741065 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 399.329877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 241 15.71% 15.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 178 11.60% 27.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 90 5.87% 33.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 63 4.11% 37.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 79 5.15% 42.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 102 6.65% 49.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 37 2.41% 51.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 39 2.54% 54.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 705 45.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1534 # Bytes accessed per row activation -system.physmem.totQLat 73247750 # Total ticks spent queuing -system.physmem.totMemAccLat 365279000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 642.644287 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 437.986910 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 400.933627 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 248 16.01% 16.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 186 12.01% 28.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 90 5.81% 33.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 71 4.58% 38.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 77 4.97% 43.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 93 6.00% 49.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 43 2.78% 52.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 36 2.32% 54.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 705 45.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation +system.physmem.totQLat 77242000 # Total ticks spent queuing +system.physmem.totMemAccLat 369273250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4702.91 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4959.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23452.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 16.21 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23709.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 16.21 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.13 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14031 # Number of row buffer hits during reads +system.physmem.readRowHits 14018 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.00 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 3948227.51 # Average gap between requests -system.physmem.pageHitRate 90.09 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6320160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3448500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 63663600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 3954575.02 # Average gap between requests +system.physmem.pageHitRate 90.00 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6373080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3477375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 63718200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2490640650 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34708185000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41288356230 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.483541 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57732029500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2053220000 # Time in different power states +system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2539008855 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34726497750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41361784860 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.572046 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57760380750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1704707500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1772530500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5261760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2871000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5329800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2908125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57478200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2514095865 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34687610250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41283399795 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.402933 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57698939250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2053220000 # Time in different power states +system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2571546735 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34697955750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41357928210 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.509428 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57713961000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1738589750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1819631500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20789429 # Number of BP lookups -system.cpu.branchPred.condPredicted 17091399 # Number of conditional branches predicted +system.cpu.branchPred.lookups 20789446 # Number of BP lookups +system.cpu.branchPred.condPredicted 17091418 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8973618 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8867020 # Number of BTB hits +system.cpu.branchPred.BTBLookups 8973614 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8867024 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.812096 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 62716 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 98.812184 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 62715 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,89 +377,89 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 122987464 # number of cpu cycles simulated +system.cpu.numCycles 123185201 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602849 # Number of instructions committed system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2068195 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2068247 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.357435 # CPI: cycles per instruction -system.cpu.ipc 0.736684 # IPC: instructions per cycle -system.cpu.tickCycles 109826570 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13160894 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.359617 # CPI: cycles per instruction +system.cpu.ipc 0.735501 # IPC: instructions per cycle +system.cpu.tickCycles 109827605 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13357596 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 946107 # number of replacements -system.cpu.dcache.tags.tagsinuse 3616.604238 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26267660 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3616.143974 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26267423 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.644261 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20617906250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3616.604238 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.882960 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.882960 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 27.644012 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20661192250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.143974 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.882848 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.882848 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 262 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2249 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1585 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 252 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55463255 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55463255 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21598813 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21598813 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4661073 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4661073 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55463259 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55463259 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21598839 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21598839 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660810 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660810 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26259886 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26259886 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26259886 # number of overall hits -system.cpu.dcache.overall_hits::total 26259886 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 914958 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 914958 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 73908 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 73908 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 988866 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 988866 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 988866 # number of overall misses -system.cpu.dcache.overall_misses::total 988866 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11910296994 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11910296994 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2345727500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2345727500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14256024494 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14256024494 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14256024494 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14256024494 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22513771 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22513771 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 26259649 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26259649 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26259649 # number of overall hits +system.cpu.dcache.overall_hits::total 26259649 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 914934 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 914934 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74171 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74171 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 989105 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 989105 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 989105 # number of overall misses +system.cpu.dcache.overall_misses::total 989105 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918412494 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11918412494 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2568231500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2568231500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14486643994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14486643994 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14486643994 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14486643994 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22513773 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22513773 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27248752 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27248752 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27248752 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27248752 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040640 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015609 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015609 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036290 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036290 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13017.315542 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.315542 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31738.478920 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.478920 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14416.538231 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14416.538231 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14416.538231 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14416.538231 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 27248754 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27248754 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27248754 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27248754 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015664 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015664 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036299 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036299 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.527043 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.527043 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34625.817368 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34625.817368 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14646.214501 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14646.214501 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14646.214501 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14646.214501 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,14 +470,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 943286 # number of writebacks system.cpu.dcache.writebacks::total 943286 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11523 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 11523 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27140 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27140 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38663 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38663 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38663 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38663 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11499 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11499 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27403 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27403 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 38902 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 38902 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 38902 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 38902 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903435 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46768 # number of WriteReq MSHR misses @@ -486,14 +486,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950203 system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950203 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9958855506 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958855506 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1333449750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333449750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11292305256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11292305256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11292305256 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11292305256 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10413322256 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10413322256 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464464500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464464500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11877786756 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11877786756 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877786756 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11877786756 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses @@ -502,67 +502,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11023.322659 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.322659 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28512.011418 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28512.011418 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11884.097668 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11884.097668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.365766 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.365766 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31313.387359 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31313.387359 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12500.262319 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12500.262319 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12500.262319 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12500.262319 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 690.411182 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27857009 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 690.370829 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27857028 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34691.169365 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34691.193026 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 690.411182 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.337115 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.337115 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 690.370829 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.337095 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.337095 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55716427 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55716427 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27857009 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27857009 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27857009 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27857009 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27857009 # number of overall hits -system.cpu.icache.overall_hits::total 27857009 # number of overall hits +system.cpu.icache.tags.tag_accesses 55716465 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55716465 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27857028 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27857028 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27857028 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27857028 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27857028 # number of overall hits +system.cpu.icache.overall_hits::total 27857028 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses system.cpu.icache.overall_misses::total 803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 55346748 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 55346748 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 55346748 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 55346748 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 55346748 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 55346748 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27857812 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27857812 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27857812 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27857812 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27857812 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27857812 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 61138997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 61138997 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 61138997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 61138997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 61138997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 61138997 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27857831 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27857831 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27857831 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27857831 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27857831 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27857831 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68924.966376 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68924.966376 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68924.966376 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68924.966376 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76138.227895 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76138.227895 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76138.227895 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76138.227895 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76138.227895 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76138.227895 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -577,38 +577,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 803 system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53408252 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 53408252 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53408252 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 53408252 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53408252 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 53408252 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59598503 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59598503 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59598503 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59598503 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59598503 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59598503 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66510.899128 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66510.899128 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74219.804483 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74219.804483 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74219.804483 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74219.804483 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74219.804483 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74219.804483 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10247.121902 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1831334 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10238.643668 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1831333 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 117.710117 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 117.710053 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236608 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.415381 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 215.469913 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.285530 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020612 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006576 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.312717 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 9347.860585 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.375683 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.407400 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.285274 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020611 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006574 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.312459 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id @@ -618,41 +618,41 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15216662 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15216662 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 903173 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903199 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 903198 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 943286 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 943286 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32224 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32224 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 935397 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 935423 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits +system.cpu.l2cache.demand_hits::total 935422 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 935397 # number of overall hits -system.cpu.l2cache.overall_hits::total 935423 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 777 # number of ReadReq misses +system.cpu.l2cache.overall_hits::total 935422 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 778 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 262 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1040 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 777 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 778 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 777 # number of overall misses +system.cpu.l2cache.demand_misses::total 15584 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 778 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses -system.cpu.l2cache.overall_misses::total 15583 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 52344250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19360000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71704250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 958084250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 958084250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 52344250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 977444250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1029788500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 52344250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 977444250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1029788500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::total 15584 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58533000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22267750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 80800750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073909000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1073909000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 58533000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1096176750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1154709750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 58533000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1096176750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1154709750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 803 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 903435 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses) @@ -666,28 +666,28 @@ system.cpu.l2cache.demand_accesses::total 951006 # n system.cpu.l2cache.overall_accesses::cpu.inst 803 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 950203 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967621 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968867 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001150 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310982 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967621 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968867 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967621 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.016387 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968867 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67367.117117 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73893.129771 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69012.752647 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65874.879675 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65874.879675 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67367.117117 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66016.766851 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66084.098056 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67367.117117 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66016.766851 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66084.098056 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.016387 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75235.218509 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84991.412214 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77693.028846 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73838.627613 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73838.627613 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75235.218509 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74035.982034 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74095.851514 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75235.218509 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74035.982034 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74095.851514 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -696,15 +696,15 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 1031 # number of ReadReq MSHR misses @@ -716,17 +716,17 @@ system.cpu.l2cache.demand_mshr_misses::total 15575 system.cpu.l2cache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42469000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15862000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58331000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 774515250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774515250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42469000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 790377250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 832846250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42469000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 790377250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 832846250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48659000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18669250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 67328250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 892098500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 892098500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48659000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910767750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 959426750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48659000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910767750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 959426750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses @@ -738,17 +738,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.709677 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61960.937500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56577.109602 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53253.248762 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53253.248762 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54798.709677 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53403.868243 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54798.709677 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53403.868243 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62785.806452 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72926.757812 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65303.831232 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61337.905666 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61337.905666 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62785.806452 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61538.361486 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61600.433387 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62785.806452 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61538.361486 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61600.433387 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution @@ -763,25 +763,23 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1894292 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 1894292 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 1894292 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1894292 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1370748 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1372497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1428672244 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1428682244 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.membus.trans_dist::ReadReq 1031 # Transaction distribution system.membus.trans_dist::ReadResp 1031 # Transaction distribution @@ -802,9 +800,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15575 # Request fanout histogram -system.membus.reqLayer0.occupancy 17956500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21632500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 146201750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 82148250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index ea993d96c..8fe6f61b1 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057719 # Number of seconds simulated -sim_ticks 57719377000 # Number of ticks simulated -final_tick 57719377000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058203 # Number of seconds simulated +sim_ticks 58202727500 # Number of ticks simulated +final_tick 58202727500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125223 # Simulator instruction rate (inst/s) -host_op_rate 125847 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79786059 # Simulator tick rate (ticks/s) -host_mem_usage 443544 # Number of bytes of host memory used -host_seconds 723.43 # Real time elapsed on the host +host_inst_rate 129726 # Simulator instruction rate (inst/s) +host_op_rate 130372 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83346935 # Simulator tick rate (ticks/s) +host_mem_usage 443628 # Number of bytes of host memory used +host_seconds 698.32 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91041029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 44416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 43648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 927744 # Number of bytes read from this memory -system.physmem.bytes_read::total 1015808 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 19776 # Number of bytes written to this memory -system.physmem.bytes_written::total 19776 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 694 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 682 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14496 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15872 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 309 # Number of write requests responded to by this memory -system.physmem.num_writes::total 309 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 769516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 756211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 16073354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17599081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 769516 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 769516 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 342623 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 342623 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 342623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 769516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 756211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 16073354 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17941704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15872 # Number of read requests accepted -system.physmem.writeReqs 309 # Number of write requests accepted -system.physmem.readBursts 15872 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 309 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1006016 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue -system.physmem.bytesWritten 18432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1015808 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 19776 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 44480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 45376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 930112 # Number of bytes read from this memory +system.physmem.bytes_read::total 1019968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44480 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 22912 # Number of bytes written to this memory +system.physmem.bytes_written::total 22912 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 695 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 709 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14533 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15937 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 358 # Number of write requests responded to by this memory +system.physmem.num_writes::total 358 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 764225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 779620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15980557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17524402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 764225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 764225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 393659 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 393659 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 393659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 764225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 779620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15980557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17918061 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15937 # Number of read requests accepted +system.physmem.writeReqs 358 # Number of write requests accepted +system.physmem.readBursts 15937 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 358 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1010432 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue +system.physmem.bytesWritten 21184 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1019968 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 22912 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 999 # Per bank write bursts +system.physmem.perBankRdBursts::0 1009 # Per bank write bursts system.physmem.perBankRdBursts::1 876 # Per bank write bursts -system.physmem.perBankRdBursts::2 956 # Per bank write bursts -system.physmem.perBankRdBursts::3 1023 # Per bank write bursts +system.physmem.perBankRdBursts::2 958 # Per bank write bursts +system.physmem.perBankRdBursts::3 1024 # Per bank write bursts system.physmem.perBankRdBursts::4 1064 # Per bank write bursts -system.physmem.perBankRdBursts::5 1127 # Per bank write bursts -system.physmem.perBankRdBursts::6 1115 # Per bank write bursts -system.physmem.perBankRdBursts::7 1101 # Per bank write bursts -system.physmem.perBankRdBursts::8 1033 # Per bank write bursts +system.physmem.perBankRdBursts::5 1132 # Per bank write bursts +system.physmem.perBankRdBursts::6 1124 # Per bank write bursts +system.physmem.perBankRdBursts::7 1103 # Per bank write bursts +system.physmem.perBankRdBursts::8 1046 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts system.physmem.perBankRdBursts::10 937 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 910 # Per bank write bursts -system.physmem.perBankRdBursts::13 886 # Per bank write bursts -system.physmem.perBankRdBursts::14 919 # Per bank write bursts -system.physmem.perBankRdBursts::15 912 # Per bank write bursts -system.physmem.perBankWrBursts::0 23 # Per bank write bursts +system.physmem.perBankRdBursts::12 909 # Per bank write bursts +system.physmem.perBankRdBursts::13 889 # Per bank write bursts +system.physmem.perBankRdBursts::14 926 # Per bank write bursts +system.physmem.perBankRdBursts::15 930 # Per bank write bursts +system.physmem.perBankWrBursts::0 30 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 4 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 9 # Per bank write bursts +system.physmem.perBankWrBursts::2 8 # Per bank write bursts +system.physmem.perBankWrBursts::3 1 # Per bank write bursts +system.physmem.perBankWrBursts::4 10 # Per bank write bursts system.physmem.perBankWrBursts::5 29 # Per bank write bursts -system.physmem.perBankWrBursts::6 62 # Per bank write bursts -system.physmem.perBankWrBursts::7 30 # Per bank write bursts -system.physmem.perBankWrBursts::8 15 # Per bank write bursts +system.physmem.perBankWrBursts::6 69 # Per bank write bursts +system.physmem.perBankWrBursts::7 31 # Per bank write bursts +system.physmem.perBankWrBursts::8 36 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 10 # Per bank write bursts -system.physmem.perBankWrBursts::11 1 # Per bank write bursts -system.physmem.perBankWrBursts::12 9 # Per bank write bursts +system.physmem.perBankWrBursts::10 7 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 7 # Per bank write bursts system.physmem.perBankWrBursts::13 27 # Per bank write bursts -system.physmem.perBankWrBursts::14 48 # Per bank write bursts -system.physmem.perBankWrBursts::15 21 # Per bank write bursts +system.physmem.perBankWrBursts::14 45 # Per bank write bursts +system.physmem.perBankWrBursts::15 31 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57719226000 # Total gap between requests +system.physmem.totGap 58202569500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15872 # Read request sizes (log2) +system.physmem.readPktSize::6 15937 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 309 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2671 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 358 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 10945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 305 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 289 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see @@ -148,24 +148,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -197,95 +197,94 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1739 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 588.402530 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 354.168959 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 429.121053 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 443 25.47% 25.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 194 11.16% 36.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 91 5.23% 41.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 64 3.68% 45.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 57 3.28% 48.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 43 2.47% 51.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 46 2.65% 53.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 54 3.11% 57.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 747 42.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1739 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 16 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 981 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 40.634826 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3762.941438 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 15 93.75% 93.75% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 6.25% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 16 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 16 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.975187 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.966092 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2 12.50% 12.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 11 68.75% 81.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 12.50% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 6.25% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 16 # Writes before turning the bus around for reads -system.physmem.totQLat 179464908 # Total ticks spent queuing -system.physmem.totMemAccLat 474196158 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78595000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11417.07 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1871 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 551.268840 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 315.885566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 433.770323 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 552 29.50% 29.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 218 11.65% 41.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 92 4.92% 46.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 3.05% 49.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 63 3.37% 52.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 44 2.35% 54.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 55 2.94% 57.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 42 2.24% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 748 39.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1871 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 18 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 874.777778 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 39.760140 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3541.219224 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 17 94.44% 94.44% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 5.56% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 18 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 18 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.388889 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.356746 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.195033 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 15 83.33% 83.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 11.11% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 5.56% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 18 # Writes before turning the bus around for reads +system.physmem.totQLat 172783990 # Total ticks spent queuing +system.physmem.totMemAccLat 468808990 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78940000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10944.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30167.07 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 17.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.32 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 17.60 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.34 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29694.01 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 17.36 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 17.52 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.39 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.97 # Average write queue length when enqueuing -system.physmem.readRowHits 14166 # Number of row buffer hits during reads -system.physmem.writeRowHits 92 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.97 # Row buffer hit rate for writes -system.physmem.avgGap 3567098.82 # Average gap between requests -system.physmem.pageHitRate 88.97 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7053480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3848625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 64162800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 959040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2338304445 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32576022750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 38759797860 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.607894 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 54183699610 # Time in different power states -system.physmem_0.memoryStateTime::REF 1927120000 # Time in different power states +system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 16.15 # Average write queue length when enqueuing +system.physmem.readRowHits 14154 # Number of row buffer hits during reads +system.physmem.writeRowHits 93 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 26.20 # Row buffer hit rate for writes +system.physmem.avgGap 3571805.43 # Average gap between requests +system.physmem.pageHitRate 88.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7658280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 4178625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 64638600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1153440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2451888630 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32770707750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39101711325 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.822097 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54506616189 # Time in different power states +system.physmem_0.memoryStateTime::REF 1943500000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1601139140 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1752376311 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6002640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3275250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 58133400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 803520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2319744105 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32592295500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 38749701135 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.433104 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54217128450 # Time in different power states -system.physmem_1.memoryStateTime::REF 1927120000 # Time in different power states +system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 58484400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 991440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2431326735 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32788744500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39091058805 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.639072 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54537138662 # Time in different power states +system.physmem_1.memoryStateTime::REF 1943500000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1573598050 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1721853838 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 28271166 # Number of BP lookups -system.cpu.branchPred.condPredicted 23289258 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 837919 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11857915 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11789421 # Number of BTB hits +system.cpu.branchPred.lookups 28259323 # Number of BP lookups +system.cpu.branchPred.condPredicted 23281308 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 837964 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11850778 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11785443 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.422377 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 75707 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.448686 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 75758 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 89 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -404,83 +403,83 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 115438755 # number of cpu cycles simulated +system.cpu.numCycles 116405456 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 750677 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 135029605 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28271166 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11865128 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 113801477 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1679415 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1154 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 715 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32315558 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 576 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 115393730 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.175455 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.320715 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 749294 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134993998 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28259323 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11861201 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 114761716 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1679249 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1000 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 840 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32304088 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 579 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116352474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.165469 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.319047 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 57838402 50.12% 50.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13925125 12.07% 62.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9175651 7.95% 70.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34454552 29.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58780581 50.52% 50.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13944559 11.98% 62.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9221403 7.93% 70.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34405931 29.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 115393730 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.244902 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.169708 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8870766 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63114849 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33033969 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9546674 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 827472 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4101024 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12335 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114392732 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1987220 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 827472 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15224664 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49207626 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 108919 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35472493 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14552556 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110856042 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1413744 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11047079 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1056491 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1457150 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 456315 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129915292 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483076638 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119437218 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 116352474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.242766 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.159688 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8844184 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64087377 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33032699 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9560836 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 827378 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4101289 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12349 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114434840 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1995518 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 827378 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15306554 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49837632 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 110028 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35408205 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14862677 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110902804 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1415247 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11133046 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1143083 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1515709 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 570063 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129962368 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483290389 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119478713 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 424 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22602373 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22649449 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21217869 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26815015 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5348915 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 559856 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 297304 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109685726 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101429576 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1059441 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18455382 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41507392 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 115393730 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.878987 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.999963 # Number of insts issued each cycle +system.cpu.rename.skidInsts 21572068 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26814283 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5349560 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 615072 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 351208 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109694902 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8246 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 101389982 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1073881 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18465721 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41703174 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 116352474 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.871404 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.988585 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54518642 47.25% 47.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 30124755 26.11% 73.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22142664 19.19% 92.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7411500 6.42% 98.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1195852 1.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54656656 46.98% 46.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31447896 27.03% 74.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 21997479 18.91% 92.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7054961 6.06% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1195165 1.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -488,149 +487,149 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 115393730 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116352474 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9750384 48.86% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 50 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9494227 47.58% 96.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 710033 3.56% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9796147 48.71% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 50 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 12 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9605529 47.77% 96.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 708223 3.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71988081 70.97% 70.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10708 0.01% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 55 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24381590 24.04% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5049013 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71985557 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10710 0.01% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 58 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 123 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24344215 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5049315 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101429576 # Type of FU issued -system.cpu.iq.rate 0.878644 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19954707 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.196735 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 339266571 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128150140 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99658235 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 101389982 # Type of FU issued +system.cpu.iq.rate 0.871007 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20109961 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198343 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340315821 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128169527 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99626078 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 459 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 607 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 119 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121384044 # Number of integer alu accesses +system.cpu.iq.fp_inst_queue_writes 609 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121499704 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 285219 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 282708 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4339104 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1483 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1422 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 604071 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4338372 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1511 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1302 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 604716 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7565 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130466 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7561 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130367 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 827472 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8003638 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 730506 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109706640 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 827378 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8117043 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 661508 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109715814 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26815015 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5348915 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 187146 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 360894 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1422 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 436340 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412872 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 849212 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100146798 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23824665 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1282778 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26814283 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5349560 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4358 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 178487 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 319637 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1302 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 436579 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412967 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 849546 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100128293 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23807365 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1261689 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12667 # number of nop insts executed -system.cpu.iew.exec_refs 28743608 # number of memory reference insts executed -system.cpu.iew.exec_branches 20629236 # Number of branches executed -system.cpu.iew.exec_stores 4918943 # Number of stores executed -system.cpu.iew.exec_rate 0.867532 # Inst execution rate -system.cpu.iew.wb_sent 99756620 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99658354 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59706662 # num instructions producing a value -system.cpu.iew.wb_consumers 95558908 # num instructions consuming a value +system.cpu.iew.exec_nop 12666 # number of nop insts executed +system.cpu.iew.exec_refs 28725194 # number of memory reference insts executed +system.cpu.iew.exec_branches 20624883 # Number of branches executed +system.cpu.iew.exec_stores 4917829 # Number of stores executed +system.cpu.iew.exec_rate 0.860168 # Inst execution rate +system.cpu.iew.wb_sent 99711182 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99626193 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59706016 # num instructions producing a value +system.cpu.iew.wb_consumers 95562461 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.863301 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624815 # average fanout of values written-back +system.cpu.iew.wb_rate 0.855855 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624785 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 17391201 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 17390136 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 825684 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 112699801 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.807931 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.745752 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 825718 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113659456 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.801109 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.737097 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 76441556 67.83% 67.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18447200 16.37% 84.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7119761 6.32% 90.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3375676 3.00% 93.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1760831 1.56% 95.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 536786 0.48% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 726119 0.64% 96.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 179056 0.16% 96.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4112816 3.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77211009 67.93% 67.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18641585 16.40% 84.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7152887 6.29% 90.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3463018 3.05% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1652627 1.45% 95.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 524640 0.46% 95.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 723684 0.64% 96.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 178635 0.16% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4111371 3.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 112699801 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113659456 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -676,383 +675,383 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction -system.cpu.commit.bw_lim_events 4112816 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4111371 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 217026090 # The number of ROB reads -system.cpu.rob.rob_writes 219584249 # The number of ROB writes -system.cpu.timesIdled 586 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 45025 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 217986125 # The number of ROB reads +system.cpu.rob.rob_writes 219581178 # The number of ROB writes +system.cpu.timesIdled 584 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 52982 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.274302 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.274302 # CPI: Total CPI of All Threads -system.cpu.ipc 0.784743 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.784743 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108125012 # number of integer regfile reads -system.cpu.int_regfile_writes 58739124 # number of integer regfile writes +system.cpu.cpi 1.284973 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.284973 # CPI: Total CPI of All Threads +system.cpu.ipc 0.778226 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.778226 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108112973 # number of integer regfile reads +system.cpu.int_regfile_writes 58701982 # number of integer regfile writes system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 99 # number of floating regfile writes -system.cpu.cc_regfile_reads 369256929 # number of cc regfile reads -system.cpu.cc_regfile_writes 58699332 # number of cc regfile writes -system.cpu.misc_regfile_reads 28460693 # number of misc regfile reads +system.cpu.fp_regfile_writes 95 # number of floating regfile writes +system.cpu.cc_regfile_reads 369069288 # number of cc regfile reads +system.cpu.cc_regfile_writes 58692619 # number of cc regfile writes +system.cpu.misc_regfile_reads 28415446 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.replacements 5486247 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.800439 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18271247 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5486759 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.330062 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 33236000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.800439 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999610 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999610 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 5469543 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.788616 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18297454 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5470055 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.345022 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 35157000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.788616 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999587 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999587 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 342 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61970439 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61970439 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13905626 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13905626 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4357324 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4357324 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61924995 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61924995 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13934183 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13934183 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4354974 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4354974 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18262950 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18262950 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18263472 # number of overall hits -system.cpu.dcache.overall_hits::total 18263472 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9592929 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9592929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 377657 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 377657 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 8 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 8 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 18289157 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18289157 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18289679 # number of overall hits +system.cpu.dcache.overall_hits::total 18289679 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9550003 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9550003 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 380007 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 380007 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9970586 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9970586 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9970594 # number of overall misses -system.cpu.dcache.overall_misses::total 9970594 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 87008583027 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 87008583027 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3975903343 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3975903343 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 269500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 269500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90984486370 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90984486370 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90984486370 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90984486370 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23498555 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23498555 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9930010 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9930010 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9930017 # number of overall misses +system.cpu.dcache.overall_misses::total 9930017 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88443276736 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88443276736 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3962066244 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3962066244 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 297000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92405342980 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92405342980 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92405342980 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92405342980 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23484186 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23484186 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 530 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 530 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28233536 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28233536 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28234066 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28234066 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408235 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408235 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079759 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079759 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.015094 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.015094 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28219167 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28219167 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28219696 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28219696 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.406657 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.406657 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080255 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080255 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353147 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353147 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353141 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353141 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9070.074742 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9070.074742 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10527.815830 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10527.815830 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17966.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17966.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9125.289764 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9125.289764 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9125.282443 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9125.282443 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 301798 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 69284 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 120550 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12191 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.503509 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5.683209 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.351889 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.351889 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.351882 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.351882 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9261.073189 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9261.073189 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10426.298052 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10426.298052 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19800 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19800 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9305.664645 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9305.664645 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9305.658085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9305.658085 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 306020 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 36082 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 120709 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2278 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.535188 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15.839333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 5460017 # number of writebacks -system.cpu.dcache.writebacks::total 5460017 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328962 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4328962 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154868 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 154868 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 5439051 # number of writebacks +system.cpu.dcache.writebacks::total 5439051 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4313021 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4313021 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 146936 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 146936 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4483830 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4483830 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4483830 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4483830 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5263967 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5263967 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222789 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222789 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 5 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5486756 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5486756 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5486761 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5486761 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38199288241 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 38199288241 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2164503781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2164503781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 250500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 250500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40363792022 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 40363792022 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40364042522 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 40364042522 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047052 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047052 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.009434 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009434 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194335 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.194335 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7356.624887 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7356.624887 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 4459957 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4459957 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4459957 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4459957 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5236982 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5236982 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 233071 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 233071 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 5470053 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5470053 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5470057 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5470057 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40519086258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 40519086258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2295163471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2295163471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 213000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 213000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42814249729 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 42814249729 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42814462729 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 42814462729 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223000 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223000 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049223 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049223 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # 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Cycle average of tags in use +system.cpu.icache.tags.total_refs 32302915 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 910 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 35497.708791 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 428.924531 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.837743 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.837743 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 428.263511 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.836452 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.836452 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64631998 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64631998 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 32314402 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32314402 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32314402 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32314402 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32314402 # number of overall hits -system.cpu.icache.overall_hits::total 32314402 # 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number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1158 # number of overall misses +system.cpu.icache.overall_misses::total 1158 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62669987 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62669987 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62669987 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62669987 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62669987 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62669987 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32304073 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32304073 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32304073 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32304073 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54119.159758 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54119.159758 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54119.159758 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 19414 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 134 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 238 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 81.571429 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 26.800000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 238 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 238 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 238 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 238 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 238 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 238 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 906 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 906 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 906 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 906 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 906 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 44276742 # 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number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 910 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 910 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 910 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 910 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50368733 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50368733 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50368733 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50368733 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50368733 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50368733 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48870.576159 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48870.576159 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48870.576159 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48870.576159 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 214 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 973 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1059 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13108 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.014648 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927856 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 175404109 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 175404109 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 211 # 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Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 174809424 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 174809424 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 213 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 5236439 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5236652 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 5439051 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 5439051 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 232688 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 232688 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 213 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 5469127 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5469340 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 213 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000197 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 695 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 709 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1404 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 695 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 709 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 20246 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 21650 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42518507 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21103750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63622257 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 830590289 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 830590289 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27502 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27502 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 25988008 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 25988008 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42518507 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47091758 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 89610265 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42518507 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47091758 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 830590289 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 920200554 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000070 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000203 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000124 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000251 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000124 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001462 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001462 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000257 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.003937 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52643.371758 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47254.398827 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50867.874396 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38413.799357 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 38413.799357 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66251.548387 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66251.548387 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52643.371758 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56752.973607 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54680.252907 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52643.371758 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56752.973607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38413.799357 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39449.744932 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.003957 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61177.707914 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57347.146739 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59851.605833 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41024.908081 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41024.908081 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13751 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13751 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76211.167155 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76211.167155 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61177.707914 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66419.968970 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63824.975071 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61177.707914 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66419.968970 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41024.908081 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42503.489792 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5262376 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5262376 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 5460017 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 22339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 5237765 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5237765 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 5439051 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 22132 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 225289 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 225289 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1812 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16433541 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16435353 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 57984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700593792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700651776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 22341 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10970023 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.002036 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045080 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 233200 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 233200 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1820 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16379167 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16380987 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 698182912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 698241152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 22134 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10932150 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.002024 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.044949 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 10947684 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 22339 0.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 10910018 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 22132 0.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10970023 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10933859000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 18.9 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 10932150 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10894060998 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1479748 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1497004 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8230187517 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 14.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 15531 # Transaction distribution -system.membus.trans_dist::ReadResp 15531 # Transaction distribution -system.membus.trans_dist::Writeback 309 # Transaction distribution +system.cpu.toL2Bus.respLayer1.occupancy 8205133181 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 15596 # Transaction distribution +system.membus.trans_dist::ReadResp 15596 # Transaction distribution +system.membus.trans_dist::Writeback 358 # Transaction distribution system.membus.trans_dist::UpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 341 # Transaction distribution system.membus.trans_dist::ReadExResp 341 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32057 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 32057 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1035584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1035584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32236 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 32236 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1042880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1042880 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 16183 # Request fanout histogram +system.membus.snoop_fanout::samples 16297 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 16183 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 16297 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 16183 # Request fanout histogram -system.membus.reqLayer0.occupancy 28002068 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 16297 # Request fanout histogram +system.membus.reqLayer0.occupancy 26854780 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 149256371 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 83365318 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 16d507b60..b143a6790 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054141 # Nu sim_ticks 54141000000 # Number of ticks simulated final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1669323 # Simulator instruction rate (inst/s) -host_op_rate 1677636 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 997531404 # Simulator tick rate (ticks/s) -host_mem_usage 433488 # Number of bytes of host memory used -host_seconds 54.28 # Real time elapsed on the host +host_inst_rate 1893120 # Simulator instruction rate (inst/s) +host_op_rate 1902548 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1131265211 # Simulator tick rate (ticks/s) +host_mem_usage 433636 # Number of bytes of host memory used +host_seconds 47.86 # Real time elapsed on the host sim_insts 90602407 # Number of instructions simulated sim_ops 91053638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 135031170 # Request fanout histogram -system.membus.snoop_fanout::mean 4.798562 # Request fanout histogram +system.membus.snoop_fanout::mean 2.798562 # Request fanout histogram system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 27200400 20.14% 20.14% # Request fanout histogram -system.membus.snoop_fanout::5 107830770 79.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 27200400 20.14% 20.14% # Request fanout histogram +system.membus.snoop_fanout::3 107830770 79.86% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 135031170 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 3f9742fb4..7176a8af9 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.147041 # Number of seconds simulated -sim_ticks 147041218000 # Number of ticks simulated -final_tick 147041218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 147041218500 # Number of ticks simulated +final_tick 147041218500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1114927 # Simulator instruction rate (inst/s) -host_op_rate 1120467 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1809956176 # Simulator tick rate (ticks/s) -host_mem_usage 442716 # Number of bytes of host memory used -host_seconds 81.24 # Real time elapsed on the host +host_inst_rate 937429 # Simulator instruction rate (inst/s) +host_op_rate 942087 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1521808702 # Simulator tick rate (ticks/s) +host_mem_usage 442868 # Number of bytes of host memory used +host_seconds 96.62 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91026990 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 294082436 # number of cpu cycles simulated +system.cpu.numCycles 294082437 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90576861 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 27220755 # nu system.cpu.num_load_insts 22475911 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 294082435.998000 # Number of busy cycles +system.cpu.num_busy_cycles 294082436.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 18732304 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054080 # Class of executed instruction system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.593965 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3565.593939 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54410413000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593965 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 54410414000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593939 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946795 system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9910952000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9910952000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123965500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123965500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 117000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 117000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034917500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11034917500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11035034500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11035034500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10361045000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10361045000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1147270000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1147270000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 118500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 118500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11508315000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11508315000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11508433500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11508433500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses @@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.893511 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.893511 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24114.773971 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24114.773971 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11655.022999 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11509.893511 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11509.893511 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24614.773971 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24614.773971 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12155.022999 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12155.022999 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12155.109643 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12155.109643 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 510.120575 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 510.120572 # Cycle average of tags in use system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.120575 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.120572 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id @@ -374,12 +374,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32073500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32073500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32073500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32073500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32073500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32073500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32074000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32074000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32074000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32074000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32074000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32074000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses @@ -392,12 +392,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53545.075125 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53545.075125 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53545.075125 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53545.075125 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53545.075125 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53545.075125 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53545.909850 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53545.909850 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53545.909850 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53545.909850 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53545.909850 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53545.909850 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,34 +412,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599 system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30875500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 30875500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30875500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 30875500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30875500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 30875500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31175500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 31175500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31175500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 31175500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31175500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 31175500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51545.075125 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51545.075125 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51545.075125 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51545.075125 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51545.075125 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51545.075125 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52045.909850 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52045.909850 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52045.909850 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52045.909850 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52045.909850 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52045.909850 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9567.852615 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9567.852421 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446533 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.172981 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 193.233101 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446344 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.172977 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 193.233100 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015111 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy @@ -477,17 +477,17 @@ system.cpu.l2cache.demand_misses::total 15340 # nu system.cpu.l2cache.overall_misses::cpu.inst 578 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14762 # number of overall misses system.cpu.l2cache.overall_misses::total 15340 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30066500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11130000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 41196500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 756746500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 756746500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 30066500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 767876500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 797943000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 30066500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 767876500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 797943000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30356000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11237000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 41593000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764020500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 764020500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 30356000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 775257500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 805613500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 30356000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 775257500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 805613500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 900788 # number of ReadReq accesses(hits+misses) @@ -512,17 +512,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.016192 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52018.166090 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52009.345794 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52015.782828 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52017.218862 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52017.218862 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52018.166090 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52017.104728 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52017.144720 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52018.166090 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52017.104728 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52017.144720 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.031142 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52509.345794 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52516.414141 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52517.218862 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52517.218862 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.031142 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52517.104728 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52517.177314 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.031142 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52517.104728 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52517.177314 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -542,17 +542,17 @@ system.cpu.l2cache.demand_mshr_misses::total 15340 system.cpu.l2cache.overall_mshr_misses::cpu.inst 578 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14762 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8560000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 31680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 581920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 581920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590480000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 613600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590480000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 613600000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23409000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8667000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32076000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 589194000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 589194000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23409000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 597861000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 621270000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23409000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 597861000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 621270000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000238 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000879 # mshr miss rate for ReadReq accesses @@ -564,17 +564,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution @@ -589,19 +589,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1889731 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 1889731 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 1889731 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1889731 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) @@ -628,9 +626,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15340 # Request fanout histogram -system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 15603500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 138323000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 76963500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 86f47af4e..b81c12b39 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.361489 # Number of seconds simulated -sim_ticks 361488530000 # Number of ticks simulated -final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 361488530500 # Number of ticks simulated +final_tick 361488530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1379749 # Simulator instruction rate (inst/s) -host_op_rate 1379806 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2045576865 # Simulator tick rate (ticks/s) -host_mem_usage 421936 # Number of bytes of host memory used -host_seconds 176.72 # Real time elapsed on the host +host_inst_rate 1163469 # Simulator instruction rate (inst/s) +host_op_rate 1163517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1724927568 # Simulator tick rate (ticks/s) +host_mem_usage 425840 # Number of bytes of host memory used +host_seconds 209.57 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,32 +29,9 @@ system.physmem.bw_inst_read::total 155623 # In system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1036 # Transaction distribution -system.membus.trans_dist::ReadResp 1036 # Transaction distribution -system.membus.trans_dist::ReadExReq 14567 # Transaction distribution -system.membus.trans_dist::ReadExResp 14567 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 15603 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 15603 # Request fanout histogram -system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 722977060 # number of cpu cycles simulated +system.cpu.numCycles 722977061 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 243825150 # Number of instructions committed @@ -73,7 +50,7 @@ system.cpu.num_mem_refs 105711441 # nu system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 722977059.998000 # Number of busy cycles +system.cpu.num_busy_cycles 722977060.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29302884 # Number of branches fetched @@ -112,13 +89,141 @@ system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction +system.cpu.dcache.tags.replacements 935475 # number of replacements +system.cpu.dcache.tags.tagsinuse 3562.469045 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 134366266000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469045 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits +system.cpu.dcache.overall_hits::total 104182817 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses +system.cpu.dcache.overall_misses::total 939567 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks +system.cpu.dcache.writebacks::total 935266 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10274449500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10274449500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1148937000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1148937000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 88000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 88000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11423386500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11423386500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11423386500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11423386500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11507.385281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11507.385281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24597.238279 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24597.238279 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12158.139334 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12158.139334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12158.139334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12158.139334 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 25 # number of replacements -system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 725.412975 # Cycle average of tags in use system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 725.412975 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id @@ -141,12 +246,12 @@ system.cpu.icache.demand_misses::cpu.inst 882 # n system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses system.cpu.icache.overall_misses::total 882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 48384000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 48384000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 48384000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 48384000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 48384000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 48384500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 48384500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 48384500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 48384500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 48384500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses @@ -159,12 +264,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.142857 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54857.142857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54857.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54857.142857 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.709751 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54857.709751 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.709751 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54857.709751 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.709751 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54857.709751 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -179,33 +284,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 882 system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47061500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 47061500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47061500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 47061500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47061500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 47061500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53357.709751 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53357.709751 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53357.709751 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53357.709751 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53357.709751 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53357.709751 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9730.625210 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670164 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635590 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy @@ -244,17 +349,17 @@ system.cpu.l2cache.demand_misses::total 15603 # nu system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses system.cpu.l2cache.overall_misses::total 15603 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8164000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 53872000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 765648000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 811356000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 765648000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 811356000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46148000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8242500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 54390500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764767500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 764767500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 46148000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 773010000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 819158000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 46148000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 773010000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 819158000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses) @@ -279,17 +384,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.016591 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.568828 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.482625 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.568828 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.032045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.568828 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.032045 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -309,17 +414,17 @@ system.cpu.l2cache.demand_mshr_misses::total 15603 system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41440000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 588960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 624120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 588960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 624120000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35599500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6358500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41958000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 589963500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 589963500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35599500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 596322000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 631921500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35599500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 596322000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 631921500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001159 # mshr miss rate for ReadReq accesses @@ -331,146 +436,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 935475 # number of replacements -system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits -system.cpu.dcache.overall_hits::total 104182817 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses -system.cpu.dcache.overall_misses::total 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks -system.cpu.dcache.writebacks::total 935266 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution @@ -500,5 +477,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 1323000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1036 # Transaction distribution +system.membus.trans_dist::ReadResp 1036 # Transaction distribution +system.membus.trans_dist::ReadExReq 14567 # Transaction distribution +system.membus.trans_dist::ReadExResp 14567 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15603 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15603 # Request fanout histogram +system.membus.reqLayer0.occupancy 15603500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 78015500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index a20619a99..22cc57507 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061857 # Number of seconds simulated -sim_ticks 61857343500 # Number of ticks simulated -final_tick 61857343500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.062113 # Number of seconds simulated +sim_ticks 62113055500 # Number of ticks simulated +final_tick 62113055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113051 # Simulator instruction rate (inst/s) -host_op_rate 199065 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44263102 # Simulator tick rate (ticks/s) -host_mem_usage 453712 # Number of bytes of host memory used -host_seconds 1397.49 # Real time elapsed on the host +host_inst_rate 113198 # Simulator instruction rate (inst/s) +host_op_rate 199324 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44503726 # Simulator tick rate (ticks/s) +host_mem_usage 454072 # Number of bytes of host memory used +host_seconds 1395.68 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 64640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1884928 # Number of bytes read from this memory -system.physmem.bytes_read::total 1949568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64640 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 12608 # Number of bytes written to this memory -system.physmem.bytes_written::total 12608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1010 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29452 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30462 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 197 # Number of write requests responded to by this memory -system.physmem.num_writes::total 197 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1044985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 30472178 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 31517163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1044985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1044985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 203824 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 203824 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 203824 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1044985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 30472178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 31720987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30463 # Number of read requests accepted -system.physmem.writeReqs 197 # Number of write requests accepted -system.physmem.readBursts 30463 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 197 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1943744 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5888 # Total number of bytes read from write queue -system.physmem.bytesWritten 11328 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1949632 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 12608 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 92 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 64896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1883008 # Number of bytes read from this memory +system.physmem.bytes_read::total 1947904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10624 # Number of bytes written to this memory +system.physmem.bytes_written::total 10624 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1014 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29422 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30436 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 166 # Number of write requests responded to by this memory +system.physmem.num_writes::total 166 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1044805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 30315817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 31360621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1044805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1044805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 171043 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 171043 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 171043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1044805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 30315817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 31531664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30436 # Number of read requests accepted +system.physmem.writeReqs 166 # Number of write requests accepted +system.physmem.readBursts 30436 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 166 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1943680 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4224 # Total number of bytes read from write queue +system.physmem.bytesWritten 9216 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1947904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10624 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 66 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1927 # Per bank write bursts -system.physmem.perBankRdBursts::1 2067 # Per bank write bursts -system.physmem.perBankRdBursts::2 2027 # Per bank write bursts -system.physmem.perBankRdBursts::3 1932 # Per bank write bursts +system.physmem.perBankRdBursts::0 1923 # Per bank write bursts +system.physmem.perBankRdBursts::1 2063 # Per bank write bursts +system.physmem.perBankRdBursts::2 2030 # Per bank write bursts +system.physmem.perBankRdBursts::3 1928 # Per bank write bursts system.physmem.perBankRdBursts::4 2026 # Per bank write bursts system.physmem.perBankRdBursts::5 1903 # Per bank write bursts system.physmem.perBankRdBursts::6 1964 # Per bank write bursts -system.physmem.perBankRdBursts::7 1863 # Per bank write bursts -system.physmem.perBankRdBursts::8 1937 # Per bank write bursts -system.physmem.perBankRdBursts::9 1937 # Per bank write bursts -system.physmem.perBankRdBursts::10 1804 # Per bank write bursts -system.physmem.perBankRdBursts::11 1796 # Per bank write bursts +system.physmem.perBankRdBursts::7 1866 # Per bank write bursts +system.physmem.perBankRdBursts::8 1938 # Per bank write bursts +system.physmem.perBankRdBursts::9 1940 # Per bank write bursts +system.physmem.perBankRdBursts::10 1805 # Per bank write bursts +system.physmem.perBankRdBursts::11 1795 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1800 # Per bank write bursts system.physmem.perBankRdBursts::14 1818 # Per bank write bursts -system.physmem.perBankRdBursts::15 1778 # Per bank write bursts +system.physmem.perBankRdBursts::15 1779 # Per bank write bursts system.physmem.perBankWrBursts::0 15 # Per bank write bursts -system.physmem.perBankWrBursts::1 94 # Per bank write bursts -system.physmem.perBankWrBursts::2 13 # Per bank write bursts -system.physmem.perBankWrBursts::3 21 # Per bank write bursts +system.physmem.perBankWrBursts::1 80 # Per bank write bursts +system.physmem.perBankWrBursts::2 11 # Per bank write bursts +system.physmem.perBankWrBursts::3 10 # Per bank write bursts system.physmem.perBankWrBursts::4 7 # Per bank write bursts -system.physmem.perBankWrBursts::5 7 # Per bank write bursts -system.physmem.perBankWrBursts::6 12 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 13 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 5 # Per bank write bursts @@ -82,27 +82,27 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61857329000 # Total gap between requests +system.physmem.totGap 62113012500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30463 # Read request sizes (log2) +system.physmem.readPktSize::6 30436 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 197 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 166 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29887 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -146,22 +146,22 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,327 +193,324 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2724 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 716.922173 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 515.538805 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 389.679049 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 350 12.85% 12.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 254 9.32% 22.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 128 4.70% 26.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 108 3.96% 30.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 103 3.78% 34.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 103 3.78% 38.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 111 4.07% 42.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 70 2.57% 45.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1497 54.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2724 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 10 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3031.200000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 22.218074 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 9548.252985 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 9 90.00% 90.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 10.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 10 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 10 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.700000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.676249 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.948683 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2 20.00% 20.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 7 70.00% 90.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 10.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 10 # Writes before turning the bus around for reads -system.physmem.totQLat 130999000 # Total ticks spent queuing -system.physmem.totMemAccLat 700455250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 151855000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4313.29 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 2732 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 714.471449 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 512.855124 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 389.294613 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 368 13.47% 13.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 227 8.31% 21.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 131 4.80% 26.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 130 4.76% 31.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 109 3.99% 35.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 99 3.62% 38.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 107 3.92% 42.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 79 2.89% 45.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1482 54.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2732 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 3788.500000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.757307 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10676.303052 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7 87.50% 87.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 12.50% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 8 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads +system.physmem.totQLat 135350500 # Total ticks spent queuing +system.physmem.totMemAccLat 704788000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 151850000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4456.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23063.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 31.42 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.18 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 31.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.20 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 23206.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 31.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 31.36 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.25 # Data bus utilization in percentage -system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.24 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.62 # Average write queue length when enqueuing -system.physmem.readRowHits 27696 # Number of row buffer hits during reads -system.physmem.writeRowHits 119 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 60.41 # Row buffer hit rate for writes -system.physmem.avgGap 2017525.41 # Average gap between requests -system.physmem.pageHitRate 90.99 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 10939320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 5968875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 122226000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1095120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4040000640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2776043070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34677412500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41633685525 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.093587 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57673269750 # Time in different power states -system.physmem_0.memoryStateTime::REF 2065440000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.89 # Average write queue length when enqueuing +system.physmem.readRowHits 27681 # Number of row buffer hits during reads +system.physmem.writeRowHits 96 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.15 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.83 # Row buffer hit rate for writes +system.physmem.avgGap 2029704.35 # Average gap between requests +system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 10931760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 5964750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 122311800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 881280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4056783120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2875200840 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34744599750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41816673300 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.255215 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57785258250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2074020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2115534000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2252296250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 9623880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5251125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 114246600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 9714600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5300625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 114332400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4040000640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2977027920 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34501101750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41647303755 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.313903 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57380456750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2065440000 # Time in different power states +system.physmem_1.refreshEnergy 4056783120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3044489985 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34596104250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41826776820 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.417815 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57536988500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2074020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2409426750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2500187750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37414357 # Number of BP lookups -system.cpu.branchPred.condPredicted 37414357 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 797165 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 21409472 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21302649 # Number of BTB hits +system.cpu.branchPred.lookups 37409115 # Number of BP lookups +system.cpu.branchPred.condPredicted 37409115 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 796961 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 21404292 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21297612 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.501048 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5521067 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5418 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.501595 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5520840 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5370 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 123714688 # number of cpu cycles simulated +system.cpu.numCycles 124226112 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28240185 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 201519425 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37414357 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 26823716 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 94568946 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1664995 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 796 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13919 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 16 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 27849620 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 205824 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 123656373 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.872113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.370891 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28235935 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 201516528 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37409115 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 26818452 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 95078093 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1665601 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 765 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13635 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 27845177 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 203940 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 124161279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.860308 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.369086 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 62738354 50.74% 50.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3652838 2.95% 53.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3508504 2.84% 56.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5967471 4.83% 61.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7654257 6.19% 67.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5436238 4.40% 71.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3366087 2.72% 74.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2072932 1.68% 76.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 29259692 23.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 63245394 50.94% 50.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3661074 2.95% 53.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3505984 2.82% 56.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5966145 4.81% 61.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7636259 6.15% 67.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5451035 4.39% 72.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3359633 2.71% 74.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2076013 1.67% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 29259742 23.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 123656373 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.302425 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.628905 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13285381 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63221156 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 36527318 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9790021 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 832497 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 334996459 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 832497 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18592314 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8932600 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16230 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 40801194 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 54481538 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 328650401 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2309 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 768646 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 48119117 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4597217 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 330628900 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 873052183 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 537682976 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 692 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 124161279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.301137 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.622175 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13292806 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63720296 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 36521548 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9793829 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 832800 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 335002829 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 832800 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18597256 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8862328 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16249 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 40799373 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 55053273 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 328652486 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2589 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 765140 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 48300530 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4998296 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 330629230 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 873051813 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 537695602 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 524 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 51416153 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 475 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 66201491 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106325920 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 36528653 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 49813174 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8481864 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 325481116 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2295 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 307976733 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 54133 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 46686820 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 68916320 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1850 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 123656373 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.490585 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.124426 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 51416483 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 478 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 478 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 66182076 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106321382 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 36530805 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 49812358 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8510426 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 325477303 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2126 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 307989355 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 51384 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 46683880 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 68913858 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1681 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 124161279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.480559 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.127626 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 30107102 24.35% 24.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19550071 15.81% 40.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 16727632 13.53% 53.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17064547 13.80% 67.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16031841 12.96% 80.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12684150 10.26% 90.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5762404 4.66% 95.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4173789 3.38% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1554837 1.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30601082 24.65% 24.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19574247 15.77% 40.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 16779908 13.51% 53.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17045625 13.73% 67.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15969415 12.86% 80.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12663210 10.20% 90.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5764205 4.64% 95.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4169219 3.36% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1594368 1.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 123656373 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 124161279 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 316999 7.53% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3711822 88.14% 95.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 182351 4.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 316891 7.52% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3711549 88.13% 95.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 182770 4.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33338 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 175394846 56.95% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11227 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 339 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 53 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 98503391 31.98% 88.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34033539 11.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 175395413 56.95% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11214 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 334 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 40 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 98514236 31.99% 88.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34034780 11.05% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 307976733 # Type of FU issued -system.cpu.iq.rate 2.489411 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4211172 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013674 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 743874545 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 372209729 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 305990656 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 599 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1009 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 208 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 312154274 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 58255905 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 307989355 # Type of FU issued +system.cpu.iq.rate 2.479264 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4211210 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013673 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 744402178 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 372203676 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 305987015 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 405 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 146 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 312167028 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 199 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 58260510 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 15546535 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 56855 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 41794 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 5088901 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 15541997 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 57887 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 42363 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 5091053 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3643 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 105171 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3649 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 124471 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 832497 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5705091 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3134574 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 325483411 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125197 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106325920 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 36528653 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 468 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2776 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3138754 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 41794 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 401755 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445201 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 846956 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 306897357 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98135370 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1079376 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 832800 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5705086 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3056605 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 325479429 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 124396 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106321382 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 36530805 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2770 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3059848 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 42363 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 401945 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 444615 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 846560 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 306916313 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98157297 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1073042 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 131959976 # number of memory reference insts executed -system.cpu.iew.exec_branches 31536734 # Number of branches executed -system.cpu.iew.exec_stores 33824606 # Number of stores executed -system.cpu.iew.exec_rate 2.480687 # Inst execution rate -system.cpu.iew.wb_sent 306320115 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 305990864 # cumulative count of insts written-back -system.cpu.iew.wb_producers 231632886 # num instructions producing a value -system.cpu.iew.wb_consumers 336126880 # num instructions consuming a value +system.cpu.iew.exec_refs 131977680 # number of memory reference insts executed +system.cpu.iew.exec_branches 31536553 # Number of branches executed +system.cpu.iew.exec_stores 33820383 # Number of stores executed +system.cpu.iew.exec_rate 2.470626 # Inst execution rate +system.cpu.iew.wb_sent 306317735 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 305987161 # cumulative count of insts written-back +system.cpu.iew.wb_producers 231581512 # num instructions producing a value +system.cpu.iew.wb_consumers 336076811 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.473359 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.689123 # average fanout of values written-back +system.cpu.iew.wb_rate 2.463147 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.689073 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 47392313 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 47389031 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 797958 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 117208008 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.373494 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.089570 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 797726 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 117712955 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.363312 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.086758 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52857679 45.10% 45.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15964987 13.62% 58.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 10970811 9.36% 68.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8748487 7.46% 75.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1925592 1.64% 77.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1731776 1.48% 78.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 850158 0.73% 79.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 689946 0.59% 79.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23468572 20.02% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 53359699 45.33% 45.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 15949045 13.55% 58.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 10998829 9.34% 68.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8750765 7.43% 75.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1918688 1.63% 77.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1725778 1.47% 78.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 854994 0.73% 79.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 681396 0.58% 80.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23473761 19.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 117208008 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 117712955 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -559,325 +556,325 @@ system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23468572 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 23473761 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 419324213 # The number of ROB reads -system.cpu.rob.rob_writes 657627213 # The number of ROB writes -system.cpu.timesIdled 611 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58315 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 419820689 # The number of ROB reads +system.cpu.rob.rob_writes 657620446 # The number of ROB writes +system.cpu.timesIdled 598 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 64833 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.783061 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.783061 # CPI: Total CPI of All Threads -system.cpu.ipc 1.277040 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.277040 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 493625454 # number of integer regfile reads -system.cpu.int_regfile_writes 240898259 # number of integer regfile writes -system.cpu.fp_regfile_reads 178 # number of floating regfile reads -system.cpu.fp_regfile_writes 135 # number of floating regfile writes -system.cpu.cc_regfile_reads 107699117 # number of cc regfile reads -system.cpu.cc_regfile_writes 64568807 # number of cc regfile writes -system.cpu.misc_regfile_reads 196282104 # number of misc regfile reads +system.cpu.cpi 0.786298 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.786298 # CPI: Total CPI of All Threads +system.cpu.ipc 1.271782 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.271782 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 493661924 # number of integer regfile reads +system.cpu.int_regfile_writes 240899982 # number of integer regfile writes +system.cpu.fp_regfile_reads 121 # number of floating regfile reads +system.cpu.fp_regfile_writes 99 # number of floating regfile writes +system.cpu.cc_regfile_reads 107697498 # number of cc regfile reads +system.cpu.cc_regfile_writes 64570083 # number of cc regfile writes +system.cpu.misc_regfile_reads 196298941 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2072433 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.938050 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 68459745 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076529 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32.968355 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 19695463250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.938050 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993393 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993393 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2072451 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.920590 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 68431233 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076547 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32.954339 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 19749732250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.920590 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993145 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993145 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 636 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3333 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 585 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3383 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 144502465 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 144502465 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 37113882 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37113882 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345863 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345863 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68459745 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68459745 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68459745 # number of overall hits -system.cpu.dcache.overall_hits::total 68459745 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2659334 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2659334 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93889 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93889 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2753223 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2753223 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2753223 # number of overall misses -system.cpu.dcache.overall_misses::total 2753223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31861027000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31861027000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2765155494 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2765155494 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34626182494 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34626182494 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34626182494 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34626182494 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 39773216 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 39773216 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 144497109 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 144497109 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 37085404 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 37085404 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345829 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345829 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68431233 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68431233 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68431233 # number of overall hits +system.cpu.dcache.overall_hits::total 68431233 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2685125 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2685125 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93923 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93923 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2779048 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2779048 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2779048 # number of overall misses +system.cpu.dcache.overall_misses::total 2779048 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32124036248 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32124036248 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2977938994 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2977938994 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35101975242 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35101975242 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35101975242 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35101975242 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 39770529 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 39770529 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 71212968 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 71212968 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 71212968 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 71212968 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066862 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.066862 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002986 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002986 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.038662 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.038662 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038662 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038662 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11980.829411 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11980.829411 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29451.325437 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29451.325437 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12576.599314 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12576.599314 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12576.599314 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12576.599314 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 182189 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 71210281 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 71210281 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 71210281 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 71210281 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067515 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.067515 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002987 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002987 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.039026 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.039026 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039026 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039026 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11963.702341 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11963.702341 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31706.174143 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31706.174143 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12630.935213 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12630.935213 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12630.935213 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12630.935213 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 199096 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 39926 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 39942 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.563167 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.984628 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066654 # number of writebacks -system.cpu.dcache.writebacks::total 2066654 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 664835 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 664835 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11856 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11856 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 676691 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 676691 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 676691 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 676691 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994499 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994499 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82033 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82033 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076532 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076532 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076532 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076532 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22009124500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22009124500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2514972744 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2514972744 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24524097244 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24524097244 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24524097244 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24524097244 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050147 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050147 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 2066749 # number of writebacks +system.cpu.dcache.writebacks::total 2066749 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 690617 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 690617 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 702500 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 702500 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 702500 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 702500 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994508 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994508 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82040 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82040 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076548 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076548 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076548 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076548 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23032838251 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23032838251 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2765865745 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2765865745 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25798703996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25798703996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25798703996 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25798703996 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050150 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050150 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029159 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029159 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11034.913780 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11034.913780 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30658.061317 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30658.061317 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11810.122475 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11810.122475 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11810.122475 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11810.122475 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029161 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029161 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11548.130291 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11548.130291 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33713.624391 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33713.624391 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12423.841874 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12423.841874 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12423.841874 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12423.841874 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 62 # number of replacements -system.cpu.icache.tags.tagsinuse 827.714171 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27848273 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1026 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 27142.566277 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 58 # number of replacements +system.cpu.icache.tags.tagsinuse 832.593358 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27843840 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1028 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 27085.447471 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 827.714171 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.404157 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.404157 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 964 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.470703 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55700266 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55700266 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27848273 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27848273 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27848273 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27848273 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27848273 # number of overall hits -system.cpu.icache.overall_hits::total 27848273 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1347 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1347 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1347 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1347 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1347 # number of overall misses -system.cpu.icache.overall_misses::total 1347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 92877749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 92877749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 92877749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 92877749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 92877749 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 880 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.473633 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 55691382 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55691382 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27843840 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27843840 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27843840 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27843840 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27843840 # number of overall hits +system.cpu.icache.overall_hits::total 27843840 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 761 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1395 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27655 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913666 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33267098 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33267098 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1994043 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1994057 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2066749 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2066749 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2158751250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2237185250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 78434000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2158751250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2237185250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1028 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1994469 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1995497 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2066749 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2066749 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82079 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82079 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1028 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076548 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077576 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1028 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076548 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077576 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.986381 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000214 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000722 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353269 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.353269 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.986381 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014169 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014650 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.986381 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014169 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014650 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77351.084813 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76067.488263 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76971.354167 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73332.407918 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73332.407918 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77351.084813 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73372.009041 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73504.575174 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77351.084813 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73372.009041 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73504.575174 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -886,109 +883,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 197 # number of writebacks -system.cpu.l2cache.writebacks::total 197 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1010 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 455 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1465 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1010 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29453 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30463 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1010 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29453 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30463 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58476750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26090500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84567250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1530042250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1530042250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58476750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1556132750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1614609500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58476750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1556132750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1614609500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000228 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000734 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353354 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353354 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014663 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014663 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57897.772277 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57341.758242 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57725.085324 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52763.716463 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.716463 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57897.772277 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52834.439616 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53002.314283 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57897.772277 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52834.439616 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53002.314283 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 166 # number of writebacks +system.cpu.l2cache.writebacks::total 166 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1014 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 426 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1440 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1014 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29422 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30436 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29422 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30436 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 65771000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27116250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 92887250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1763882000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1763882000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65771000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1790998250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1856769250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65771000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1790998250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1856769250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000214 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000722 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353269 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353269 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014650 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014650 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64862.919132 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63653.169014 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64505.034722 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60831.907849 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60831.907849 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64862.919132 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60872.756781 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61005.692272 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64862.919132 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60872.756781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61005.692272 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1995493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82065 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82065 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2052 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219715 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6221767 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 1995497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995496 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066749 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82079 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82079 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2056 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219844 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6221900 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265170944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265236736 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4144212 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 4144325 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4144212 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4144325 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4144212 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4138760000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4144325 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4138911500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1710750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1734248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3121417250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3121601499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1465 # Transaction distribution -system.membus.trans_dist::ReadResp 1462 # Transaction distribution -system.membus.trans_dist::Writeback 197 # Transaction distribution -system.membus.trans_dist::ReadExReq 28998 # Transaction distribution -system.membus.trans_dist::ReadExResp 28998 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61120 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61120 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61120 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1440 # Transaction distribution +system.membus.trans_dist::ReadResp 1439 # Transaction distribution +system.membus.trans_dist::Writeback 166 # Transaction distribution +system.membus.trans_dist::ReadExReq 28996 # Transaction distribution +system.membus.trans_dist::ReadExResp 28996 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61037 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61037 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61037 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1958464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1958464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1958464 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 30660 # Request fanout histogram +system.membus.snoop_fanout::samples 30602 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30660 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30602 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30660 # Request fanout histogram -system.membus.reqLayer0.occupancy 43499500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30602 # Request fanout histogram +system.membus.reqLayer0.occupancy 42540000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 291787500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 160392250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index f80736ade..05a346173 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.365989 # Number of seconds simulated -sim_ticks 365989065000 # Number of ticks simulated -final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 365989065500 # Number of ticks simulated +final_tick 365989065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 756908 # Simulator instruction rate (inst/s) -host_op_rate 1332794 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1753418925 # Simulator tick rate (ticks/s) -host_mem_usage 446124 # Number of bytes of host memory used -host_seconds 208.73 # Real time elapsed on the host +host_inst_rate 638452 # Simulator instruction rate (inst/s) +host_op_rate 1124211 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1479007835 # Simulator tick rate (ticks/s) +host_mem_usage 450980 # Number of bytes of host memory used +host_seconds 247.46 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,36 +36,10 @@ system.physmem.bw_total::writebacks 17487 # To system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1025 # Transaction distribution -system.membus.trans_dist::ReadResp 1025 # Transaction distribution -system.membus.trans_dist::Writeback 100 # Transaction distribution -system.membus.trans_dist::ReadExReq 29024 # Transaction distribution -system.membus.trans_dist::ReadExResp 29024 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 30149 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30149 # Request fanout histogram -system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 731978130 # number of cpu cycles simulated +system.cpu.numCycles 731978131 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed @@ -86,7 +60,7 @@ system.cpu.num_mem_refs 122219137 # nu system.cpu.num_load_insts 90779385 # Number of load instructions system.cpu.num_store_insts 31439752 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 731978129.998000 # Number of busy cycles +system.cpu.num_busy_cycles 731978130.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29309705 # Number of branches fetched @@ -125,13 +99,121 @@ system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction +system.cpu.dcache.tags.replacements 2062733 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.488607 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 126079702000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488607 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits +system.cpu.dcache.overall_hits::total 120152370 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses +system.cpu.dcache.overall_misses::total 2066829 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks +system.cpu.dcache.writebacks::total 2062484 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22557604000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22557604000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2439292500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2439292500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24996896500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24996896500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24996896500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24996896500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11504.755396 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11504.755396 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22988.554223 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22988.554223 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 24 # number of replacements -system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 665.632506 # Cycle average of tags in use system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 665.632506 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id @@ -153,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses system.cpu.icache.overall_misses::total 808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44230000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44230000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44230500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44230500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44230500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44230500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44230500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses @@ -171,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54740.099010 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54740.099010 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54740.099010 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.717822 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54740.717822 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54740.717822 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54740.717822 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -191,33 +273,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 808 system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42614000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42614000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42614000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42614000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42614000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42614000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43018500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 43018500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43018500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 43018500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43018500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 43018500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52740.099010 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52740.099010 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53240.717822 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53240.717822 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53240.717822 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53240.717822 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53240.717822 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53240.717822 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 318 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 20041.899592 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 19330.352993 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646380 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy @@ -256,17 +338,17 @@ system.cpu.l2cache.demand_misses::total 30049 # nu system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29246 # number of overall misses system.cpu.l2cache.overall_misses::total 30049 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41756000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11544000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 53300000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509279000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1509279000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 41756000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1520823000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1562579000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 41756000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1520823000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1562579000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42158000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11655000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 53813000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1523791000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1523791000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 42158000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1535446000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1577604000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 42158000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1535446000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1577604000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses) @@ -291,17 +373,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.014533 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.068082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.068082 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52001.031648 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52001.031648 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.622665 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.487805 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52501.068082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52501.068082 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.622665 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.059974 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.048288 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.622665 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.059974 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.048288 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,17 +405,17 @@ system.cpu.l2cache.demand_mshr_misses::total 30049 system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41000000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1160960000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1160960000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1169840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1201960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1169840000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1201960000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32521500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8991000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41512500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1175472000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1175472000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32521500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1184463000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1216984500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32521500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1184463000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1216984500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses @@ -345,126 +427,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2062733 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits -system.cpu.dcache.overall_hits::total 120152370 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses -system.cpu.dcache.overall_misses::total 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks -system.cpu.dcache.writebacks::total 2062484 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386238000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386238000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23963482000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23963482000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23963482000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23963482000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11004.755396 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution @@ -496,5 +470,31 @@ system.cpu.toL2Bus.respLayer0.occupancy 1212000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1025 # Transaction distribution +system.membus.trans_dist::ReadResp 1025 # Transaction distribution +system.membus.trans_dist::Writeback 100 # Transaction distribution +system.membus.trans_dist::ReadExReq 29024 # Transaction distribution +system.membus.trans_dist::ReadExResp 29024 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 30149 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 30149 # Request fanout histogram +system.membus.reqLayer0.occupancy 30585000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 150276500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index 9abbba24f..af9445aa2 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.410940 # Number of seconds simulated -sim_ticks 410940483000 # Number of ticks simulated -final_tick 410940483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.413669 # Number of seconds simulated +sim_ticks 413668621500 # Number of ticks simulated +final_tick 413668621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 207244 # Simulator instruction rate (inst/s) -host_op_rate 207244 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 139181064 # Simulator tick rate (ticks/s) -host_mem_usage 283892 # Number of bytes of host memory used -host_seconds 2952.56 # Real time elapsed on the host +host_inst_rate 330001 # Simulator instruction rate (inst/s) +host_op_rate 330001 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 223093103 # Simulator tick rate (ticks/s) +host_mem_usage 297764 # Number of bytes of host memory used +host_seconds 1854.24 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 171008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24149568 # Number of bytes read from this memory -system.physmem.bytes_read::total 24320576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 171008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 171008 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18724416 # Number of bytes written to this memory -system.physmem.bytes_written::total 18724416 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2672 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 377337 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380009 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292569 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292569 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 416138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 58766583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59182721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 416138 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 416138 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45564788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45564788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45564788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 416138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 58766583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104747509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 380009 # Number of read requests accepted -system.physmem.writeReqs 292569 # Number of write requests accepted -system.physmem.readBursts 380009 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292569 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24297024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23552 # Total number of bytes read from write queue +system.physmem.bytes_read::cpu.inst 170880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24149824 # Number of bytes read from this memory +system.physmem.bytes_read::total 24320704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 170880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 170880 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18724288 # Number of bytes written to this memory +system.physmem.bytes_written::total 18724288 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2670 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 377341 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380011 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292567 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292567 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 413084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58379637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 58792721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 413084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 413084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45263979 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45263979 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45263979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 413084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58379637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104056701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 380011 # Number of read requests accepted +system.physmem.writeReqs 292567 # Number of write requests accepted +system.physmem.readBursts 380011 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292567 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24296448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 24256 # Total number of bytes read from write queue system.physmem.bytesWritten 18722752 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24320576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18724416 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 368 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytesReadSys 24320704 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18724288 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 379 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23736 # Per bank write bursts -system.physmem.perBankRdBursts::1 23216 # Per bank write bursts -system.physmem.perBankRdBursts::2 23510 # Per bank write bursts -system.physmem.perBankRdBursts::3 24529 # Per bank write bursts -system.physmem.perBankRdBursts::4 25457 # Per bank write bursts -system.physmem.perBankRdBursts::5 23594 # Per bank write bursts -system.physmem.perBankRdBursts::6 23677 # Per bank write bursts -system.physmem.perBankRdBursts::7 23981 # Per bank write bursts -system.physmem.perBankRdBursts::8 23173 # Per bank write bursts -system.physmem.perBankRdBursts::9 23945 # Per bank write bursts -system.physmem.perBankRdBursts::10 24675 # Per bank write bursts -system.physmem.perBankRdBursts::11 22741 # Per bank write bursts -system.physmem.perBankRdBursts::12 23723 # Per bank write bursts -system.physmem.perBankRdBursts::13 24409 # Per bank write bursts -system.physmem.perBankRdBursts::14 22807 # Per bank write bursts -system.physmem.perBankRdBursts::15 22468 # Per bank write bursts +system.physmem.perBankRdBursts::0 23738 # Per bank write bursts +system.physmem.perBankRdBursts::1 23215 # Per bank write bursts +system.physmem.perBankRdBursts::2 23512 # Per bank write bursts +system.physmem.perBankRdBursts::3 24525 # Per bank write bursts +system.physmem.perBankRdBursts::4 25461 # Per bank write bursts +system.physmem.perBankRdBursts::5 23591 # Per bank write bursts +system.physmem.perBankRdBursts::6 23667 # Per bank write bursts +system.physmem.perBankRdBursts::7 23972 # Per bank write bursts +system.physmem.perBankRdBursts::8 23176 # Per bank write bursts +system.physmem.perBankRdBursts::9 23948 # Per bank write bursts +system.physmem.perBankRdBursts::10 24672 # Per bank write bursts +system.physmem.perBankRdBursts::11 22745 # Per bank write bursts +system.physmem.perBankRdBursts::12 23724 # Per bank write bursts +system.physmem.perBankRdBursts::13 24415 # Per bank write bursts +system.physmem.perBankRdBursts::14 22805 # Per bank write bursts +system.physmem.perBankRdBursts::15 22466 # Per bank write bursts system.physmem.perBankWrBursts::0 17754 # Per bank write bursts -system.physmem.perBankWrBursts::1 17431 # Per bank write bursts -system.physmem.perBankWrBursts::2 17901 # Per bank write bursts -system.physmem.perBankWrBursts::3 18773 # Per bank write bursts +system.physmem.perBankWrBursts::1 17430 # Per bank write bursts +system.physmem.perBankWrBursts::2 17902 # Per bank write bursts +system.physmem.perBankWrBursts::3 18771 # Per bank write bursts system.physmem.perBankWrBursts::4 19442 # Per bank write bursts system.physmem.perBankWrBursts::5 18543 # Per bank write bursts -system.physmem.perBankWrBursts::6 18677 # Per bank write bursts -system.physmem.perBankWrBursts::7 18574 # Per bank write bursts -system.physmem.perBankWrBursts::8 18352 # Per bank write bursts +system.physmem.perBankWrBursts::6 18683 # Per bank write bursts +system.physmem.perBankWrBursts::7 18577 # Per bank write bursts +system.physmem.perBankWrBursts::8 18350 # Per bank write bursts system.physmem.perBankWrBursts::9 18833 # Per bank write bursts -system.physmem.perBankWrBursts::10 19127 # Per bank write bursts -system.physmem.perBankWrBursts::11 17966 # Per bank write bursts -system.physmem.perBankWrBursts::12 18224 # Per bank write bursts -system.physmem.perBankWrBursts::13 18695 # Per bank write bursts -system.physmem.perBankWrBursts::14 17148 # Per bank write bursts +system.physmem.perBankWrBursts::10 19129 # Per bank write bursts +system.physmem.perBankWrBursts::11 17963 # Per bank write bursts +system.physmem.perBankWrBursts::12 18222 # Per bank write bursts +system.physmem.perBankWrBursts::13 18694 # Per bank write bursts +system.physmem.perBankWrBursts::14 17147 # Per bank write bursts system.physmem.perBankWrBursts::15 17103 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 410940401000 # Total gap between requests +system.physmem.totGap 413668533000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 380009 # Read request sizes (log2) +system.physmem.readPktSize::6 380011 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292569 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 378252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292567 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 378248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,40 +144,40 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see @@ -193,126 +193,128 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 142331 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.240383 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.797095 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.472154 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 51326 36.06% 36.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38738 27.22% 63.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13057 9.17% 72.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7891 5.54% 78.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5698 4.00% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3672 2.58% 84.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3107 2.18% 86.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2648 1.86% 88.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16194 11.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 142331 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17261 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.992932 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 228.052387 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17249 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 142473 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 301.943638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.238649 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.808189 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 51183 35.92% 35.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38564 27.07% 62.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13147 9.23% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8365 5.87% 78.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5777 4.05% 82.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3877 2.72% 84.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2993 2.10% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2580 1.81% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15987 11.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 142473 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17260 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.993917 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 228.515702 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17249 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17261 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17261 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.948207 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.879580 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.601828 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17058 98.82% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 154 0.89% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 25 0.14% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 10 0.06% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 4 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17260 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17260 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.949189 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.879017 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.574623 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17060 98.84% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 147 0.85% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 31 0.18% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 6 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::120-123 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17261 # Writes before turning the bus around for reads -system.physmem.totQLat 4019056000 # Total ticks spent queuing -system.physmem.totMemAccLat 11137324750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1898205000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10586.46 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17260 # Writes before turning the bus around for reads +system.physmem.totQLat 4063422250 # Total ticks spent queuing +system.physmem.totMemAccLat 11181522250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1898160000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10703.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29336.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 59.13 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 59.18 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.56 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29453.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 58.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 58.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.26 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.82 # Data bus utilization in percentage +system.physmem.busUtil 0.81 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.74 # Average write queue length when enqueuing -system.physmem.readRowHits 314673 # Number of row buffer hits during reads -system.physmem.writeRowHits 215171 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.55 # Row buffer hit rate for writes -system.physmem.avgGap 610992.93 # Average gap between requests -system.physmem.pageHitRate 78.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 547495200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 298732500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1495119600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 953078400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26840271120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 61546767165 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 192572713500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 284254177485 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.725104 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 319820574750 # Time in different power states -system.physmem_0.memoryStateTime::REF 13722020000 # Time in different power states +system.physmem.avgWrQLen 20.80 # Average write queue length when enqueuing +system.physmem.readRowHits 314502 # Number of row buffer hits during reads +system.physmem.writeRowHits 215198 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.56 # Row buffer hit rate for writes +system.physmem.avgGap 615049.16 # Average gap between requests +system.physmem.pageHitRate 78.80 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 548387280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 299219250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1495111800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 953220960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27018775680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62462923605 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 193408851750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 286186490325 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.826263 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 321201361250 # Time in different power states +system.physmem_0.memoryStateTime::REF 13813280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 77392866750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78653522500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 528262560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 288238500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1465495200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 942392880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26840271120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 58539586815 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 195210595500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 283814842575 # Total energy per rank (pJ) -system.physmem_1.averagePower 690.655981 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 324225356250 # Time in different power states -system.physmem_1.memoryStateTime::REF 13722020000 # Time in different power states +system.physmem_1.actEnergy 528708600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 288481875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1465971000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 942457680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 27018775680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 59403829365 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 196092272250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 285740496450 # Total energy per rank (pJ) +system.physmem_1.averagePower 690.748106 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 325682433750 # Time in different power states +system.physmem_1.memoryStateTime::REF 13813280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 72987820500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 74172457500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 124267347 # Number of BP lookups -system.cpu.branchPred.condPredicted 87926966 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6405633 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71910290 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67438494 # Number of BTB hits +system.cpu.branchPred.lookups 124268150 # Number of BP lookups +system.cpu.branchPred.condPredicted 87927054 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6406473 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71778224 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67442624 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.781424 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15062581 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1126311 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.959728 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15063408 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1126260 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149395037 # DTB read hits -system.cpu.dtb.read_misses 569044 # DTB read misses +system.cpu.dtb.read_hits 149394774 # DTB read hits +system.cpu.dtb.read_misses 568338 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 149964081 # DTB read accesses -system.cpu.dtb.write_hits 57322306 # DTB write hits -system.cpu.dtb.write_misses 67257 # DTB write misses +system.cpu.dtb.read_accesses 149963112 # DTB read accesses +system.cpu.dtb.write_hits 57322660 # DTB write hits +system.cpu.dtb.write_misses 67060 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57389563 # DTB write accesses -system.cpu.dtb.data_hits 206717343 # DTB hits -system.cpu.dtb.data_misses 636301 # DTB misses +system.cpu.dtb.write_accesses 57389720 # DTB write accesses +system.cpu.dtb.data_hits 206717434 # DTB hits +system.cpu.dtb.data_misses 635398 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 207353644 # DTB accesses -system.cpu.itb.fetch_hits 226796884 # ITB hits +system.cpu.dtb.data_accesses 207352832 # DTB accesses +system.cpu.itb.fetch_hits 226805869 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 226796932 # ITB accesses +system.cpu.itb.fetch_accesses 226805917 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -326,66 +328,66 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.numCycles 821880966 # number of cpu cycles simulated +system.cpu.numCycles 827337243 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12979255 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12980749 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.343159 # CPI: cycles per instruction -system.cpu.ipc 0.744514 # IPC: instructions per cycle -system.cpu.tickCycles 741712966 # Number of cycles that the object actually ticked -system.cpu.idleCycles 80168000 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 2535450 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.778260 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202631199 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2539546 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.790324 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1608227250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.778260 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997993 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997993 # Average percentage of cache occupancy +system.cpu.cpi 1.352076 # CPI: cycles per instruction +system.cpu.ipc 0.739604 # IPC: instructions per cycle +system.cpu.tickCycles 741744427 # Number of cycles that the object actually ticked +system.cpu.idleCycles 85592816 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 2535433 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.647440 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202630848 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2539529 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.790720 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1642835250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.647440 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 830 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3144 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 414706244 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 414706244 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146964985 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146964985 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 55666214 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666214 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 202631199 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 202631199 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 202631199 # number of overall hits -system.cpu.dcache.overall_hits::total 202631199 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1908330 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1908330 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1543820 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543820 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3452150 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3452150 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3452150 # number of overall misses -system.cpu.dcache.overall_misses::total 3452150 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36414832750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36414832750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 44905898000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 44905898000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 81320730750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 81320730750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 81320730750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 81320730750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 148873315 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 148873315 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 414705331 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 414705331 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 146964653 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146964653 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 55666195 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666195 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 202630848 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 202630848 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 202630848 # number of overall hits +system.cpu.dcache.overall_hits::total 202630848 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1908214 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1908214 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1543839 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543839 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3452053 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3452053 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3452053 # number of overall misses +system.cpu.dcache.overall_misses::total 3452053 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37787863500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37787863500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 48074024750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 48074024750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 85861888250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 85861888250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 85861888250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 85861888250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 148872867 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148872867 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 206083349 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206083349 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 206083349 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206083349 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 206082901 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206082901 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 206082901 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206082901 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012818 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012818 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026985 # miss rate for WriteReq accesses @@ -394,14 +396,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016751 system.cpu.dcache.demand_miss_rate::total 0.016751 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016751 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016751 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19082.041759 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19082.041759 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29087.521861 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29087.521861 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23556.546138 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23556.546138 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23556.546138 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23556.546138 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19802.738844 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19802.738844 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31139.273428 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31139.273428 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24872.702780 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24872.702780 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24872.702780 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24872.702780 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -410,32 +412,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2340060 # number of writebacks -system.cpu.dcache.writebacks::total 2340060 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143560 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 143560 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769044 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769044 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 912604 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 912604 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 912604 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 912604 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764770 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764770 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774776 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 774776 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2539546 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2539546 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2539546 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2539546 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30222614500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30222614500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21167535500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 21167535500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 51390150000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 51390150000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51390150000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 51390150000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2340050 # number of writebacks +system.cpu.dcache.writebacks::total 2340050 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143464 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 143464 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769060 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769060 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 912524 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 912524 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 912524 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 912524 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764750 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764750 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774779 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 774779 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2539529 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2539529 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2539529 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2539529 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32323432750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32323432750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23036899500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23036899500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55360332250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 55360332250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55360332250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 55360332250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011854 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011854 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses @@ -444,69 +446,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012323 system.cpu.dcache.demand_mshr_miss_rate::total 0.012323 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012323 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012323 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17125.525989 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17125.525989 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27320.845638 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27320.845638 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20235.959498 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20235.959498 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20235.959498 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20235.959498 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18316.153988 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18316.153988 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29733.510459 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29733.510459 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21799.448736 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21799.448736 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21799.448736 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21799.448736 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 3192 # number of replacements -system.cpu.icache.tags.tagsinuse 1117.017357 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 226791863 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5021 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45168.664210 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 3160 # number of replacements +system.cpu.icache.tags.tagsinuse 1117.931154 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 226800880 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4989 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 45460.188415 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1117.017357 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545419 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545419 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1117.931154 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545865 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545865 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 77 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 453598789 # Number of tag accesses -system.cpu.icache.tags.data_accesses 453598789 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 226791863 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 226791863 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 226791863 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 226791863 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 226791863 # number of overall hits -system.cpu.icache.overall_hits::total 226791863 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5021 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5021 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5021 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5021 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5021 # number of overall misses -system.cpu.icache.overall_misses::total 5021 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 229227250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 229227250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 229227250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 229227250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 229227250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 229227250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 226796884 # 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miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45653.704441 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 45653.704441 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 45653.704441 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 45653.704441 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 45653.704441 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 45653.704441 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49564.341551 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49564.341551 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49564.341551 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22549899250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 155967750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22393931500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22549899250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.532165 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.096917 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098154 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265541 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265541 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.532165 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148584 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.149341 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.532165 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148584 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.149341 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58371.163922 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60364.425843 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60333.707745 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58506.964274 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58506.964274 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58371.163922 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59347.298304 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59340.434700 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58371.163922 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59347.298304 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59340.434700 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2670 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 377341 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 380011 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2670 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 377341 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380011 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175922000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11655046250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11830968250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13719523500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13719523500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175922000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25374569750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25550491750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175922000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25374569750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25550491750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.535177 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.096921 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098158 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265538 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265538 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.535177 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148587 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149345 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.535177 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148587 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149345 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65888.389513 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68271.951791 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68235.246705 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66397.856514 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66397.856514 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65888.389513 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67245.726677 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67236.189873 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65888.389513 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67245.726677 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67236.189873 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1766435 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1766435 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2340060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 778132 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 778132 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10042 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419152 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7429194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 321344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312294784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312616128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 1766378 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1766378 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2340050 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 778140 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 778140 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9978 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419108 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7429086 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 319296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312293056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312612352 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4884627 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 4884568 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4884627 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4884568 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4884627 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4782373500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4884568 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4782334000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8080250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8035000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3891629500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3891583750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadReq 173383 # Transaction distribution -system.membus.trans_dist::ReadResp 173383 # Transaction distribution -system.membus.trans_dist::Writeback 292569 # Transaction distribution +system.membus.trans_dist::ReadReq 173385 # Transaction distribution +system.membus.trans_dist::ReadResp 173385 # Transaction distribution +system.membus.trans_dist::Writeback 292567 # Transaction distribution system.membus.trans_dist::ReadExReq 206626 # Transaction distribution system.membus.trans_dist::ReadExResp 206626 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052587 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1052587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052589 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1052589 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044992 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 43044992 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) @@ -736,9 +738,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 672578 # Request fanout histogram -system.membus.reqLayer0.occupancy 3222626500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3617752750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.reqLayer0.occupancy 1986204500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2010997250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 441853c88..8128561b2 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.365317 # Number of seconds simulated -sim_ticks 365317233000 # Number of ticks simulated -final_tick 365317233000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.366359 # Number of seconds simulated +sim_ticks 366358704500 # Number of ticks simulated +final_tick 366358704500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157262 # Simulator instruction rate (inst/s) -host_op_rate 170335 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 113407877 # Simulator tick rate (ticks/s) -host_mem_usage 304680 # Number of bytes of host memory used -host_seconds 3221.27 # Real time elapsed on the host +host_inst_rate 242855 # Simulator instruction rate (inst/s) +host_op_rate 263044 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 175631724 # Simulator tick rate (ticks/s) +host_mem_usage 316616 # Number of bytes of host memory used +host_seconds 2085.95 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated sim_ops 548695378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 222144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9003904 # Number of bytes read from this memory -system.physmem.bytes_read::total 9226048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 222144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 222144 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6179904 # Number of bytes written to this memory -system.physmem.bytes_written::total 6179904 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3471 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140686 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144157 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96561 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96561 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 608085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24646809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25254894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 608085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 608085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16916541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16916541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16916541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 608085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24646809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42171435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144157 # Number of read requests accepted -system.physmem.writeReqs 96561 # Number of write requests accepted -system.physmem.readBursts 144157 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96561 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9219904 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue -system.physmem.bytesWritten 6178688 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9226048 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6179904 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 221696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9006016 # Number of bytes read from this memory +system.physmem.bytes_read::total 9227712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6179648 # Number of bytes written to this memory +system.physmem.bytes_written::total 6179648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3464 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140719 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144183 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96557 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96557 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 605134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24582509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25187642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 605134 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 605134 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 16867753 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16867753 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 16867753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 605134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24582509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42055395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144183 # Number of read requests accepted +system.physmem.writeReqs 96557 # Number of write requests accepted +system.physmem.readBursts 144183 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96557 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9220288 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue +system.physmem.bytesWritten 6178496 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9227712 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6179648 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 9347 # Per bank write bursts -system.physmem.perBankRdBursts::1 8970 # Per bank write bursts -system.physmem.perBankRdBursts::2 8998 # Per bank write bursts -system.physmem.perBankRdBursts::3 8695 # Per bank write bursts +system.physmem.perBankRdBursts::1 9007 # Per bank write bursts +system.physmem.perBankRdBursts::2 8992 # Per bank write bursts +system.physmem.perBankRdBursts::3 8698 # Per bank write bursts system.physmem.perBankRdBursts::4 9455 # Per bank write bursts system.physmem.perBankRdBursts::5 9342 # Per bank write bursts -system.physmem.perBankRdBursts::6 8947 # Per bank write bursts -system.physmem.perBankRdBursts::7 8101 # Per bank write bursts -system.physmem.perBankRdBursts::8 8578 # Per bank write bursts +system.physmem.perBankRdBursts::6 8946 # Per bank write bursts +system.physmem.perBankRdBursts::7 8102 # Per bank write bursts +system.physmem.perBankRdBursts::8 8570 # Per bank write bursts system.physmem.perBankRdBursts::9 8679 # Per bank write bursts -system.physmem.perBankRdBursts::10 8774 # Per bank write bursts -system.physmem.perBankRdBursts::11 9477 # Per bank write bursts +system.physmem.perBankRdBursts::10 8773 # Per bank write bursts +system.physmem.perBankRdBursts::11 9476 # Per bank write bursts system.physmem.perBankRdBursts::12 9374 # Per bank write bursts -system.physmem.perBankRdBursts::13 9525 # Per bank write bursts +system.physmem.perBankRdBursts::13 9521 # Per bank write bursts system.physmem.perBankRdBursts::14 8712 # Per bank write bursts -system.physmem.perBankRdBursts::15 9087 # Per bank write bursts -system.physmem.perBankWrBursts::0 6196 # Per bank write bursts -system.physmem.perBankWrBursts::1 6092 # Per bank write bursts -system.physmem.perBankWrBursts::2 6006 # Per bank write bursts -system.physmem.perBankWrBursts::3 5813 # Per bank write bursts +system.physmem.perBankRdBursts::15 9073 # Per bank write bursts +system.physmem.perBankWrBursts::0 6191 # Per bank write bursts +system.physmem.perBankWrBursts::1 6098 # Per bank write bursts +system.physmem.perBankWrBursts::2 6005 # Per bank write bursts +system.physmem.perBankWrBursts::3 5815 # Per bank write bursts system.physmem.perBankWrBursts::4 6163 # Per bank write bursts -system.physmem.perBankWrBursts::5 6172 # Per bank write bursts +system.physmem.perBankWrBursts::5 6174 # Per bank write bursts system.physmem.perBankWrBursts::6 6014 # Per bank write bursts -system.physmem.perBankWrBursts::7 5493 # Per bank write bursts -system.physmem.perBankWrBursts::8 5728 # Per bank write bursts -system.physmem.perBankWrBursts::9 5823 # Per bank write bursts -system.physmem.perBankWrBursts::10 5962 # Per bank write bursts +system.physmem.perBankWrBursts::7 5494 # Per bank write bursts +system.physmem.perBankWrBursts::8 5727 # Per bank write bursts +system.physmem.perBankWrBursts::9 5822 # Per bank write bursts +system.physmem.perBankWrBursts::10 5961 # Per bank write bursts system.physmem.perBankWrBursts::11 6445 # Per bank write bursts system.physmem.perBankWrBursts::12 6308 # Per bank write bursts -system.physmem.perBankWrBursts::13 6282 # Per bank write bursts -system.physmem.perBankWrBursts::14 5997 # Per bank write bursts -system.physmem.perBankWrBursts::15 6048 # Per bank write bursts +system.physmem.perBankWrBursts::13 6277 # Per bank write bursts +system.physmem.perBankWrBursts::14 5998 # Per bank write bursts +system.physmem.perBankWrBursts::15 6047 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 365317203500 # Total gap between requests +system.physmem.totGap 366358675500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144157 # Read request sizes (log2) +system.physmem.readPktSize::6 144183 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96561 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96557 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,37 +144,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2930 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 3119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -193,110 +193,112 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65080 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 236.601352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.588709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 242.751381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24737 38.01% 38.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18138 27.87% 65.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6930 10.65% 76.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7871 12.09% 88.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2125 3.27% 91.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1134 1.74% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 708 1.09% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 644 0.99% 95.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2793 4.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65080 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5572 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.854092 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 382.114973 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5569 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65205 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 236.159558 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.546491 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.906067 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24752 37.96% 37.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18185 27.89% 65.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7019 10.76% 76.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7903 12.12% 88.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2061 3.16% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1167 1.79% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 745 1.14% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 604 0.93% 95.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2769 4.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65205 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5568 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.873563 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 382.195910 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5565 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.04% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5572 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5572 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.326274 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.230410 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.286782 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2628 47.16% 47.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2789 50.05% 97.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 53 0.95% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 30 0.54% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 23 0.41% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 9 0.16% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 9 0.16% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 6 0.11% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 7 0.13% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 3 0.05% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 4 0.07% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 2 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 2 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 2 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5568 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5568 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.338182 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.234627 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.449204 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2631 47.25% 47.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2778 49.89% 97.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 61 1.10% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 29 0.52% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 20 0.36% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 10 0.18% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 6 0.11% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 7 0.13% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 5 0.09% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 2 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 5 0.09% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 2 0.04% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 2 0.04% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 2 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 2 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5572 # Writes before turning the bus around for reads -system.physmem.totQLat 1534207250 # Total ticks spent queuing -system.physmem.totMemAccLat 4235351000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720305000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10649.71 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5568 # Writes before turning the bus around for reads +system.physmem.totQLat 1536843000 # Total ticks spent queuing +system.physmem.totMemAccLat 4238099250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720335000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10667.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29399.71 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 16.91 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.92 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29417.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 16.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 16.87 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.29 # Average write queue length when enqueuing -system.physmem.readRowHits 111019 # Number of row buffer hits during reads -system.physmem.writeRowHits 64498 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.06 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes -system.physmem.avgGap 1517614.82 # Average gap between requests -system.physmem.pageHitRate 72.94 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 247892400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135258750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 560445600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 310566960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23860618080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47138982615 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 177839337750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 250093102155 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.594758 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 295545266000 # Time in different power states -system.physmem_0.memoryStateTime::REF 12198680000 # Time in different power states +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 20.79 # Average write queue length when enqueuing +system.physmem.readRowHits 110982 # Number of row buffer hits during reads +system.physmem.writeRowHits 64419 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.03 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.72 # Row buffer hit rate for writes +system.physmem.avgGap 1521802.26 # Average gap between requests +system.physmem.pageHitRate 72.89 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 248111640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135378375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 560734200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 310741920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23928765120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47516601060 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 178134108000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 250834440315 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.668623 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 296034178750 # Time in different power states +system.physmem_0.memoryStateTime::REF 12233260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 57571800000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 58091210000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 244014120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133142625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 563058600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 314817840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23860618080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 46734210225 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 178194401250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 250044262740 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.461067 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 296138902500 # Time in different power states -system.physmem_1.memoryStateTime::REF 12198680000 # Time in different power states +system.physmem_1.actEnergy 244838160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133592250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562988400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 314830800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23928765120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46994125095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 178592423250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 250771563075 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.496987 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 296797282750 # Time in different power states +system.physmem_1.memoryStateTime::REF 12233260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 56977968750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57328110000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 132578917 # Number of BP lookups -system.cpu.branchPred.condPredicted 98507789 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6555100 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 69037584 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64855119 # Number of BTB hits +system.cpu.branchPred.lookups 132587783 # Number of BP lookups +system.cpu.branchPred.condPredicted 98513206 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6558220 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68845364 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64852055 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.941756 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 10014942 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17500 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.199596 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 10016928 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17846 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -415,74 +417,74 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 730634466 # number of cpu cycles simulated +system.cpu.numCycles 732717409 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582155 # Number of instructions committed system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13461155 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13466110 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.442282 # CPI: cycles per instruction -system.cpu.ipc 0.693346 # IPC: instructions per cycle -system.cpu.tickCycles 695780172 # Number of cycles that the object actually ticked -system.cpu.idleCycles 34854294 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139812 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.074819 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171281876 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1143908 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.733961 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4867376000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4071.074819 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993915 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993915 # Average percentage of cache occupancy +system.cpu.cpi 1.446394 # CPI: cycles per instruction +system.cpu.ipc 0.691375 # IPC: instructions per cycle +system.cpu.tickCycles 695820940 # Number of cycles that the object actually ticked +system.cpu.idleCycles 36896469 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139887 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.954708 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171283476 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1143983 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.725543 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4900143250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.954708 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993885 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993885 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3506 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346818362 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346818362 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114766084 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114766084 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53538710 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538710 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 346821767 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346821767 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114767712 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114767712 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53538682 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538682 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168304794 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168304794 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168304794 # number of overall hits -system.cpu.dcache.overall_hits::total 168304794 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 854755 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854755 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 700596 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700596 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1555351 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1555351 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1555351 # number of overall misses -system.cpu.dcache.overall_misses::total 1555351 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13707430482 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13707430482 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20521575250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20521575250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34229005732 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34229005732 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34229005732 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34229005732 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115620839 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115620839 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168306394 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168306394 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168306394 # number of overall hits +system.cpu.dcache.overall_hits::total 168306394 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 854792 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854792 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700624 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700624 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1555416 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1555416 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1555416 # number of overall misses +system.cpu.dcache.overall_misses::total 1555416 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024046732 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14024046732 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22031424000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22031424000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36055470732 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36055470732 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36055470732 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36055470732 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115622504 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115622504 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169860145 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169860145 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169860145 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169860145 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169861810 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169861810 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169861810 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169861810 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007393 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012917 # miss rate for WriteReq accesses @@ -491,14 +493,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.009157 system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009157 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16036.677740 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16036.677740 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29291.596369 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29291.596369 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22007.254782 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22007.254782 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22007.254782 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22007.254782 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.385100 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.385100 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31445.431501 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31445.431501 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23180.596530 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23180.596530 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23180.596530 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23180.596530 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -507,103 +509,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068525 # number of writebacks -system.cpu.dcache.writebacks::total 1068525 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66991 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66991 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344452 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344452 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 411443 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411443 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 411443 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411443 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787764 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787764 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356144 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356144 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1143908 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1143908 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1143908 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1143908 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11252029015 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11252029015 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10073374750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10073374750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21325403765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21325403765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21325403765 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21325403765 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006813 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 1068568 # number of writebacks +system.cpu.dcache.writebacks::total 1068568 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66956 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66956 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344477 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344477 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 411433 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411433 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 411433 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411433 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787836 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 787836 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356147 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356147 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1143983 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1143983 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1143983 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1143983 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11930645015 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11930645015 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10967643750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10967643750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22898288765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22898288765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22898288765 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22898288765 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006814 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006814 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006566 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006734 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006734 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14283.502439 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14283.502439 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28284.555545 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28284.555545 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18642.586436 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18642.586436 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18642.586436 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18642.586436 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006735 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006735 # 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Number of misses that were no-allocate -system.cpu.icache.tags.replacements 17690 # number of replacements -system.cpu.icache.tags.tagsinuse 1190.635807 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 200942292 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19563 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10271.547922 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 17670 # number of replacements +system.cpu.icache.tags.tagsinuse 1190.214047 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 200949213 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19542 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10282.939975 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1190.635807 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25299.406253 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25299.406253 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25299.406253 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25299.406253 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -612,122 +614,122 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19563 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67183.475579 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67175.561613 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 807073 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 807073 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1068525 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356398 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39126 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356341 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3395467 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141595712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142847744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 807125 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 807125 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1068568 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356400 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356400 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39084 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356534 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3395618 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1250688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141603264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142853952 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2231996 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2232093 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 2231996 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 2232093 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2231996 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2184523000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2232093 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2184614500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30038495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30006497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1744651235 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1744748235 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 43289 # Transaction distribution -system.membus.trans_dist::ReadResp 43289 # Transaction distribution -system.membus.trans_dist::Writeback 96561 # Transaction distribution -system.membus.trans_dist::ReadExReq 100868 # Transaction distribution -system.membus.trans_dist::ReadExResp 100868 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384875 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 384875 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15405952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15405952 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 43319 # Transaction distribution +system.membus.trans_dist::ReadResp 43319 # Transaction distribution +system.membus.trans_dist::Writeback 96557 # Transaction distribution +system.membus.trans_dist::ReadExReq 100864 # Transaction distribution +system.membus.trans_dist::ReadExResp 100864 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384923 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 384923 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15407360 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15407360 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 240718 # Request fanout histogram +system.membus.snoop_fanout::samples 240740 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 240718 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 240740 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 240718 # Request fanout histogram -system.membus.reqLayer0.occupancy 1081999000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1366864750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_fanout::total 240740 # Request fanout histogram +system.membus.reqLayer0.occupancy 679202000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 765364000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index e36a9b419..17deb175b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.232212 # Number of seconds simulated -sim_ticks 232211555000 # Number of ticks simulated -final_tick 232211555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233382 # Number of seconds simulated +sim_ticks 233381523500 # Number of ticks simulated +final_tick 233381523500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135087 # Simulator instruction rate (inst/s) -host_op_rate 146347 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62087234 # Simulator tick rate (ticks/s) -host_mem_usage 317808 # Number of bytes of host memory used -host_seconds 3740.09 # Real time elapsed on the host +host_inst_rate 139639 # Simulator instruction rate (inst/s) +host_op_rate 151279 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64502789 # Simulator tick rate (ticks/s) +host_mem_usage 317896 # Number of bytes of host memory used +host_seconds 3618.16 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 547350944 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 681088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9254400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16474624 # Number of bytes read from this memory -system.physmem.bytes_read::total 26410112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 681088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 681088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18728832 # Number of bytes written to this memory -system.physmem.bytes_written::total 18728832 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10642 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144600 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257416 # Number of read requests responded to by this memory -system.physmem.num_reads::total 412658 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292638 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292638 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2933050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39853314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70946616 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 113732979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2933050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2933050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80654178 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80654178 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80654178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2933050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39853314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70946616 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 194387157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 412658 # Number of read requests accepted -system.physmem.writeReqs 292638 # Number of write requests accepted -system.physmem.readBursts 412658 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292638 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26271168 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 138944 # Total number of bytes read from write queue -system.physmem.bytesWritten 18727424 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26410112 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18728832 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2171 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 689856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9181056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16498240 # Number of bytes read from this memory +system.physmem.bytes_read::total 26369152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 689856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 689856 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18710272 # Number of bytes written to this memory +system.physmem.bytes_written::total 18710272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10779 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143454 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257785 # Number of read requests responded to by this memory +system.physmem.num_reads::total 412018 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292348 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292348 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2955915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39339258 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70692143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 112987316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2955915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2955915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80170322 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80170322 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80170322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2955915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39339258 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70692143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193157639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 412018 # Number of read requests accepted +system.physmem.writeReqs 292348 # Number of write requests accepted +system.physmem.readBursts 412018 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292348 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26233536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 135616 # Total number of bytes read from write queue +system.physmem.bytesWritten 18708736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26369152 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18710272 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2119 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26576 # Per bank write bursts -system.physmem.perBankRdBursts::1 25575 # Per bank write bursts -system.physmem.perBankRdBursts::2 25174 # Per bank write bursts -system.physmem.perBankRdBursts::3 24876 # Per bank write bursts -system.physmem.perBankRdBursts::4 27202 # Per bank write bursts -system.physmem.perBankRdBursts::5 26589 # Per bank write bursts -system.physmem.perBankRdBursts::6 25428 # Per bank write bursts -system.physmem.perBankRdBursts::7 24234 # Per bank write bursts -system.physmem.perBankRdBursts::8 25846 # Per bank write bursts -system.physmem.perBankRdBursts::9 24812 # Per bank write bursts -system.physmem.perBankRdBursts::10 25055 # Per bank write bursts -system.physmem.perBankRdBursts::11 26081 # Per bank write bursts -system.physmem.perBankRdBursts::12 26502 # Per bank write bursts -system.physmem.perBankRdBursts::13 25872 # Per bank write bursts -system.physmem.perBankRdBursts::14 25198 # Per bank write bursts -system.physmem.perBankRdBursts::15 25467 # Per bank write bursts -system.physmem.perBankWrBursts::0 18795 # Per bank write bursts -system.physmem.perBankWrBursts::1 18343 # Per bank write bursts -system.physmem.perBankWrBursts::2 17877 # Per bank write bursts -system.physmem.perBankWrBursts::3 18076 # Per bank write bursts -system.physmem.perBankWrBursts::4 18802 # Per bank write bursts -system.physmem.perBankWrBursts::5 18306 # Per bank write bursts -system.physmem.perBankWrBursts::6 18071 # Per bank write bursts -system.physmem.perBankWrBursts::7 17638 # Per bank write bursts -system.physmem.perBankWrBursts::8 18138 # Per bank write bursts -system.physmem.perBankWrBursts::9 17849 # Per bank write bursts -system.physmem.perBankWrBursts::10 18079 # Per bank write bursts -system.physmem.perBankWrBursts::11 18708 # Per bank write bursts -system.physmem.perBankWrBursts::12 18879 # Per bank write bursts -system.physmem.perBankWrBursts::13 18261 # Per bank write bursts -system.physmem.perBankWrBursts::14 18465 # Per bank write bursts -system.physmem.perBankWrBursts::15 18329 # Per bank write bursts +system.physmem.perBankRdBursts::0 26413 # Per bank write bursts +system.physmem.perBankRdBursts::1 25441 # Per bank write bursts +system.physmem.perBankRdBursts::2 25280 # Per bank write bursts +system.physmem.perBankRdBursts::3 24861 # Per bank write bursts +system.physmem.perBankRdBursts::4 26943 # Per bank write bursts +system.physmem.perBankRdBursts::5 26409 # Per bank write bursts +system.physmem.perBankRdBursts::6 25350 # Per bank write bursts +system.physmem.perBankRdBursts::7 24226 # Per bank write bursts +system.physmem.perBankRdBursts::8 25719 # Per bank write bursts +system.physmem.perBankRdBursts::9 24800 # Per bank write bursts +system.physmem.perBankRdBursts::10 25359 # Per bank write bursts +system.physmem.perBankRdBursts::11 26216 # Per bank write bursts +system.physmem.perBankRdBursts::12 26433 # Per bank write bursts +system.physmem.perBankRdBursts::13 25856 # Per bank write bursts +system.physmem.perBankRdBursts::14 25009 # Per bank write bursts +system.physmem.perBankRdBursts::15 25584 # Per bank write bursts +system.physmem.perBankWrBursts::0 18684 # Per bank write bursts +system.physmem.perBankWrBursts::1 18331 # Per bank write bursts +system.physmem.perBankWrBursts::2 18001 # Per bank write bursts +system.physmem.perBankWrBursts::3 18053 # Per bank write bursts +system.physmem.perBankWrBursts::4 18581 # Per bank write bursts +system.physmem.perBankWrBursts::5 18287 # Per bank write bursts +system.physmem.perBankWrBursts::6 18028 # Per bank write bursts +system.physmem.perBankWrBursts::7 17667 # Per bank write bursts +system.physmem.perBankWrBursts::8 18026 # Per bank write bursts +system.physmem.perBankWrBursts::9 17689 # Per bank write bursts +system.physmem.perBankWrBursts::10 18246 # Per bank write bursts +system.physmem.perBankWrBursts::11 18799 # Per bank write bursts +system.physmem.perBankWrBursts::12 18831 # Per bank write bursts +system.physmem.perBankWrBursts::13 18312 # Per bank write bursts +system.physmem.perBankWrBursts::14 18349 # Per bank write bursts +system.physmem.perBankWrBursts::15 18440 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 232211534500 # Total gap between requests +system.physmem.totGap 233381437000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 412658 # Read request sizes (log2) +system.physmem.readPktSize::6 412018 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292638 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 311514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5306 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292348 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 312437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -148,30 +148,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 19068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 19781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -197,102 +197,103 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 307877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 146.155822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.817953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 181.897933 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 185209 60.16% 60.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 81919 26.61% 86.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16650 5.41% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7285 2.37% 94.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4666 1.52% 96.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2373 0.77% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1833 0.60% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1570 0.51% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6372 2.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 307877 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17388 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.607430 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 116.348412 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 17387 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 307121 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 146.330964 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.916756 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 182.072957 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 184589 60.10% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 81854 26.65% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16654 5.42% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7226 2.35% 94.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4782 1.56% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2270 0.74% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1753 0.57% 97.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1588 0.52% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6405 2.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 307121 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17353 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.620930 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 116.705820 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 17352 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17388 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17388 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.828617 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.789393 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.188635 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 10816 62.20% 62.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 278 1.60% 63.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5484 31.54% 95.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 506 2.91% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 126 0.72% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 66 0.38% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 41 0.24% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 33 0.19% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 20 0.12% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 12 0.07% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17353 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17353 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.845733 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.805125 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.212117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10719 61.77% 61.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 285 1.64% 63.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5449 31.40% 94.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 585 3.37% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 128 0.74% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 65 0.37% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 37 0.21% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 35 0.20% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 29 0.17% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 15 0.09% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 4 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::31 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17388 # Writes before turning the bus around for reads -system.physmem.totQLat 9526506707 # Total ticks spent queuing -system.physmem.totMemAccLat 17223137957 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2052435000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23207.82 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17353 # Writes before turning the bus around for reads +system.physmem.totQLat 9387910450 # Total ticks spent queuing +system.physmem.totMemAccLat 17073516700 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2049495000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22902.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41957.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 113.13 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.65 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 113.73 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.65 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41652.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 112.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 80.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 112.99 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 80.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.51 # Data bus utilization in percentage +system.physmem.busUtil 1.50 # Data bus utilization in percentage system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.62 # Average write queue length when enqueuing -system.physmem.readRowHits 299737 # Number of row buffer hits during reads -system.physmem.writeRowHits 95481 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.63 # Row buffer hit rate for writes -system.physmem.avgGap 329239.83 # Average gap between requests -system.physmem.pageHitRate 56.21 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1161435240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 633719625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1603960800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 945386640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15166784880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 74505009510 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 73970535750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 167986832445 # Total energy per rank (pJ) -system.physmem_0.averagePower 723.427350 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 122529683190 # Time in different power states -system.physmem_0.memoryStateTime::REF 7753980000 # Time in different power states +system.physmem.avgWrQLen 21.73 # Average write queue length when enqueuing +system.physmem.readRowHits 299659 # Number of row buffer hits during reads +system.physmem.writeRowHits 95432 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.64 # Row buffer hit rate for writes +system.physmem.avgGap 331335.47 # Average gap between requests +system.physmem.pageHitRate 56.26 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1156453200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 631001250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1598134200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 943500960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15243068880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 74948893020 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 74281875750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 168802927260 # Total energy per rank (pJ) +system.physmem_0.averagePower 723.304109 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 123045424463 # Time in different power states +system.physmem_0.memoryStateTime::REF 7792980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 101926029060 # Time in different power states +system.physmem_0.memoryStateTime::ACT 102539140537 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1165888080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 636149250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1597541400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 950557680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15166784880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 73837287855 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 74556205500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 167910414645 # Total energy per rank (pJ) -system.physmem_1.averagePower 723.098525 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 123510236330 # Time in different power states -system.physmem_1.memoryStateTime::REF 7753980000 # Time in different power states +system.physmem_1.actEnergy 1165048920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 635691375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1598610000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 950447520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15243068880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 74482095510 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 74691339000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 168766301205 # Total energy per rank (pJ) +system.physmem_1.averagePower 723.147212 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 123736015873 # Time in different power states +system.physmem_1.memoryStateTime::REF 7792980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 100945998170 # Time in different power states +system.physmem_1.memoryStateTime::ACT 101848756127 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 175052211 # Number of BP lookups -system.cpu.branchPred.condPredicted 131310953 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7443013 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90523756 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83852008 # Number of BTB hits +system.cpu.branchPred.lookups 175093442 # Number of BP lookups +system.cpu.branchPred.condPredicted 131339013 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7445255 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90524838 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83882931 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.629837 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12106573 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104182 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.662890 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12110656 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104163 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,129 +412,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 464423111 # number of cpu cycles simulated +system.cpu.numCycles 466763048 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7829450 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 731665108 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175052211 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95958581 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 448342475 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14938309 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5167 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 75 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11385 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236661621 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34410 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 463657706 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.708988 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.176697 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7833738 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731827371 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175093442 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95993587 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 450556948 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14942959 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 6375 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 162 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 12684 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236728618 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34396 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 465881386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.701216 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.179605 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 91809808 19.80% 19.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132662466 28.61% 48.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57833448 12.47% 60.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181351984 39.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 93942381 20.16% 20.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132696529 28.48% 48.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57859169 12.42% 61.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181383307 38.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 463657706 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.376924 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.575428 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32373161 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 115247897 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 287024980 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22030943 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6980725 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24047273 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496181 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 715717692 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29980742 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6980725 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63423134 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 52089726 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40328416 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276637091 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24198614 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686503661 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13339375 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9395545 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2450716 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1889859 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1786281 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 830901474 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3018793647 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 723833359 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 465881386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.375123 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.567878 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32362328 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 117422213 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 287082190 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22031979 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6982676 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24051776 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496598 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715820836 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 30011268 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6982676 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63423410 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 54356901 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40333857 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276674345 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24110197 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686603373 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13342977 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9430232 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2385222 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1668168 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1866322 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 831029947 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3019214336 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723928049 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 176777723 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544705 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1534955 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42254952 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143502988 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67972899 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12881093 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11309167 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668070815 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978330 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610220228 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5852709 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 122637533 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 318907162 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 698 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 463657706 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.316101 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101419 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176906196 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544708 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1534779 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42310456 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143529227 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67980457 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12876117 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11223865 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668168633 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978333 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610244720 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5860928 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 122748160 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 319249921 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 701 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 465881386 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.309871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101485 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 147083310 31.72% 31.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100037180 21.58% 53.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 146356248 31.57% 84.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63253795 13.64% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6926698 1.49% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 475 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 148726725 31.92% 31.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 101219272 21.73% 53.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145704053 31.27% 84.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63308472 13.59% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6922394 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 470 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 463657706 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 465881386 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71297182 52.75% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 31 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44549866 32.96% 85.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19309097 14.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71926892 52.97% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44548808 32.81% 85.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19308609 14.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413143881 67.70% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 351753 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413151205 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351762 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued @@ -561,84 +562,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134202503 21.99% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62522088 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134213175 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62528575 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610220228 # Type of FU issued -system.cpu.iq.rate 1.313932 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135156176 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.221488 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1825106754 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 793714763 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594959628 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 610244720 # Type of FU issued +system.cpu.iq.rate 1.307397 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135784339 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222508 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1828015800 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 793923222 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594984495 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 745376227 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 746028882 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7281483 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 7272735 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27618232 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25000 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28827 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11112422 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27644471 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25523 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28862 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11119980 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 224691 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19267 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225173 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 19543 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6980725 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22383279 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 635884 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672535669 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6982676 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23041794 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 922625 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672634659 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143502988 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67972899 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489788 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 251092 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 252064 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28827 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3821462 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3734064 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7555526 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599376603 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129568443 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10843625 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 143529227 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67980457 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489791 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 257738 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 528673 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28862 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3822612 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3731799 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7554411 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599400407 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129575642 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10844313 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1486524 # number of nop insts executed -system.cpu.iew.exec_refs 190520911 # number of memory reference insts executed -system.cpu.iew.exec_branches 131371292 # Number of branches executed -system.cpu.iew.exec_stores 60952468 # Number of stores executed -system.cpu.iew.exec_rate 1.290583 # Inst execution rate -system.cpu.iew.wb_sent 596255942 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594959644 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349870966 # num instructions producing a value -system.cpu.iew.wb_consumers 570295631 # num instructions consuming a value +system.cpu.iew.exec_nop 1487693 # number of nop insts executed +system.cpu.iew.exec_refs 190530493 # number of memory reference insts executed +system.cpu.iew.exec_branches 131374378 # Number of branches executed +system.cpu.iew.exec_stores 60954851 # Number of stores executed +system.cpu.iew.exec_rate 1.284164 # Inst execution rate +system.cpu.iew.wb_sent 596279757 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594984511 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349915362 # num instructions producing a value +system.cpu.iew.wb_consumers 570660996 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.281072 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613491 # average fanout of values written-back +system.cpu.iew.wb_rate 1.274704 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613176 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 109920418 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 110032490 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6954584 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 446560356 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.228714 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.894004 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6956452 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 448764802 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.222678 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.888107 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 218012124 48.82% 48.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116021741 25.98% 74.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43540177 9.75% 84.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23444560 5.25% 89.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10920781 2.45% 92.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8059552 1.80% 94.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8487825 1.90% 95.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4237549 0.95% 96.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13836047 3.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 219732753 48.96% 48.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116339584 25.92% 74.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43745322 9.75% 84.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23276938 5.19% 89.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11568250 2.58% 92.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7761637 1.73% 94.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8261110 1.84% 95.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4247723 0.95% 96.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13831485 3.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 446560356 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 448764802 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -684,380 +685,381 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction -system.cpu.commit.bw_lim_events 13836047 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 13831485 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1091332417 # The number of ROB reads -system.cpu.rob.rob_writes 1334357175 # The number of ROB writes -system.cpu.timesIdled 13678 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 765405 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1093653497 # The number of ROB reads +system.cpu.rob.rob_writes 1334601058 # The number of ROB writes +system.cpu.timesIdled 13925 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 881662 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.919217 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.919217 # CPI: Total CPI of All Threads -system.cpu.ipc 1.087882 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.087882 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611063177 # number of integer regfile reads -system.cpu.int_regfile_writes 328106532 # number of integer regfile writes +system.cpu.cpi 0.923848 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.923848 # CPI: Total CPI of All Threads +system.cpu.ipc 1.082429 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.082429 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611089137 # number of integer regfile reads +system.cpu.int_regfile_writes 328121807 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170100255 # number of cc regfile reads -system.cpu.cc_regfile_writes 376532879 # number of cc regfile writes -system.cpu.misc_regfile_reads 217961412 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170187431 # number of cc regfile reads +system.cpu.cc_regfile_writes 376547848 # number of cc regfile writes +system.cpu.misc_regfile_reads 217970630 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2823114 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.633158 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169651956 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2823626 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 60.083012 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 496259500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.633158 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999284 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999284 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2821443 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.630682 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169417803 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2821955 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.035615 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 498977500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.630682 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999279 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999279 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356228622 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356228622 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114681272 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114681272 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51990753 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51990753 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2786 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2786 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488557 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488557 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 356251797 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356251797 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114676407 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114676407 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51761464 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51761464 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2782 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2782 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488559 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488559 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 166672025 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166672025 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 166674811 # number of overall hits -system.cpu.dcache.overall_hits::total 166674811 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4801959 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4801959 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2248553 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2248553 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 166437871 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166437871 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166440653 # number of overall hits +system.cpu.dcache.overall_hits::total 166440653 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4819248 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4819248 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2477842 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2477842 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7050512 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7050512 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7050523 # number of overall misses -system.cpu.dcache.overall_misses::total 7050523 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 53499385357 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 53499385357 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17165986851 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17165986851 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1002500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1002500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 70665372208 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 70665372208 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 70665372208 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 70665372208 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119483231 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119483231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7297090 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7297090 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7297102 # number of overall misses +system.cpu.dcache.overall_misses::total 7297102 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 56184151983 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 56184151983 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18816988488 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18816988488 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1349500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1349500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75001140471 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75001140471 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75001140471 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75001140471 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119495655 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119495655 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2797 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2797 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488623 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488623 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2794 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2794 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173722537 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173722537 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173725334 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173725334 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040189 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040189 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041456 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.041456 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003933 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.003933 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173734961 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173734961 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173737755 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173737755 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040330 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040330 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045684 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045684 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004295 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.004295 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.040585 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.040585 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.040584 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.040584 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11141.158297 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11141.158297 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7634.237152 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7634.237152 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15189.393939 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15189.393939 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10022.729159 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10022.729159 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10022.713522 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10022.713522 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 454984 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10035 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 45.339711 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.042001 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042001 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042001 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042001 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11658.281952 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11658.281952 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7594.103453 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7594.103453 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20446.969697 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20446.969697 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10278.226042 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10278.226042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10278.209140 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10278.209140 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 705176 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 220270 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 3.201416 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2354028 # number of writebacks -system.cpu.dcache.writebacks::total 2354028 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2498261 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2498261 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1728610 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1728610 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2356074 # number of writebacks +system.cpu.dcache.writebacks::total 2356074 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2516883 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2516883 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1958234 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1958234 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4226871 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4226871 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4226871 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4226871 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2303698 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2303698 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519943 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519943 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4475117 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4475117 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4475117 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4475117 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2302365 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2302365 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519608 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519608 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2823641 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2823641 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2823651 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2823651 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25499562714 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 25499562714 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4017408221 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4017408221 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 706750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 706750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29516970935 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29516970935 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29517677685 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29517677685 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019281 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019281 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009586 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009586 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003575 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003575 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016254 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016254 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016254 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016254 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11068.969420 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11068.969420 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7726.631998 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7726.631998 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70675 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70675 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10453.514075 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10453.514075 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10453.727350 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10453.727350 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_misses::cpu.data 2821973 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2821973 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2821983 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2821983 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27555148045 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27555148045 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4324407514 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4324407514 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 652250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 652250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31879555559 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31879555559 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31880207809 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31880207809 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019267 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019267 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009580 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009580 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003579 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003579 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016243 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016243 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016243 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016243 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11968.192726 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11968.192726 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8322.442137 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8322.442137 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65225 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65225 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11296.903110 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11296.903110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11297.094210 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11297.094210 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 73454 # number of replacements -system.cpu.icache.tags.tagsinuse 465.665769 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 236580046 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 73966 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3198.497228 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 114499459250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 465.665769 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.909503 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.909503 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 73466 # number of replacements +system.cpu.icache.tags.tagsinuse 466.200525 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 236646541 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 73978 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3198.877247 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 115003506250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.200525 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.910548 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.910548 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 15 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 473397028 # Number of tag accesses -system.cpu.icache.tags.data_accesses 473397028 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 236580046 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 236580046 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 236580046 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 236580046 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 236580046 # number of overall hits -system.cpu.icache.overall_hits::total 236580046 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 81472 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 81472 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 81472 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 81472 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 81472 # number of overall misses -system.cpu.icache.overall_misses::total 81472 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1465585914 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1465585914 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1465585914 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1465585914 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1465585914 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1465585914 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 236661518 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 236661518 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 236661518 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 236661518 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 236661518 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 236661518 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000344 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000344 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000344 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000344 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000344 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000344 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17988.829463 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17988.829463 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17988.829463 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17988.829463 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17988.829463 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17988.829463 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 164374 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 692 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6271 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 26.211768 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 138.400000 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 473531001 # Number of tag accesses +system.cpu.icache.tags.data_accesses 473531001 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 236646541 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 236646541 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 236646541 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 236646541 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 236646541 # number of overall hits +system.cpu.icache.overall_hits::total 236646541 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 81956 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 81956 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 81956 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 81956 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 81956 # number of overall misses +system.cpu.icache.overall_misses::total 81956 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1579166787 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1579166787 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1579166787 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1579166787 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1579166787 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1579166787 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 236728497 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 236728497 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 236728497 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 236728497 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 236728497 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 236728497 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000346 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000346 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000346 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000346 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000346 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000346 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19268.470728 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19268.470728 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19268.470728 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19268.470728 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19268.470728 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19268.470728 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 192617 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 91 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6539 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.456645 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 22.750000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7479 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 7479 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 710057825 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9879577827 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10589635652 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 710057825 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9879577827 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18910984010 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29500619662 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.060777 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063424 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.080000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.080000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007063 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007063 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.051203 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.053569 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.051203 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.071429 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.071429 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007024 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007024 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050835 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.053259 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050835 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.148555 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58219.159448 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61237.788677 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61025.777861 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 65743.908734 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 65743.908734 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62405.294437 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62405.294437 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58219.159448 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61267.546031 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61058.528060 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58219.159448 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61267.546031 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 65743.908734 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64054.352517 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.148435 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65868.072820 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68647.697938 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68448.690448 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 68612.026652 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 68612.026652 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13751 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13751 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77300.812875 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77300.812875 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.072820 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68868.828741 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68659.095873 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.072820 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68868.828741 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 68612.026652 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68628.915342 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2375885 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2375884 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2354028 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 335698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 25 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 25 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521734 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521734 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 147954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8001330 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8149284 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331369856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 336103360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 335729 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5587370 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.060082 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.237638 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 2374050 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2374049 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2356074 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 317604 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 28 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 28 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 521913 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521913 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 147982 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8000040 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8148022 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4734336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331393856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 336128192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 317637 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5569669 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.057024 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.231888 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 5251672 93.99% 93.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 335698 6.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 5252065 94.30% 94.30% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 317604 5.70% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5587370 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4979864499 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5569669 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4982106500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 112728958 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 112829788 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4257992809 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4256050685 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 408974 # Transaction distribution -system.membus.trans_dist::ReadResp 408974 # Transaction distribution -system.membus.trans_dist::Writeback 292638 # Transaction distribution +system.membus.trans_dist::ReadReq 408353 # Transaction distribution +system.membus.trans_dist::ReadResp 408353 # Transaction distribution +system.membus.trans_dist::Writeback 292348 # Transaction distribution system.membus.trans_dist::UpgradeReq 3 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 3684 # Transaction distribution -system.membus.trans_dist::ReadExResp 3684 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1117960 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1117960 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45138944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45138944 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 3665 # Transaction distribution +system.membus.trans_dist::ReadExResp 3665 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1116390 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1116390 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45079424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45079424 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 705299 # Request fanout histogram +system.membus.snoop_fanout::samples 704369 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 705299 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 704369 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 705299 # Request fanout histogram -system.membus.reqLayer0.occupancy 3281426491 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3862639706 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.7 # Layer utilization (%) +system.membus.snoop_fanout::total 704369 # Request fanout histogram +system.membus.reqLayer0.occupancy 2100254662 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2178151058 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 29aebf258..ac9d5a522 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.279362 # Nu sim_ticks 279362297500 # Number of ticks simulated final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1700410 # Simulator instruction rate (inst/s) -host_op_rate 1841769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 937717572 # Simulator tick rate (ticks/s) -host_mem_usage 304668 # Number of bytes of host memory used -host_seconds 297.92 # Real time elapsed on the host +host_inst_rate 1941586 # Simulator instruction rate (inst/s) +host_op_rate 2102994 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1070717412 # Simulator tick rate (ticks/s) +host_mem_usage 304560 # Number of bytes of host memory used +host_seconds 260.91 # Real time elapsed on the host sim_insts 506581607 # Number of instructions simulated sim_ops 548694828 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 687930749 # Request fanout histogram -system.membus.snoop_fanout::mean 4.750964 # Request fanout histogram +system.membus.snoop_fanout::mean 2.750964 # Request fanout histogram system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 171319374 24.90% 24.90% # Request fanout histogram -system.membus.snoop_fanout::5 516611375 75.10% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 171319374 24.90% 24.90% # Request fanout histogram +system.membus.snoop_fanout::3 516611375 75.10% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 687930749 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index efad42105..f53112701 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.707539 # Number of seconds simulated -sim_ticks 707539023000 # Number of ticks simulated -final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.707538 # Number of seconds simulated +sim_ticks 707538046500 # Number of ticks simulated +final_tick 707538046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1166033 # Simulator instruction rate (inst/s) -host_op_rate 1262762 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1633733414 # Simulator tick rate (ticks/s) -host_mem_usage 312880 # Number of bytes of host memory used -host_seconds 433.08 # Real time elapsed on the host +host_inst_rate 1058036 # Simulator instruction rate (inst/s) +host_op_rate 1145805 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1482416058 # Simulator tick rate (ticks/s) +host_mem_usage 313032 # Number of bytes of host memory used +host_seconds 477.29 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 546878104 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,16 +26,16 @@ system.physmem.num_reads::total 142649 # Nu system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 250559 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12652667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12903226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12652685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12903244 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 250559 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 250559 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8679369 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8679369 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8679369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 8679381 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8679381 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8679381 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12652685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21582625 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1415078046 # number of cpu cycles simulated +system.cpu.numCycles 1415076093 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504986853 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 172745235 # nu system.cpu.num_load_insts 115884756 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1415078045.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1415076092.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 121548301 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548695378 # Class of executed instruction system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4065.318390 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 11716393000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318390 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138917 # n system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11818657500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11818657500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868772000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8868772000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20687429500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20687429500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20687429500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20687429500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) @@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15100.685869 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15100.685869 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.099815 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.099815 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.123900 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18164.123900 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.107952 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18164.107952 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10644672000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10644672000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8334382000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8334382000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18979054000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18979054000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18979107500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18979107500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses @@ -336,24 +336,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13600.685869 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13600.685869 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23394.099815 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23394.099815 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16664.123900 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16664.123900 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16664.156243 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16664.156243 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 983.372001 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 983.372132 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 983.372001 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 983.372132 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id @@ -377,12 +377,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 266342000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 266342000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 266342000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 266342000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 266342000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 266342000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 266293500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 266293500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 266293500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 266293500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 266293500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 266293500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses @@ -395,12 +395,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23117.958511 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23117.958511 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23117.958511 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23117.958511 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23113.748807 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23113.748807 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23113.748807 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23113.748807 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23113.748807 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23113.748807 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -415,38 +415,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243300000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 243300000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243300000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 243300000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243300000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 243300000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249012000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 249012000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249012000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 249012000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249012000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 249012000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21117.958511 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21117.958511 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21613.748807 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21613.748807 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21613.748807 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21613.748807 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21613.748807 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21613.748807 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109895 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27249.394273 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 27249.388139 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 338494923500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23386.993586 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904756 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.495930 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 338494304500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23386.989190 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904965 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.493984 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.713714 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008786 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.109085 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831586 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.831585 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id @@ -479,17 +479,17 @@ system.cpu.l2cache.demand_misses::total 142649 # nu system.cpu.l2cache.overall_misses::cpu.inst 2770 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 139879 # number of overall misses system.cpu.l2cache.overall_misses::total 142649 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144269000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2035873000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2180142000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5245341000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5245341000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 144269000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7281214000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7425483000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 144269000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7281214000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7425483000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 145605500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2054496500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2200102000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5295729000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5295729000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 145605500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7350225500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7495831000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 145605500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7350225500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7495831000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) @@ -514,17 +514,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.123995 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.240431 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.122817 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.123995 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52082.671480 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52088.345913 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52087.970374 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52040.210727 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52040.210727 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52054.224004 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52054.224004 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52565.162455 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52564.833056 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52564.854856 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.121436 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.121436 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52565.162455 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.026358 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52547.378531 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52565.162455 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.026358 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52547.378531 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -546,17 +546,17 @@ system.cpu.l2cache.demand_mshr_misses::total 142649 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2770 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 139879 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 142649 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110883500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564721500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675605000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4031776000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4031776000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110883500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596497500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5707381000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110883500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596497500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5707381000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112218500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1583343000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1695561500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4082164000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4082164000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112218500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5665507000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5777725500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112218500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5665507000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5777725500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049939 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses @@ -568,17 +568,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40030.144404 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.810925 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.568271 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40512.093863 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40510.246898 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40510.369132 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.069449 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.069449 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40512.093863 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40502.913232 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40512.093863 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40502.913232 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution @@ -593,19 +593,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 2215344 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 2215344 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) @@ -633,9 +631,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 238603 # Request fanout histogram -system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 638238328 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 719562500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index be422e790..a1911a66a 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.451526 # Number of seconds simulated -sim_ticks 451526391500 # Number of ticks simulated -final_tick 451526391500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.455304 # Number of seconds simulated +sim_ticks 455304035500 # Number of ticks simulated +final_tick 455304035500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97078 # Simulator instruction rate (inst/s) -host_op_rate 179507 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53010367 # Simulator tick rate (ticks/s) -host_mem_usage 427448 # Number of bytes of host memory used -host_seconds 8517.70 # Real time elapsed on the host +host_inst_rate 97470 # Simulator instruction rate (inst/s) +host_op_rate 180233 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53670129 # Simulator tick rate (ticks/s) +host_mem_usage 427808 # Number of bytes of host memory used +host_seconds 8483.38 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 224960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24535168 # Number of bytes read from this memory -system.physmem.bytes_read::total 24760128 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 224960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 224960 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18817920 # Number of bytes written to this memory -system.physmem.bytes_written::total 18817920 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3515 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383362 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386877 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294030 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294030 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 498221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 54338281 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54836502 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 498221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 41676235 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 41676235 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 41676235 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 498221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 54338281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 96512737 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386877 # Number of read requests accepted -system.physmem.writeReqs 294030 # Number of write requests accepted -system.physmem.readBursts 386877 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294030 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24738496 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue -system.physmem.bytesWritten 18816576 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24760128 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18817920 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 225344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24524608 # Number of bytes read from this memory +system.physmem.bytes_read::total 24749952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 225344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 225344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18812544 # Number of bytes written to this memory +system.physmem.bytes_written::total 18812544 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3521 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383197 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386718 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293946 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293946 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 494931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53864245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54359176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 494931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 494931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41318641 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41318641 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41318641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 494931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53864245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 95677817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386718 # Number of read requests accepted +system.physmem.writeReqs 293946 # Number of write requests accepted +system.physmem.readBursts 386718 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293946 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24728064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21888 # Total number of bytes read from write queue +system.physmem.bytesWritten 18810880 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24749952 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18812544 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 342 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 180174 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24137 # Per bank write bursts -system.physmem.perBankRdBursts::1 26529 # Per bank write bursts -system.physmem.perBankRdBursts::2 24699 # Per bank write bursts -system.physmem.perBankRdBursts::3 24593 # Per bank write bursts -system.physmem.perBankRdBursts::4 23302 # Per bank write bursts -system.physmem.perBankRdBursts::5 23749 # Per bank write bursts -system.physmem.perBankRdBursts::6 24449 # Per bank write bursts -system.physmem.perBankRdBursts::7 24297 # Per bank write bursts -system.physmem.perBankRdBursts::8 23610 # Per bank write bursts -system.physmem.perBankRdBursts::9 23919 # Per bank write bursts -system.physmem.perBankRdBursts::10 24817 # Per bank write bursts -system.physmem.perBankRdBursts::11 24050 # Per bank write bursts -system.physmem.perBankRdBursts::12 23346 # Per bank write bursts -system.physmem.perBankRdBursts::13 22971 # Per bank write bursts -system.physmem.perBankRdBursts::14 24088 # Per bank write bursts -system.physmem.perBankRdBursts::15 23983 # Per bank write bursts -system.physmem.perBankWrBursts::0 18558 # Per bank write bursts -system.physmem.perBankWrBursts::1 19844 # Per bank write bursts -system.physmem.perBankWrBursts::2 18955 # Per bank write bursts -system.physmem.perBankWrBursts::3 18948 # Per bank write bursts -system.physmem.perBankWrBursts::4 18040 # Per bank write bursts -system.physmem.perBankWrBursts::5 18446 # Per bank write bursts -system.physmem.perBankWrBursts::6 18985 # Per bank write bursts -system.physmem.perBankWrBursts::7 18975 # Per bank write bursts -system.physmem.perBankWrBursts::8 18547 # Per bank write bursts -system.physmem.perBankWrBursts::9 18155 # Per bank write bursts -system.physmem.perBankWrBursts::10 18842 # Per bank write bursts -system.physmem.perBankWrBursts::11 17721 # Per bank write bursts -system.physmem.perBankWrBursts::12 17374 # Per bank write bursts -system.physmem.perBankWrBursts::13 16974 # Per bank write bursts -system.physmem.perBankWrBursts::14 17821 # Per bank write bursts -system.physmem.perBankWrBursts::15 17824 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 191861 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24073 # Per bank write bursts +system.physmem.perBankRdBursts::1 26434 # Per bank write bursts +system.physmem.perBankRdBursts::2 24630 # Per bank write bursts +system.physmem.perBankRdBursts::3 24561 # Per bank write bursts +system.physmem.perBankRdBursts::4 23290 # Per bank write bursts +system.physmem.perBankRdBursts::5 23730 # Per bank write bursts +system.physmem.perBankRdBursts::6 24498 # Per bank write bursts +system.physmem.perBankRdBursts::7 24639 # Per bank write bursts +system.physmem.perBankRdBursts::8 23691 # Per bank write bursts +system.physmem.perBankRdBursts::9 23546 # Per bank write bursts +system.physmem.perBankRdBursts::10 24793 # Per bank write bursts +system.physmem.perBankRdBursts::11 24069 # Per bank write bursts +system.physmem.perBankRdBursts::12 23353 # Per bank write bursts +system.physmem.perBankRdBursts::13 23015 # Per bank write bursts +system.physmem.perBankRdBursts::14 24077 # Per bank write bursts +system.physmem.perBankRdBursts::15 23977 # Per bank write bursts +system.physmem.perBankWrBursts::0 18554 # Per bank write bursts +system.physmem.perBankWrBursts::1 19855 # Per bank write bursts +system.physmem.perBankWrBursts::2 18927 # Per bank write bursts +system.physmem.perBankWrBursts::3 18928 # Per bank write bursts +system.physmem.perBankWrBursts::4 18036 # Per bank write bursts +system.physmem.perBankWrBursts::5 18437 # Per bank write bursts +system.physmem.perBankWrBursts::6 18989 # Per bank write bursts +system.physmem.perBankWrBursts::7 19175 # Per bank write bursts +system.physmem.perBankWrBursts::8 18571 # Per bank write bursts +system.physmem.perBankWrBursts::9 17897 # Per bank write bursts +system.physmem.perBankWrBursts::10 18838 # Per bank write bursts +system.physmem.perBankWrBursts::11 17731 # Per bank write bursts +system.physmem.perBankWrBursts::12 17375 # Per bank write bursts +system.physmem.perBankWrBursts::13 16985 # Per bank write bursts +system.physmem.perBankWrBursts::14 17811 # Per bank write bursts +system.physmem.perBankWrBursts::15 17811 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 451526286000 # Total gap between requests +system.physmem.totGap 455304010000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386877 # Read request sizes (log2) +system.physmem.readPktSize::6 386718 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294030 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4703 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293946 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,395 +144,395 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17592 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 17612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 294.912829 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.000830 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.915309 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54902 37.17% 37.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40417 27.37% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13633 9.23% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7488 5.07% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5349 3.62% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3749 2.54% 85.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3045 2.06% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2781 1.88% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16322 11.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147686 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17443 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.159892 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 209.587687 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17430 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 147768 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.634833 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.118109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.876505 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54825 37.10% 37.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40414 27.35% 64.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13687 9.26% 73.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7337 4.97% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5611 3.80% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4054 2.74% 85.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2966 2.01% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2800 1.89% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16074 10.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147768 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17438 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.156612 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 209.316874 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17424 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17443 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17443 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.855415 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.780849 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.647023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17241 98.84% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 150 0.86% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 25 0.14% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 7 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 4 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 2 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 2 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17438 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17438 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.855144 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.781564 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.520616 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17233 98.82% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 149 0.85% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 26 0.15% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 10 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17443 # Writes before turning the bus around for reads -system.physmem.totQLat 4244351250 # Total ticks spent queuing -system.physmem.totMemAccLat 11491957500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1932695000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10980.40 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17438 # Writes before turning the bus around for reads +system.physmem.totQLat 4282128000 # Total ticks spent queuing +system.physmem.totMemAccLat 11526678000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1931880000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11082.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29730.40 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 54.79 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 41.67 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 54.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 41.68 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29832.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 54.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 41.31 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 54.36 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 41.32 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.75 # Data bus utilization in percentage -system.physmem.busUtilRead 0.43 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.33 # Data bus utilization in percentage for writes +system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.42 # Average write queue length when enqueuing -system.physmem.readRowHits 317756 # Number of row buffer hits during reads -system.physmem.writeRowHits 215101 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.16 # Row buffer hit rate for writes -system.physmem.avgGap 663124.75 # Average gap between requests -system.physmem.pageHitRate 78.30 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 569336040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 310649625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1526881200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 976788720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 29491394400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64757369970 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 214110228000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 311742647955 # Total energy per rank (pJ) -system.physmem_0.averagePower 690.421834 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 355630472000 # Time in different power states -system.physmem_0.memoryStateTime::REF 15077400000 # Time in different power states +system.physmem.avgWrQLen 21.49 # Average write queue length when enqueuing +system.physmem.readRowHits 317407 # Number of row buffer hits during reads +system.physmem.writeRowHits 215108 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.15 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.18 # Row buffer hit rate for writes +system.physmem.avgGap 668911.55 # Average gap between requests +system.physmem.pageHitRate 78.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 571588920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 311878875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1527575400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 977734800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 29738046000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 65814252570 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 215448936750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 314390013315 # Total energy per rank (pJ) +system.physmem_0.averagePower 690.509916 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 357849000500 # Time in different power states +system.physmem_0.memoryStateTime::REF 15203500000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 80817135000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 82248835500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 547049160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 298489125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1487951400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 928182240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 29491394400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 62071035210 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 216466682250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 311290783785 # Total energy per rank (pJ) -system.physmem_1.averagePower 689.421031 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 359566067000 # Time in different power states -system.physmem_1.memoryStateTime::REF 15077400000 # Time in different power states +system.physmem_1.actEnergy 545280120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 297523875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1485736200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 926555760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 29738046000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 63167759955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 217770421500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 313931323410 # Total energy per rank (pJ) +system.physmem_1.averagePower 689.502473 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 361727973250 # Time in different power states +system.physmem_1.memoryStateTime::REF 15203500000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 76881477500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 78369769250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 231910847 # Number of BP lookups -system.cpu.branchPred.condPredicted 231910847 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9746486 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 132027793 # Number of BTB lookups -system.cpu.branchPred.BTBHits 129309443 # Number of BTB hits +system.cpu.branchPred.lookups 231646337 # Number of BP lookups +system.cpu.branchPred.condPredicted 231646337 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9741961 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132013407 # Number of BTB lookups +system.cpu.branchPred.BTBHits 129322217 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.941077 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 28045741 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1465755 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.961427 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28025090 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1471468 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 903052797 # number of cpu cycles simulated +system.cpu.numCycles 910608093 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 186172753 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1278263981 # Number of instructions fetch has processed -system.cpu.fetch.Branches 231910847 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 157355184 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 705668368 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20227891 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1132 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 96729 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 811106 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1664 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 49 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 180547715 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2736967 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 902865746 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.633456 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.342016 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 186242841 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1278548490 # Number of instructions fetch has processed +system.cpu.fetch.Branches 231646337 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 157347307 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 713142960 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20218451 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1278 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 97934 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 814720 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1319 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 180536939 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2712428 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 910410345 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.611396 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.336099 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 492504429 54.55% 54.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 33980590 3.76% 58.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 33251729 3.68% 62.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33383912 3.70% 65.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 27248388 3.02% 68.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 27817475 3.08% 71.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 37350305 4.14% 75.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33792757 3.74% 79.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183536161 20.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 499900768 54.91% 54.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 34011801 3.74% 58.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 33310917 3.66% 62.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33621227 3.69% 66.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27137981 2.98% 68.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 27875262 3.06% 72.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 37328628 4.10% 76.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33745133 3.71% 79.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183478628 20.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 902865746 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.256808 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.415492 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127621918 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 442269855 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 240334233 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82525795 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10113945 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2233625829 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 10113945 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 159854620 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 227411371 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 31769 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 285878914 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 219575127 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2183611721 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 177740 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 139597859 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24038652 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 44983183 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2288587317 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5525861457 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3514141602 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 52752 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 910410345 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.254386 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.404060 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127581888 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 450063290 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 239948731 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82707211 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10109225 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2232998831 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 10109225 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 159900312 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 230280409 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 34090 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 285603646 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 224482663 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2183077018 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 183617 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 140318739 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24297006 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 48974479 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2288425781 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5524582783 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3513207505 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 61088 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 674546463 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2421 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2405 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 426714045 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 530721549 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 210389629 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 240824950 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 72195473 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2112352245 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 24995 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1828962616 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 418654 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 578669571 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1006826210 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24443 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 902865746 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.025730 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.070839 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 674384927 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2376 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2343 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 427656429 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 530632285 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 210400238 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 240350662 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 72017394 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2112353898 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 24976 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1828941324 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 423887 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 578689030 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1006760945 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24424 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 910410345 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.008920 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.068672 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 318904182 35.32% 35.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 130514441 14.46% 49.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 119555800 13.24% 63.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 110903587 12.28% 75.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91967934 10.19% 85.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 61336498 6.79% 92.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 43115692 4.78% 97.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19163460 2.12% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7404152 0.82% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 325758066 35.78% 35.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 130835258 14.37% 50.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 120048462 13.19% 63.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 111501441 12.25% 75.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91294731 10.03% 85.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 61344237 6.74% 92.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43225981 4.75% 97.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18968528 2.08% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7433641 0.82% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 902865746 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 910410345 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11303507 42.48% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12206863 45.87% 88.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3099868 11.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11322546 42.44% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12279843 46.03% 88.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3074079 11.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2714574 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1212750239 66.31% 66.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 388692 0.02% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881011 0.21% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 435509272 23.81% 90.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173718712 9.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2717047 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1212867491 66.32% 66.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 388152 0.02% 66.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881000 0.21% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 102 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 435396374 23.81% 90.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173691158 9.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1828962616 # Type of FU issued -system.cpu.iq.rate 2.025311 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26610238 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014549 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4587788532 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2691313007 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1799275575 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 31338 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 67501 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 6790 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1852843768 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 14512 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 185242573 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1828941324 # Type of FU issued +system.cpu.iq.rate 2.008483 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26676468 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014586 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4595362463 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2691335659 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1799336607 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 30885 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 66324 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6516 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1852886556 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 14189 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 185525718 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 146624129 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 213999 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 388901 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 61229443 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 146532886 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 211598 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 388823 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61240052 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19562 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 956 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19518 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1112 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10113945 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 166739883 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10207354 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2112377240 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 401313 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 530726286 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 210389629 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7530 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4519493 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3556436 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 388901 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5749904 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4643271 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10393175 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1807883955 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 429428539 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 21078661 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10109225 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 169308479 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10486289 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2112378874 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 393422 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 530635043 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 210400238 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7587 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4508389 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3837371 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 388823 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5739135 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4588886 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10328021 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1807829650 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 429333816 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21111674 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 599547832 # number of memory reference insts executed -system.cpu.iew.exec_branches 171967250 # Number of branches executed -system.cpu.iew.exec_stores 170119293 # Number of stores executed -system.cpu.iew.exec_rate 2.001969 # Inst execution rate -system.cpu.iew.wb_sent 1804612346 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1799282365 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1369352269 # num instructions producing a value -system.cpu.iew.wb_consumers 2092896532 # num instructions consuming a value +system.cpu.iew.exec_refs 599464610 # number of memory reference insts executed +system.cpu.iew.exec_branches 171918385 # Number of branches executed +system.cpu.iew.exec_stores 170130794 # Number of stores executed +system.cpu.iew.exec_rate 1.985299 # Inst execution rate +system.cpu.iew.wb_sent 1804630771 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1799343123 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1369373146 # num instructions producing a value +system.cpu.iew.wb_consumers 2092710816 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.992444 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.654286 # average fanout of values written-back +system.cpu.iew.wb_rate 1.975980 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.654354 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 583616621 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 583611522 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9832190 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 823756093 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.856118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.505218 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9827684 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 831323520 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.839222 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.498579 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 355425849 43.15% 43.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174994405 21.24% 64.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57317339 6.96% 71.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86207861 10.47% 81.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 27016335 3.28% 85.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27048633 3.28% 88.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9853927 1.20% 89.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8829984 1.07% 90.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 77061760 9.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 362694832 43.63% 43.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175144101 21.07% 64.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57358727 6.90% 71.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86263805 10.38% 81.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27150861 3.27% 85.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27127713 3.26% 88.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9862872 1.19% 89.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8848382 1.06% 90.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 76872227 9.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 823756093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 831323520 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -578,338 +578,339 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 77061760 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 76872227 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2859299655 # The number of ROB reads -system.cpu.rob.rob_writes 4304507020 # The number of ROB writes -system.cpu.timesIdled 2587 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 187051 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2867051516 # The number of ROB reads +system.cpu.rob.rob_writes 4304473794 # The number of ROB writes +system.cpu.timesIdled 2567 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 197748 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.092125 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.092125 # CPI: Total CPI of All Threads -system.cpu.ipc 0.915646 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.915646 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2763619398 # number of integer regfile reads -system.cpu.int_regfile_writes 1467382261 # number of integer regfile writes -system.cpu.fp_regfile_reads 6855 # number of floating regfile reads -system.cpu.fp_regfile_writes 205 # number of floating regfile writes -system.cpu.cc_regfile_reads 600921704 # number of cc regfile reads -system.cpu.cc_regfile_writes 409683570 # number of cc regfile writes -system.cpu.misc_regfile_reads 991700936 # number of misc regfile reads +system.cpu.cpi 1.101262 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.101262 # CPI: Total CPI of All Threads +system.cpu.ipc 0.908049 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.908049 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2763330538 # number of integer regfile reads +system.cpu.int_regfile_writes 1467435539 # number of integer regfile writes +system.cpu.fp_regfile_reads 6574 # number of floating regfile reads +system.cpu.fp_regfile_writes 209 # number of floating regfile writes +system.cpu.cc_regfile_reads 600926529 # number of cc regfile reads +system.cpu.cc_regfile_writes 409661898 # number of cc regfile writes +system.cpu.misc_regfile_reads 991625144 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2534340 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.717392 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 388713882 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2538436 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 153.131252 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1658510250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.717392 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998222 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998222 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2532368 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.654602 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 388337333 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2536464 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 153.101851 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1688557250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.654602 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998207 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998207 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 872 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3178 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 854 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3198 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 786546356 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 786546356 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 240120715 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 240120715 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148188548 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148188548 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 388309263 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 388309263 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 388309263 # number of overall hits -system.cpu.dcache.overall_hits::total 388309263 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2723043 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2723043 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 971654 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 971654 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3694697 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3694697 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3694697 # number of overall misses -system.cpu.dcache.overall_misses::total 3694697 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55426039088 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55426039088 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 27751124058 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 27751124058 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83177163146 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83177163146 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83177163146 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83177163146 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 242843758 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 242843758 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 785792022 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 785792022 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 239684650 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 239684650 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148177346 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148177346 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 387861996 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 387861996 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 387861996 # number of overall hits +system.cpu.dcache.overall_hits::total 387861996 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2782927 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2782927 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 982856 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 982856 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3765783 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3765783 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3765783 # number of overall misses +system.cpu.dcache.overall_misses::total 3765783 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59969889588 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59969889588 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31202214310 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31202214310 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91172103898 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91172103898 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91172103898 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91172103898 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 242467577 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 242467577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 392003960 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 392003960 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 392003960 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 392003960 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011213 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011213 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006514 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006514 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009425 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009425 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009425 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009425 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20354.448713 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20354.448713 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28560.705825 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28560.705825 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22512.580367 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22512.580367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22512.580367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22512.580367 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9748 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 16 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1054 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 391627779 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 391627779 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 391627779 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 391627779 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011478 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011478 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006589 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006589 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009616 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009616 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009616 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009616 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21549.214043 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21549.214043 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31746.475893 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31746.475893 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24210.663200 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24210.663200 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24210.663200 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24210.663200 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10538 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1092 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.248577 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.650183 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 2.333333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2333101 # number of writebacks -system.cpu.dcache.writebacks::total 2333101 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 955922 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 955922 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18334 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18334 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 974256 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 974256 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 974256 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 974256 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767121 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1767121 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 953320 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 953320 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2720441 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2720441 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2720441 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2720441 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30613583252 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30613583252 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25522867191 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 25522867191 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56136450443 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 56136450443 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56136450443 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 56136450443 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007277 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007277 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006391 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006391 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006940 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006940 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006940 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006940 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17323.988143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17323.988143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26772.612754 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26772.612754 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20635.055288 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20635.055288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20635.055288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20635.055288 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2331685 # number of writebacks +system.cpu.dcache.writebacks::total 2331685 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1017273 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1017273 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18365 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18365 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1035638 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1035638 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1035638 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1035638 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1765654 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1765654 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 964491 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 964491 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2730145 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2730145 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2730145 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2730145 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32740632750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32740632750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29421021688 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 29421021688 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62161654438 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 62161654438 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62161654438 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 62161654438 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007282 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007282 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006466 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006466 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006971 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006971 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006971 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006971 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18543.062656 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18543.062656 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30504.195154 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30504.195154 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22768.627468 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22768.627468 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22768.627468 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22768.627468 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 6998 # number of replacements -system.cpu.icache.tags.tagsinuse 1079.308636 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 180351835 # Total number of references to valid blocks. +system.cpu.icache.tags.replacements 6982 # number of replacements +system.cpu.icache.tags.tagsinuse 1087.309225 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 180328938 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 8606 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20956.522775 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 20953.862189 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1079.308636 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.527006 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.527006 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1608 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 308 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1173 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 361286153 # Number of tag accesses -system.cpu.icache.tags.data_accesses 361286153 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 180354535 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 180354535 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 180354535 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 180354535 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 180354535 # number of overall hits -system.cpu.icache.overall_hits::total 180354535 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 193180 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 193180 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 193180 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 193180 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 193180 # number of overall misses -system.cpu.icache.overall_misses::total 193180 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1193812485 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1193812485 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1193812485 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1193812485 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1193812485 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1193812485 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 180547715 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 180547715 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 180547715 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 180547715 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 180547715 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 180547715 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001070 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001070 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001070 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001070 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001070 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001070 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6179.793379 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6179.793379 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6179.793379 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6179.793379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6179.793379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6179.793379 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1413 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1087.309225 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.530913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.530913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1624 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 309 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1182 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 361276321 # Number of tag accesses +system.cpu.icache.tags.data_accesses 361276321 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 180331996 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 180331996 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 180331996 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 180331996 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 180331996 # number of overall hits +system.cpu.icache.overall_hits::total 180331996 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 204942 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 204942 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 204942 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 180536938 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 180536938 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 180536938 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 180536938 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001135 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001135 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001135 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001135 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001135 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001135 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6369.541090 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 245309750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25902879782 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26148189532 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 245309750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25902879782 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26148189532 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.407356 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099813 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101312 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990438 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68360.421928 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68385.705225 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18047.548744 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18047.548744 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66936.284657 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66936.284657 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69650.695627 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67591.126407 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67609.882152 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69650.695627 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67591.126407 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67609.882152 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1957626 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1957626 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2333101 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 182005 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 182005 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771533 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771533 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 199325 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7773983 # 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Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771021 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771021 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 211091 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7791975 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8003066 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 553280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311561536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312114816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 193800 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5264276 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 5244265 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 5264276 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5244265 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4971600701 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5264276 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4991831371 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 286576989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 304197990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3981486557 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3984504311 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadReq 179848 # Transaction distribution -system.membus.trans_dist::ReadResp 179848 # Transaction distribution -system.membus.trans_dist::Writeback 294030 # Transaction distribution -system.membus.trans_dist::UpgradeReq 180174 # Transaction distribution -system.membus.trans_dist::UpgradeResp 180174 # Transaction distribution -system.membus.trans_dist::ReadExReq 207029 # Transaction distribution -system.membus.trans_dist::ReadExResp 207029 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1428132 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1428132 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1428132 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43578048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43578048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43578048 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 179736 # Transaction distribution +system.membus.trans_dist::ReadResp 179736 # Transaction distribution +system.membus.trans_dist::Writeback 293946 # Transaction distribution +system.membus.trans_dist::UpgradeReq 191861 # Transaction distribution +system.membus.trans_dist::UpgradeResp 191861 # Transaction distribution +system.membus.trans_dist::ReadExReq 206982 # Transaction distribution +system.membus.trans_dist::ReadExResp 206982 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1451104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1451104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1451104 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43562496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43562496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43562496 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 861081 # Request fanout histogram +system.membus.snoop_fanout::samples 872525 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 861081 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 872525 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 861081 # Request fanout histogram -system.membus.reqLayer0.occupancy 3467092000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3996161130 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.snoop_fanout::total 872525 # Request fanout histogram +system.membus.reqLayer0.occupancy 2241314053 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2430435187 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 81d0742cf..43971ad10 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.647873 # Number of seconds simulated -sim_ticks 1647872849000 # Number of ticks simulated -final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1647872738500 # Number of ticks simulated +final_tick 1647872738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 845545 # Simulator instruction rate (inst/s) -host_op_rate 1563508 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1685075999 # Simulator tick rate (ticks/s) -host_mem_usage 318276 # Number of bytes of host memory used -host_seconds 977.92 # Real time elapsed on the host +host_inst_rate 730118 # Simulator instruction rate (inst/s) +host_op_rate 1350071 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1455043701 # Simulator tick rate (ticks/s) +host_mem_usage 323120 # Number of bytes of host memory used +host_seconds 1132.52 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,46 +26,20 @@ system.physmem.num_reads::total 381143 # Nu system.physmem.num_writes::writebacks 292286 # Number of write requests responded to by this memory system.physmem.num_writes::total 292286 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 73248 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14729564 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14802812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14729565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14802813 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11351788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11351788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 11351789 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11351789 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11351789 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 174452 # Transaction distribution -system.membus.trans_dist::ReadResp 174452 # Transaction distribution -system.membus.trans_dist::Writeback 292286 # Transaction distribution -system.membus.trans_dist::ReadExReq 206691 # Transaction distribution -system.membus.trans_dist::ReadExResp 206691 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 673429 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 673429 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 673429 # Request fanout histogram -system.membus.reqLayer0.occupancy 3011737000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.physmem.bw_total::cpu.data 14729565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 26154602 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3295745698 # number of cpu cycles simulated +system.cpu.numCycles 3295745477 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed @@ -86,7 +60,7 @@ system.cpu.num_mem_refs 533262343 # nu system.cpu.num_load_insts 384102157 # Number of load instructions system.cpu.num_store_insts 149160186 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3295745697.998000 # Number of busy cycles +system.cpu.num_busy_cycles 3295745476.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 149758583 # Number of branches fetched @@ -125,13 +99,122 @@ system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1528988702 # Class of executed instruction +system.cpu.dcache.tags.replacements 2514362 # number of replacements +system.cpu.dcache.tags.tagsinuse 4086.415780 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 8211725000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415780 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits +system.cpu.dcache.overall_hits::total 530743930 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses +system.cpu.dcache.overall_misses::total 2518458 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704183000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29704183000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964598500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18964598500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 48668781500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 48668781500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 48668781500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 48668781500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.752147 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.752147 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.138607 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.138607 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.833489 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19324.833489 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.833489 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19324.833489 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks +system.cpu.dcache.writebacks::total 2323523 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27113062000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27113062000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17778032500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17778032500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44891094500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44891094500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44891094500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44891094500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15695.752147 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15695.752147 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22474.138607 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22474.138607 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17824.833489 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17824.833489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17824.833489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17824.833489 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 881.356484 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 881.356484 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id @@ -155,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 115806000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 115806000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 115806000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 115806000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 115806000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 115806000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 115798500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 115798500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 115798500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 115798500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 115798500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 115798500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses @@ -173,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41153.518124 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41153.518124 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41153.518124 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41153.518124 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41150.852878 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41150.852878 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41150.852878 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41150.852878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41150.852878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41150.852878 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -193,34 +276,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814 system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 110178000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 110178000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 110178000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 110178000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 110178000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 110178000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 111577500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 111577500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 111577500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 111577500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 111577500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 111577500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39153.518124 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39153.518124 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39650.852878 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39650.852878 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39650.852878 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39650.852878 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39650.852878 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39650.852878 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 348459 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29286.402664 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 29286.402293 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 755936423000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21041.298927 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758524 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344842 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy @@ -257,17 +340,17 @@ system.cpu.l2cache.demand_misses::total 381143 # nu system.cpu.l2cache.overall_misses::cpu.inst 1886 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 379257 # number of overall misses system.cpu.l2cache.overall_misses::total 381143 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 98084000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8973561000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 9071645000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10747939500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10747939500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 98084000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 19721500500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 19819584500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 98084000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 19721500500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 19819584500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 99019500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9059744000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 9158763500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10851282000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10851282000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 99019500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 19911026000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20010045500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 99019500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 19911026000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20010045500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses) @@ -292,17 +375,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.151171 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.670220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.150591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.151171 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52006.362672 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.747540 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.808245 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.036286 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.036286 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.389618 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.389618 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.386002 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500.168052 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.192030 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.021772 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.021772 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.386002 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.088331 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.099700 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.386002 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.088331 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.099700 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -324,17 +407,17 @@ system.cpu.l2cache.demand_mshr_misses::total 381143 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1886 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 379257 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 381143 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 75452000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6902758000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6978210000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8267645000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8267645000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75452000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15170403000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15245855000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75452000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15170403000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15245855000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 76387000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6988941000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7065328000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8370987500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8370987500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 76387000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15359928500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15436315500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 76387000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15359928500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15436315500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099898 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100826 # mshr miss rate for ReadReq accesses @@ -346,127 +429,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.151171 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.151171 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.362672 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.683796 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.745191 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.024191 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.024191 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.120891 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500.104308 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.126109 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.009676 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.009676 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.120891 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.052735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.062968 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.120891 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.052735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.062968 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2514362 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.415783 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits -system.cpu.dcache.overall_hits::total 530743930 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses -system.cpu.dcache.overall_misses::total 2518458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704283000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29704283000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964601500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18964601500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.810037 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.810037 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.142399 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.142399 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19324.874387 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19324.874387 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks -system.cpu.dcache.writebacks::total 2323523 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26249455000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26249455000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17382513500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17382513500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43631968500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 43631968500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43631968500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 43631968500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15195.810037 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15195.810037 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution @@ -498,5 +472,31 @@ system.cpu.toL2Bus.respLayer0.occupancy 4221000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 174452 # Transaction distribution +system.membus.trans_dist::ReadResp 174452 # Transaction distribution +system.membus.trans_dist::Writeback 292286 # Transaction distribution +system.membus.trans_dist::ReadExReq 206691 # Transaction distribution +system.membus.trans_dist::ReadExResp 206691 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 673429 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 673429 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 673429 # Request fanout histogram +system.membus.reqLayer0.occupancy 1860874000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1905729000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 688c5f811..bccf5186d 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.226819 # Number of seconds simulated -sim_ticks 226818771000 # Number of ticks simulated -final_tick 226818771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.226866 # Number of seconds simulated +sim_ticks 226865901500 # Number of ticks simulated +final_tick 226865901500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 207340 # Simulator instruction rate (inst/s) -host_op_rate 207340 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 117965343 # Simulator tick rate (ticks/s) -host_mem_usage 287544 # Number of bytes of host memory used -host_seconds 1922.76 # Real time elapsed on the host +host_inst_rate 324605 # Simulator instruction rate (inst/s) +host_op_rate 324605 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 184721178 # Simulator tick rate (ticks/s) +host_mem_usage 301676 # Number of bytes of host memory used +host_seconds 1228.15 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 249280 # Nu system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1099027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1122447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2221474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1099027 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1099027 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1099027 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1122447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2221474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1098799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1122214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2221012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1098799 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1098799 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1098799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1122214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2221012 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7873 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 226818689500 # Total gap between requests +system.physmem.totGap 226865813000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 980 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 329.076822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 197.330219 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.077184 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 516 33.88% 33.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 348 22.85% 56.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 193 12.67% 69.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 104 6.83% 76.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 58 3.81% 80.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 41 2.69% 82.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 32 2.10% 84.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 40 2.63% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 191 12.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation -system.physmem.totQLat 50610250 # Total ticks spent queuing -system.physmem.totMemAccLat 198229000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1561 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 321.065983 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 192.383190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.308816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 550 35.23% 35.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 344 22.04% 57.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 200 12.81% 70.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 103 6.60% 76.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 61 3.91% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 52 3.33% 83.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 34 2.18% 86.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 30 1.92% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 187 11.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1561 # Bytes accessed per row activation +system.physmem.totQLat 54380250 # Total ticks spent queuing +system.physmem.totMemAccLat 201999000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6428.33 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6907.18 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25178.33 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25657.18 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6341 # Number of row buffer hits during reads +system.physmem.readRowHits 6303 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.54 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.06 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28809690.02 # Average gap between requests -system.physmem.pageHitRate 80.54 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6698160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3654750 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 28815675.47 # Average gap between requests +system.physmem.pageHitRate 80.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6902280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3766125 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 34164000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14814352800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5823127980 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 130980226500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 151662224190 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.664235 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 217898379000 # Time in different power states -system.physmem_0.memoryStateTime::REF 7573800000 # Time in different power states +system.physmem_0.refreshEnergy 14817404160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5855918085 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 130979493750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 151697648400 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.682686 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 217896983750 # Time in different power states +system.physmem_0.memoryStateTime::REF 7575360000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1344256000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1391017250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4808160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2623500 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 4891320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2668875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 26910000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14814352800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5572496700 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 131200078500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 151621269660 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.483670 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 218263346500 # Time in different power states -system.physmem_1.memoryStateTime::REF 7573800000 # Time in different power states +system.physmem_1.refreshEnergy 14817404160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5585732100 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 131216499000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 151654105455 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.490749 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 218290626750 # Time in different power states +system.physmem_1.memoryStateTime::REF 7575360000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 976701000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 994701750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 46273761 # Number of BP lookups +system.cpu.branchPred.lookups 46273750 # Number of BP lookups system.cpu.branchPred.condPredicted 26730646 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1017469 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25595416 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21359944 # Number of BTB hits +system.cpu.branchPred.BTBLookups 25595406 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21359943 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.452224 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8341649 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 83.452253 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8341648 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95585470 # DTB read hits +system.cpu.dtb.read_hits 95585469 # DTB read hits system.cpu.dtb.read_misses 115 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95585585 # DTB read accesses -system.cpu.dtb.write_hits 73606436 # DTB write hits +system.cpu.dtb.read_accesses 95585584 # DTB read accesses +system.cpu.dtb.write_hits 73606437 # DTB write hits system.cpu.dtb.write_misses 857 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73607293 # DTB write accesses +system.cpu.dtb.write_accesses 73607294 # DTB write accesses system.cpu.dtb.data_hits 169191906 # DTB hits system.cpu.dtb.data_misses 972 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 169192878 # DTB accesses -system.cpu.itb.fetch_hits 98781228 # ITB hits -system.cpu.itb.fetch_misses 1237 # ITB misses +system.cpu.itb.fetch_hits 98781212 # ITB hits +system.cpu.itb.fetch_misses 1236 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 98782465 # ITB accesses +system.cpu.itb.fetch_accesses 98782448 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,59 +293,59 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 453637542 # number of cpu cycles simulated +system.cpu.numCycles 453731803 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664665 # Number of instructions committed system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4467797 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4467789 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.137893 # CPI: cycles per instruction -system.cpu.ipc 0.878818 # IPC: instructions per cycle -system.cpu.tickCycles 450174327 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3463215 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.138129 # CPI: cycles per instruction +system.cpu.ipc 0.878635 # IPC: instructions per cycle +system.cpu.tickCycles 450174138 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3557665 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.955330 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168028615 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.677539 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168028622 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40343.004802 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40343.006483 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.955330 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803700 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803700 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.677539 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803632 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803632 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336075633 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336075633 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 94513823 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94513823 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514792 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514792 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168028615 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168028615 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168028615 # number of overall hits -system.cpu.dcache.overall_hits::total 168028615 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1181 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1181 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5938 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5938 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 7119 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7119 # number of overall misses -system.cpu.dcache.overall_misses::total 7119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 81009750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 81009750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 391587500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 391587500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 472597250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 472597250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 472597250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 472597250 # number of overall miss cycles +system.cpu.dcache.ReadReq_hits::cpu.data 94513824 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94513824 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514798 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514798 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168028622 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168028622 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168028622 # number of overall hits +system.cpu.dcache.overall_hits::total 168028622 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1180 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1180 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5932 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5932 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 7112 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7112 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7112 # number of overall misses +system.cpu.dcache.overall_misses::total 7112 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88706750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88706750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 435640500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 435640500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 524347250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 524347250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 524347250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 524347250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94515004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94515004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) @@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68594.199831 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68594.199831 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65946.025598 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65946.025598 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66385.342042 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66385.342042 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66385.342042 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66385.342042 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75175.211864 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75175.211864 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73439.059339 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73439.059339 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73727.116142 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73727.116142 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73727.116142 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73727.116142 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,28 +382,28 @@ system.cpu.dcache.writebacks::writebacks 654 # nu system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2743 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2743 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2954 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2954 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2954 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2954 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 970 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3195 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2736 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2736 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2947 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2947 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2947 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2947 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3196 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64296000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 64296000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 214342750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 214342750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 278638750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 278638750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 278638750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 278638750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70790750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 70790750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 240139250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 240139250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310930000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 310930000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310930000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 310930000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -412,68 +412,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66284.536082 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66284.536082 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67086.932707 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67086.932707 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66900.060024 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66900.060024 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73055.469556 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73055.469556 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75137.437422 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75137.437422 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74653.061224 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74653.061224 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74653.061224 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74653.061224 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3196 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.781818 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 98776054 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1918.668562 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 98776038 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5174 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19090.849246 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 19090.846154 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.781818 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.936905 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.936905 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1918.668562 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.936850 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.936850 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1281 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 197567630 # Number of tag accesses -system.cpu.icache.tags.data_accesses 197567630 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 98776054 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 98776054 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 98776054 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 98776054 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 98776054 # number of overall hits -system.cpu.icache.overall_hits::total 98776054 # number of overall hits +system.cpu.icache.tags.tag_accesses 197567598 # Number of tag accesses +system.cpu.icache.tags.data_accesses 197567598 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 98776038 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 98776038 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 98776038 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 98776038 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 98776038 # number of overall hits +system.cpu.icache.overall_hits::total 98776038 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5174 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5174 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5174 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5174 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5174 # number of overall misses system.cpu.icache.overall_misses::total 5174 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 293011250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 293011250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 293011250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 293011250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 293011250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 293011250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 98781228 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 98781228 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 98781228 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 98781228 # 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number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 98781212 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 98781212 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 98781212 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56631.474681 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56631.474681 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56631.474681 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56631.474681 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56631.474681 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56631.474681 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61982.460379 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61982.460379 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61982.460379 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61982.460379 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61982.460379 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61982.460379 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -488,41 +488,41 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5174 system.cpu.icache.demand_mshr_misses::total 5174 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5174 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5174 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281053750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281053750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281053750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281053750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281053750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281053750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311289750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 311289750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311289750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 311289750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311289750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 311289750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54320.400077 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54320.400077 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54320.400077 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54320.400077 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54320.400077 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54320.400077 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60164.234635 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60164.234635 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60164.234635 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60164.234635 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60164.234635 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60164.234635 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4426.924727 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4426.526265 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1494 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5273 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.283330 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 373.138335 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.752394 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 642.033998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011387 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104118 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.019593 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.135099 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 373.084024 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.466195 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 641.976046 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104110 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.019592 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.135087 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 611 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4443 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160919 # Percentage of cache occupancy per task id @@ -552,17 +552,17 @@ system.cpu.l2cache.demand_misses::total 7873 # nu system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses system.cpu.l2cache.overall_misses::total 7873 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 263088750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61866750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 324955500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 210698500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 210698500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 263088750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 272565250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 535654000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 263088750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 272565250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 535654000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 292685750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 68346250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 361032000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 236421750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 236421750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 292685750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 304768000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 597453750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 292685750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 304768000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 597453750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 5174 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 967 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses) @@ -587,17 +587,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.843024 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.752802 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843024 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67545.250321 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73563.317479 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68613.914696 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67165.604080 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67165.604080 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67545.250321 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68518.162393 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68036.834752 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67545.250321 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68518.162393 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68036.834752 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75143.966624 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81267.835910 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76231.418919 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75365.556264 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75365.556264 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75143.966624 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76613.373555 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75886.415598 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75143.966624 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76613.373555 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75886.415598 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -617,17 +617,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7873 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214177750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 51424250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265602000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 171025500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 171025500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214177750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 222449750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 436627500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214177750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 222449750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 436627500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 243926750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 57790750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301717500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 197209250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 197209250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 243926750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 255000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 498926750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 243926750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 255000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 498926750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771210 # mshr miss rate for ReadReq accesses @@ -639,17 +639,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.843024 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843024 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54987.869063 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61146.551724 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56081.503378 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54518.807778 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54518.807778 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54987.869063 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55919.997486 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54987.869063 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55919.997486 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62625.609756 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68716.706302 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63707.242399 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62865.556264 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62865.556264 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62625.609756 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64102.564103 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63371.872222 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62625.609756 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64102.564103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63371.872222 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 6141 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 6141 # Transaction distribution @@ -676,9 +676,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 9993 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 5650500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8565750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8584250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6972750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7034000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 4736 # Transaction distribution system.membus.trans_dist::ReadResp 4736 # Transaction distribution @@ -699,9 +699,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7873 # Request fanout histogram -system.membus.reqLayer0.occupancy 9387500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9289000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 73877500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 41806250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 90aeffe97..7866e7931 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.069652 # Number of seconds simulated -sim_ticks 69651704000 # Number of ticks simulated -final_tick 69651704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.069793 # Number of seconds simulated +sim_ticks 69793219500 # Number of ticks simulated +final_tick 69793219500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 253977 # Simulator instruction rate (inst/s) -host_op_rate 253977 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47101012 # Simulator tick rate (ticks/s) -host_mem_usage 302288 # Number of bytes of host memory used -host_seconds 1478.77 # Real time elapsed on the host +host_inst_rate 248568 # Simulator instruction rate (inst/s) +host_op_rate 248568 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46191499 # Simulator tick rate (ticks/s) +host_mem_usage 302704 # Number of bytes of host memory used +host_seconds 1510.95 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255744 # Number of bytes read from this memory -system.physmem.bytes_read::total 477312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221568 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3462 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3996 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7458 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3181085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3671755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6852840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3181085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3181085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3181085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3671755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6852840 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7458 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 221440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255808 # Number of bytes read from this memory +system.physmem.bytes_read::total 477248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3460 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3997 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7457 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3172801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3665227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6838028 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3172801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3172801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3172801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3665227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6838028 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7457 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7458 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7457 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 477312 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 477248 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 477312 # Total read bytes from the system interface side +system.physmem.bytesReadSys 477248 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 528 # Per bank write bursts -system.physmem.perBankRdBursts::1 655 # Per bank write bursts +system.physmem.perBankRdBursts::0 527 # Per bank write bursts +system.physmem.perBankRdBursts::1 657 # Per bank write bursts system.physmem.perBankRdBursts::2 455 # Per bank write bursts system.physmem.perBankRdBursts::3 602 # Per bank write bursts system.physmem.perBankRdBursts::4 446 # Per bank write bursts system.physmem.perBankRdBursts::5 454 # Per bank write bursts system.physmem.perBankRdBursts::6 515 # Per bank write bursts -system.physmem.perBankRdBursts::7 524 # Per bank write bursts -system.physmem.perBankRdBursts::8 439 # Per bank write bursts -system.physmem.perBankRdBursts::9 406 # Per bank write bursts -system.physmem.perBankRdBursts::10 340 # Per bank write bursts +system.physmem.perBankRdBursts::7 522 # Per bank write bursts +system.physmem.perBankRdBursts::8 438 # Per bank write bursts +system.physmem.perBankRdBursts::9 407 # Per bank write bursts +system.physmem.perBankRdBursts::10 339 # Per bank write bursts system.physmem.perBankRdBursts::11 305 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts system.physmem.perBankRdBursts::13 542 # Per bank write bursts -system.physmem.perBankRdBursts::14 454 # Per bank write bursts +system.physmem.perBankRdBursts::14 455 # Per bank write bursts system.physmem.perBankRdBursts::15 379 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 69651614500 # Total gap between requests +system.physmem.totGap 69793123000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7458 # Read request sizes (log2) +system.physmem.readPktSize::6 7457 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1353 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 350.509978 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 208.904608 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.764111 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 423 31.26% 31.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 330 24.39% 55.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 152 11.23% 66.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 83 6.13% 73.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 55 4.07% 77.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 43 3.18% 80.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 38 2.81% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 1.85% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 204 15.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1353 # Bytes accessed per row activation -system.physmem.totQLat 67034750 # Total ticks spent queuing -system.physmem.totMemAccLat 206872250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37290000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8988.30 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1360 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.047059 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 208.039838 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 346.646558 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 428 31.47% 31.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 327 24.04% 55.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 157 11.54% 67.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 92 6.76% 73.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 56 4.12% 77.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 39 2.87% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 33 2.43% 83.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25 1.84% 85.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 203 14.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1360 # Bytes accessed per row activation +system.physmem.totQLat 67335750 # Total ticks spent queuing +system.physmem.totMemAccLat 207154500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37285000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9029.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27738.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.85 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27779.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.84 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.85 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.84 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6096 # Number of row buffer hits during reads +system.physmem.readRowHits 6086 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.74 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9339181.35 # Average gap between requests -system.physmem.pageHitRate 81.74 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5843880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3188625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 32385600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 9359410.35 # Average gap between requests +system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5828760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3180375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 32377800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4549069200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2090226195 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 39955428000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 46636141500 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.595153 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 66468117000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2325700000 # Time in different power states +system.physmem_0.refreshEnergy 4558223280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2111779035 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 40020613500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 46732002750 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.624038 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 66577889000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2330380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 855864000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 882777000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4362120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2380125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 25373400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4430160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2417250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 25272000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4549069200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1978191270 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 40053704250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 46613080365 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.264045 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 66630949750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2325700000 # Time in different power states +system.physmem_1.refreshEnergy 4558223280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2013356565 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 40106949000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 46710648255 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.318049 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 66719394750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2330380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 691630250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 738657750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 51167471 # Number of BP lookups -system.cpu.branchPred.condPredicted 29641015 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1213095 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25804996 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23600999 # Number of BTB hits +system.cpu.branchPred.lookups 51259743 # Number of BP lookups +system.cpu.branchPred.condPredicted 29683169 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1233682 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26552604 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23664767 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.459030 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9351091 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 307 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.124091 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9366329 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 317 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103696202 # DTB read hits -system.cpu.dtb.read_misses 91462 # DTB read misses -system.cpu.dtb.read_acv 49407 # DTB read access violations -system.cpu.dtb.read_accesses 103787664 # DTB read accesses -system.cpu.dtb.write_hits 79414480 # DTB write hits -system.cpu.dtb.write_misses 1579 # DTB write misses +system.cpu.dtb.read_hits 103795078 # DTB read hits +system.cpu.dtb.read_misses 91880 # DTB read misses +system.cpu.dtb.read_acv 49322 # DTB read access violations +system.cpu.dtb.read_accesses 103886958 # DTB read accesses +system.cpu.dtb.write_hits 79431295 # DTB write hits +system.cpu.dtb.write_misses 1540 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 79416059 # DTB write accesses -system.cpu.dtb.data_hits 183110682 # DTB hits -system.cpu.dtb.data_misses 93041 # DTB misses -system.cpu.dtb.data_acv 49409 # DTB access violations -system.cpu.dtb.data_accesses 183203723 # DTB accesses -system.cpu.itb.fetch_hits 51277820 # ITB hits -system.cpu.itb.fetch_misses 422 # ITB misses +system.cpu.dtb.write_accesses 79432835 # DTB write accesses +system.cpu.dtb.data_hits 183226373 # DTB hits +system.cpu.dtb.data_misses 93420 # DTB misses +system.cpu.dtb.data_acv 49324 # DTB access violations +system.cpu.dtb.data_accesses 183319793 # DTB accesses +system.cpu.itb.fetch_hits 51424924 # ITB hits +system.cpu.itb.fetch_misses 367 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 51278242 # ITB accesses +system.cpu.itb.fetch_accesses 51425291 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,239 +293,239 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 139303411 # number of cpu cycles simulated +system.cpu.numCycles 139586442 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 52063926 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 457094521 # Number of instructions fetch has processed -system.cpu.fetch.Branches 51167471 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32952090 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 85692281 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2532764 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 52218190 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 457878359 # Number of instructions fetch has processed +system.cpu.fetch.Branches 51259743 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33031096 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 85762697 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2573496 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13783 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 51277820 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 545278 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 139036576 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.287585 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.344928 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 172 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13442 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 10 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 51424924 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 558112 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 139281263 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.287437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.344389 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58307337 41.94% 41.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4519216 3.25% 45.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7280822 5.24% 50.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5545601 3.99% 54.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11970286 8.61% 63.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8019991 5.77% 68.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5933032 4.27% 73.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1884761 1.36% 74.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35575530 25.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58400466 41.93% 41.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4519538 3.24% 45.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7300185 5.24% 50.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5568881 4.00% 54.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11993718 8.61% 63.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8035210 5.77% 68.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5954127 4.27% 73.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1896980 1.36% 74.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35612158 25.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 139036576 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367310 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.281287 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45112383 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16348146 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 71787003 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4526860 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1262184 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9563244 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4245 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 451283163 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 14196 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1262184 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47011024 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5663526 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 519113 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 74309218 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10271511 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 447721649 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 439815 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2540100 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2926498 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3600527 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 292278306 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 589607782 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 419965282 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 169642499 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 139281263 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367226 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.280250 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45296559 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16238717 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 71951122 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4512320 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1282545 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9579038 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4257 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 452073358 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 14179 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1282545 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 47196926 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5664651 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 519192 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 74460720 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10157229 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 448418638 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 439172 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2532304 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2861217 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3565763 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 292805975 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 590541853 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 420605547 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 169936305 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32745977 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37893 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 316 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 16173797 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106306370 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81667386 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12470725 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9729569 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 414594685 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 306 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 406915918 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 484036 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 38878487 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 18208107 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 139036576 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.926683 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.221929 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 33273646 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37923 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 320 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 15988914 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106425467 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81691000 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12462225 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9670397 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 415046688 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 308 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 407272286 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 487219 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 39326693 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 18379010 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 139281263 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.924100 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.223091 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23891494 17.18% 17.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19616678 14.11% 31.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22677483 16.31% 47.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18900240 13.59% 61.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19609416 14.10% 75.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14153871 10.18% 85.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9626410 6.92% 92.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6209797 4.47% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4351187 3.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24058662 17.27% 17.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19633951 14.10% 31.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22674806 16.28% 47.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18925755 13.59% 61.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19544360 14.03% 75.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14234748 10.22% 85.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9653364 6.93% 92.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6204842 4.45% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4350775 3.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 139036576 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 139281263 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 258477 1.29% 1.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 145250 0.73% 2.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 90218 0.45% 2.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 2947 0.01% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3497968 17.50% 19.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1676632 8.39% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9338598 46.73% 75.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4976149 24.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 264805 1.33% 1.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 148480 0.74% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 91560 0.46% 2.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 2226 0.01% 2.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3500111 17.53% 20.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1672568 8.38% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9323721 46.69% 75.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4965817 24.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 153207490 37.65% 37.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2128182 0.52% 38.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 37392506 9.19% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7524499 1.85% 49.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2804822 0.69% 49.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16757586 4.12% 54.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1601657 0.39% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105367868 25.89% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 80097727 19.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 153389569 37.66% 37.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2128191 0.52% 38.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 37431648 9.19% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7537641 1.85% 49.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2804878 0.69% 49.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16758896 4.11% 54.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1606846 0.39% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105464958 25.90% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 80116078 19.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 406915918 # Type of FU issued -system.cpu.iq.rate 2.921076 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19986240 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.049116 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 625897049 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 265989715 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237228631 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 347441639 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 187559752 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 163339265 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 246150914 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 180717663 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19936358 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 407272286 # Type of FU issued +system.cpu.iq.rate 2.917707 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19969288 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.049032 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 626696170 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 266696972 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237458259 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 347586172 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187752417 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 163387975 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 246426590 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 180781403 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19964423 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11551883 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 163597 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76334 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8146657 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11670980 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 165408 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76048 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8170271 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 381699 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4488 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 382447 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3767 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1262184 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4471526 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 139208 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 439574480 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 145285 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106306370 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81667386 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 306 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6690 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 131691 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76334 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 976027 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412585 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1388612 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403157736 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103837102 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3758182 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1282545 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4525606 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 90420 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 440059104 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 152527 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106425467 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81691000 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 308 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 7009 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 82356 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76048 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1000879 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 421168 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1422047 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403473304 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103936308 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3798982 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24979489 # number of nop insts executed -system.cpu.iew.exec_refs 183253198 # number of memory reference insts executed -system.cpu.iew.exec_branches 46959989 # Number of branches executed -system.cpu.iew.exec_stores 79416096 # Number of stores executed -system.cpu.iew.exec_rate 2.894098 # Inst execution rate -system.cpu.iew.wb_sent 401401507 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400567896 # cumulative count of insts written-back -system.cpu.iew.wb_producers 198000452 # num instructions producing a value -system.cpu.iew.wb_consumers 283955606 # num instructions consuming a value +system.cpu.iew.exec_nop 25012108 # number of nop insts executed +system.cpu.iew.exec_refs 183369178 # number of memory reference insts executed +system.cpu.iew.exec_branches 46997600 # Number of branches executed +system.cpu.iew.exec_stores 79432870 # Number of stores executed +system.cpu.iew.exec_rate 2.890491 # Inst execution rate +system.cpu.iew.wb_sent 401684713 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400846234 # cumulative count of insts written-back +system.cpu.iew.wb_producers 198095133 # num instructions producing a value +system.cpu.iew.wb_consumers 284050882 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.875507 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.697294 # average fanout of values written-back +system.cpu.iew.wb_rate 2.871670 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.697393 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 40912072 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 41395670 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1208897 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 133310723 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.990491 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.213946 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1229479 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 133482933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.986633 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.212859 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 48555712 36.42% 36.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18055923 13.54% 49.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 9630862 7.22% 57.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8737322 6.55% 63.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6426217 4.82% 68.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4404759 3.30% 71.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4988493 3.74% 75.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2616131 1.96% 77.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29895304 22.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 48683097 36.47% 36.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18109981 13.57% 50.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9618460 7.21% 57.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8715508 6.53% 63.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6449297 4.83% 68.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4412968 3.31% 71.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5003390 3.75% 75.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2633066 1.97% 77.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29857166 22.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 133310723 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 133482933 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -571,128 +571,128 @@ system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction -system.cpu.commit.bw_lim_events 29895304 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29857166 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 542989097 # The number of ROB reads -system.cpu.rob.rob_writes 884890973 # The number of ROB writes -system.cpu.timesIdled 3476 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 266835 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 543683043 # The number of ROB reads +system.cpu.rob.rob_writes 885930772 # The number of ROB writes +system.cpu.timesIdled 3165 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 305179 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.370907 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.370907 # CPI: Total CPI of All Threads -system.cpu.ipc 2.696092 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.696092 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 403240146 # number of integer regfile reads -system.cpu.int_regfile_writes 171897288 # number of integer regfile writes -system.cpu.fp_regfile_reads 157938395 # number of floating regfile reads -system.cpu.fp_regfile_writes 105579710 # number of floating regfile writes +system.cpu.cpi 0.371661 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.371661 # CPI: Total CPI of All Threads +system.cpu.ipc 2.690625 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.690625 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 403591803 # number of integer regfile reads +system.cpu.int_regfile_writes 172078772 # number of integer regfile writes +system.cpu.fp_regfile_reads 157997982 # number of floating regfile reads +system.cpu.fp_regfile_writes 105636085 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 798 # number of replacements -system.cpu.dcache.tags.tagsinuse 3297.113166 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 156873476 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4201 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37341.936682 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 806 # number of replacements +system.cpu.dcache.tags.tagsinuse 3297.136243 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 156944357 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4209 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37287.801616 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113166 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.804959 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.804959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3297.136243 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804965 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804965 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3119 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.830811 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 313794583 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 313794583 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 83372633 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 83372633 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500836 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500836 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 156873469 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 156873469 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 156873469 # number of overall hits -system.cpu.dcache.overall_hits::total 156873469 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1822 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1822 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19893 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19893 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21715 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21715 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21715 # number of overall misses -system.cpu.dcache.overall_misses::total 21715 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 114608500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 114608500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125293584 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1125293584 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1239902084 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1239902084 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1239902084 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1239902084 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83374455 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83374455 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 313935887 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 313935887 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 83443297 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 83443297 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501051 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501051 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 156944348 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 156944348 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 156944348 # number of overall hits +system.cpu.dcache.overall_hits::total 156944348 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1804 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1804 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19678 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19678 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21482 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21482 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21482 # number of overall misses +system.cpu.dcache.overall_misses::total 21482 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 122640500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 122640500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1228413709 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1228413709 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1351054209 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1351054209 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1351054209 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1351054209 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83445101 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83445101 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 156895184 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 156895184 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 156895184 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 156895184 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 9 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 156965830 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 156965830 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 156965830 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 156965830 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62902.579583 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62902.579583 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56567.314332 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56567.314332 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57098.875616 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57098.875616 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57098.875616 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57098.875616 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 46396 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 61 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 946 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000268 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000137 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000137 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000137 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000137 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67982.538803 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67982.538803 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62425.739862 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62425.739862 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62892.384741 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62892.384741 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62892.384741 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62892.384741 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 51314 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 108 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 737 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.044397 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.625509 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 108 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 674 # number of writebacks -system.cpu.dcache.writebacks::total 674 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 824 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 824 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16690 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16690 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17514 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17514 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17514 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17514 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 998 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 998 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3203 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3203 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4201 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4201 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4201 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4201 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67693000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 67693000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235962750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 235962750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303655750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 303655750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303655750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 303655750 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 682 # number of writebacks +system.cpu.dcache.writebacks::total 682 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 803 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 803 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16470 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16470 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17273 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17273 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17273 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17273 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1001 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1001 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3208 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3208 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4209 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4209 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4209 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4209 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72824500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 72824500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 253362750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 253362750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 326187250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 326187250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 326187250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 326187250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -701,198 +701,198 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67828.657315 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67828.657315 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73669.294411 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73669.294411 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72281.778148 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72281.778148 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72281.778148 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72281.778148 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72751.748252 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72751.748252 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78978.413342 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78978.413342 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77497.564742 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77497.564742 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77497.564742 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77497.564742 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2164 # number of replacements -system.cpu.icache.tags.tagsinuse 1832.364532 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 51272141 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4091 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12532.911513 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2160 # number of replacements +system.cpu.icache.tags.tagsinuse 1831.206745 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 51419247 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4087 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12581.171275 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364532 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894709 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894709 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1831.206745 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894144 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894144 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1343 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1348 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 102559731 # Number of tag accesses -system.cpu.icache.tags.data_accesses 102559731 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 51272141 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 51272141 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 51272141 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 51272141 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 51272141 # number of overall hits -system.cpu.icache.overall_hits::total 51272141 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5679 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5679 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5679 # 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number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8296 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.846587 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.866134 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.850432 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.975686 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.975686 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.846587 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.949632 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.898867 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.846587 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.949632 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.898867 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76149.277457 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81116.493656 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77144.557430 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79628.833866 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79628.833866 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76149.277457 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79951.526145 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78187.307228 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76149.277457 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79951.526145 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78187.307228 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -901,102 +901,102 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3462 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 866 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4328 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3460 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 867 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4327 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3130 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3462 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3996 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7458 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3996 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7458 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195982250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54610500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250592750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193350250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193350250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195982250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 247960750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 443943000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195982250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 247960750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 443943000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867735 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850462 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.977209 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.977209 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.899421 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.899421 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56609.546505 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63060.623557 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57900.358133 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61773.242812 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61773.242812 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56609.546505 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62052.239740 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59525.744167 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56609.546505 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62052.239740 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59525.744167 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3460 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3997 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7457 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3460 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3997 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7457 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 220205500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 59518000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 279723500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 210540750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 210540750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 220205500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 270058750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 490264250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 220205500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 270058750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 490264250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866134 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850432 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.975686 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.975686 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.949632 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.898867 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.949632 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.898867 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63643.208092 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68648.212226 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64646.059626 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67265.415335 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67265.415335 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63643.208092 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67565.361521 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65745.507577 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63643.208092 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67565.361521 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65745.507577 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5089 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5089 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 674 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3203 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3203 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8182 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9076 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17258 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 5088 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5088 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3208 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8174 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9100 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17274 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 313024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 574592 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8966 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 8978 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 8966 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8978 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8966 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5157000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 8978 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5171000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6787250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6830250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6700250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6882750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4328 # Transaction distribution -system.membus.trans_dist::ReadResp 4328 # Transaction distribution +system.membus.trans_dist::ReadReq 4327 # Transaction distribution +system.membus.trans_dist::ReadResp 4327 # Transaction distribution system.membus.trans_dist::ReadExReq 3130 # Transaction distribution system.membus.trans_dist::ReadExResp 3130 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14916 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14914 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14914 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 477248 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7458 # Request fanout histogram +system.membus.snoop_fanout::samples 7457 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7458 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7457 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7458 # Request fanout histogram -system.membus.reqLayer0.occupancy 9422500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7457 # Request fanout histogram +system.membus.reqLayer0.occupancy 9341500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69712000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 39310250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 01baacd99..97440304f 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.567335 # Number of seconds simulated -sim_ticks 567335093000 # Number of ticks simulated -final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 567335093500 # Number of ticks simulated +final_tick 567335093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1606485 # Simulator instruction rate (inst/s) -host_op_rate 1606484 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2286169690 # Simulator tick rate (ticks/s) -host_mem_usage 295576 # Number of bytes of host memory used -host_seconds 248.16 # Real time elapsed on the host +host_inst_rate 1360508 # Simulator instruction rate (inst/s) +host_op_rate 1360508 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1936123010 # Simulator tick rate (ticks/s) +host_mem_usage 299124 # Number of bytes of host memory used +host_seconds 293.03 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,29 +29,6 @@ system.physmem.bw_inst_read::total 361550 # In system.physmem.bw_total::cpu.inst 361550 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 447735 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 809285 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 4032 # Transaction distribution -system.membus.trans_dist::ReadResp 4032 # Transaction distribution -system.membus.trans_dist::ReadExReq 3142 # Transaction distribution -system.membus.trans_dist::ReadExResp 3142 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7174 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7174 # Request fanout histogram -system.membus.reqLayer0.occupancy 7174000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 64566000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 1134670186 # number of cpu cycles simulated +system.cpu.numCycles 1134670187 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664609 # Number of instructions committed @@ -105,7 +82,7 @@ system.cpu.num_mem_refs 168275276 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134670186 # Number of busy cycles +system.cpu.num_busy_cycles 1134670187 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 44587535 # Number of branches fetched @@ -144,13 +121,122 @@ system.cpu.op_class::MemWrite 73520765 18.44% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664665 # Class of executed instruction +system.cpu.dcache.tags.replacements 764 # number of replacements +system.cpu.dcache.tags.tagsinuse 3288.930570 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930570 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 210 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits +system.cpu.dcache.overall_hits::total 168271068 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses +system.cpu.dcache.overall_misses::total 4152 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 649 # number of writebacks +system.cpu.dcache.writebacks::total 649 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45659000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 45659000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 168787000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 168787000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214446000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 214446000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214446000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 214446000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48062.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48062.105263 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52712.991880 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52712.991880 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51648.843931 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51648.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51648.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51648.843931 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1769 # number of replacements -system.cpu.icache.tags.tagsinuse 1795.138964 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1795.138960 # Cycle average of tags in use system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138960 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id @@ -174,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses system.cpu.icache.overall_misses::total 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 182359000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 182359000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 182359000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 182359000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 182359000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 182359000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 182359500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 182359500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 182359500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 182359500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 182359500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 182359500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses @@ -192,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49648.516199 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49648.516199 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49648.516199 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49648.516199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49648.516199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49648.516199 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49648.652328 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49648.652328 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49648.652328 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49648.652328 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49648.652328 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49648.652328 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,34 +298,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3673 system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175013000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 175013000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175013000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 175013000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175013000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 175013000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176850000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 176850000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176850000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 176850000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176850000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 176850000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47648.516199 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47648.516199 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48148.652328 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48148.652328 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48148.652328 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48148.652328 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48148.652328 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48148.652328 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3772.485305 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3772.485298 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 677 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.148270 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 371.540220 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469918 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475159 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy @@ -277,17 +363,17 @@ system.cpu.l2cache.demand_misses::total 7174 # nu system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7174 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 166660000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43004000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 209664000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163384000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 163384000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 166660000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 206388000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 373048000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 166660000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 206388000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 373048000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 168263000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43417500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 211680500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164955000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 164955000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 168263000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 208372500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 376635500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 168263000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 208372500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 376635500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3673 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 950 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4623 # number of ReadReq accesses(hits+misses) @@ -312,17 +398,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.916805 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.156006 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.124008 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.156006 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.069696 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.156006 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.069696 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -342,17 +428,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7174 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 125680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 125680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158760000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 286960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158760000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 286960000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 129802500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33493500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163296000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 127251000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 127251000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129802500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160744500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 290547000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129802500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160744500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 290547000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.872161 # mshr miss rate for ReadReq accesses @@ -364,127 +450,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3288.930576 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 210 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits -system.cpu.dcache.overall_hits::total 168271068 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses -system.cpu.dcache.overall_misses::total 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 649 # number of writebacks -system.cpu.dcache.writebacks::total 649 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution @@ -514,5 +491,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 5509500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 4032 # Transaction distribution +system.membus.trans_dist::ReadResp 4032 # Transaction distribution +system.membus.trans_dist::ReadExReq 3142 # Transaction distribution +system.membus.trans_dist::ReadExResp 3142 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7174 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7174 # Request fanout histogram +system.membus.reqLayer0.occupancy 7174500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 35870500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index dd174365b..32197bf04 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.216828 # Number of seconds simulated -sim_ticks 216828260500 # Number of ticks simulated -final_tick 216828260500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.216865 # Number of seconds simulated +sim_ticks 216864820000 # Number of ticks simulated +final_tick 216864820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113548 # Simulator instruction rate (inst/s) -host_op_rate 136327 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90171945 # Simulator tick rate (ticks/s) -host_mem_usage 309844 # Number of bytes of host memory used -host_seconds 2404.61 # Real time elapsed on the host +host_inst_rate 175540 # Simulator instruction rate (inst/s) +host_op_rate 210755 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 139425507 # Simulator tick rate (ticks/s) +host_mem_usage 321524 # Number of bytes of host memory used +host_seconds 1555.42 # Real time elapsed on the host sim_insts 273037856 # Number of instructions simulated sim_ops 327812213 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 219008 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory -system.physmem.bytes_read::total 485440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 485376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3422 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7585 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1010348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1228475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2238823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1010348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1010348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1010348 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1228475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2238823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7585 # Number of read requests accepted +system.physmem.num_reads::total 7584 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1009883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1228267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2238150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1009883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1009883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1009883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1228267 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2238150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7584 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7585 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7584 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485440 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 485376 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485440 # Total read bytes from the system interface side +system.physmem.bytesReadSys 485376 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -53,7 +53,7 @@ system.physmem.perBankRdBursts::8 209 # Pe system.physmem.perBankRdBursts::9 311 # Per bank write bursts system.physmem.perBankRdBursts::10 342 # Per bank write bursts system.physmem.perBankRdBursts::11 428 # Per bank write bursts -system.physmem.perBankRdBursts::12 554 # Per bank write bursts +system.physmem.perBankRdBursts::12 553 # Per bank write bursts system.physmem.perBankRdBursts::13 706 # Per bank write bursts system.physmem.perBankRdBursts::14 637 # Per bank write bursts system.physmem.perBankRdBursts::15 541 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 216828031000 # Total gap between requests +system.physmem.totGap 216864583500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7585 # Read request sizes (log2) +system.physmem.readPktSize::6 7584 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 896 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6626 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1505 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.360797 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.304771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.736324 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 549 36.48% 36.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 346 22.99% 59.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 165 10.96% 70.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 68 4.52% 74.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 70 4.65% 79.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 58 3.85% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 34 2.26% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 33 2.19% 87.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 182 12.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1505 # Bytes accessed per row activation -system.physmem.totQLat 50845500 # Total ticks spent queuing -system.physmem.totMemAccLat 193064250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6703.43 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 317.772817 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.476979 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.358112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 549 36.05% 36.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 352 23.11% 59.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 179 11.75% 70.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 73 4.79% 75.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 70 4.60% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 53 3.48% 83.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.43% 86.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 29 1.90% 88.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 181 11.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation +system.physmem.totQLat 53728750 # Total ticks spent queuing +system.physmem.totMemAccLat 195928750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37920000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7084.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25453.43 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25834.49 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6073 # Number of row buffer hits during reads +system.physmem.readRowHits 6056 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.07 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.85 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28586424.65 # Average gap between requests -system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28595013.65 # Average gap between requests +system.physmem.pageHitRate 79.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5652564030 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 125135988750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 144988075455 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.690273 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 208174326250 # Time in different power states -system.physmem_0.memoryStateTime::REF 7240220000 # Time in different power states +system.physmem_0.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5668320825 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 125145525750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 145015982220 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.698913 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 208188918000 # Time in different power states +system.physmem_0.memoryStateTime::REF 7241520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1410814750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1432738500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6342840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3460875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 29031600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5745534165 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 125054436000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 145000644600 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.748242 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 208036674250 # Time in different power states -system.physmem_1.memoryStateTime::REF 7240220000 # Time in different power states +system.physmem_1.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5831746380 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 125002170000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 145037386830 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.797614 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 207947266000 # Time in different power states +system.physmem_1.memoryStateTime::REF 7241520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1549163250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1674122750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 33221230 # Number of BP lookups -system.cpu.branchPred.condPredicted 17174007 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1583983 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17995686 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15666979 # Number of BTB hits +system.cpu.branchPred.lookups 33219592 # Number of BP lookups +system.cpu.branchPred.condPredicted 17177082 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1581285 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17974979 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15661112 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.059638 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6611215 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 87.127290 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6612085 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,75 +377,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 433656521 # number of cpu cycles simulated +system.cpu.numCycles 433729640 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037856 # Number of instructions committed system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4064410 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4054235 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.588265 # CPI: cycles per instruction -system.cpu.ipc 0.629618 # IPC: instructions per cycle -system.cpu.tickCycles 430211127 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3445394 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.588533 # CPI: cycles per instruction +system.cpu.ipc 0.629512 # IPC: instructions per cycle +system.cpu.tickCycles 430193160 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3536480 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3086.009488 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168783807 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.768991 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168782225 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37416.051208 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37415.700510 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3086.009488 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753420 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753420 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768991 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753362 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753362 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337586705 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337586705 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86714567 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86714567 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047450 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047450 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 337583521 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337583521 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86712977 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86712977 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047458 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047458 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168762017 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168762017 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168762017 # number of overall hits -system.cpu.dcache.overall_hits::total 168762017 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2063 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2063 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5227 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5227 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 7290 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7290 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses -system.cpu.dcache.overall_misses::total 7290 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 126489706 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 126489706 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 360451750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 360451750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 486941456 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 486941456 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 486941456 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 486941456 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86716630 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86716630 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168760435 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168760435 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168760435 # number of overall hits +system.cpu.dcache.overall_hits::total 168760435 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2061 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2061 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5219 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5219 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 7280 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7280 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7280 # number of overall misses +system.cpu.dcache.overall_misses::total 7280 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 137684956 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 137684956 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 400150250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 400150250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 537835206 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 537835206 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 537835206 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 537835206 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86715038 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86715038 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168769307 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168769307 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168769307 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168769307 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168767715 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168767715 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168767715 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168767715 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -454,14 +454,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61313.478429 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61313.478429 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68959.584848 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68959.584848 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66795.810151 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66795.810151 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66795.810151 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66795.810151 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66804.927705 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66804.927705 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76671.824104 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76671.824104 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73878.462363 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73878.462363 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,14 +472,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks system.cpu.dcache.writebacks::total 1010 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2357 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2779 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2779 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 420 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 420 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2349 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2349 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2769 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2769 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2769 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2769 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1641 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -488,14 +488,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4511 system.cpu.dcache.demand_mshr_misses::total 4511 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 100259792 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 100259792 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 197855250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 197855250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298115042 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 298115042 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298115042 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 298115042 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109745542 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109745542 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219964750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 219964750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329710292 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 329710292 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329710292 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 329710292 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -504,69 +504,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61096.765387 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61096.765387 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68939.111498 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68939.111498 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66086.242962 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66086.242962 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66877.234613 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66877.234613 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76642.770035 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76642.770035 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 36927 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.993634 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73270394 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 38864 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1885.302439 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 36897 # number of replacements +system.cpu.icache.tags.tagsinuse 1924.852609 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73252005 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 38834 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1886.285343 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.993634 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939938 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939938 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852609 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939869 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939869 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146657382 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146657382 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73270394 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73270394 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73270394 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73270394 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73270394 # number of overall hits -system.cpu.icache.overall_hits::total 73270394 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 38865 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 38865 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 38865 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 38865 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 38865 # number of overall misses -system.cpu.icache.overall_misses::total 38865 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 703218247 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 703218247 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 703218247 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 703218247 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 703218247 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 703218247 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73309259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73309259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73309259 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73309259 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73309259 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73309259 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 146620514 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146620514 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73252005 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73252005 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73252005 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73252005 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73252005 # number of overall hits +system.cpu.icache.overall_hits::total 73252005 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 38835 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 38835 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 38835 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 38835 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 38835 # number of overall misses +system.cpu.icache.overall_misses::total 38835 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 728456748 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 728456748 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 728456748 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 728456748 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 728456748 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 728456748 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 73290840 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 73290840 # 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number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4730 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3422 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 4162 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7585 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7584 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3422 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7585 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187452250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 77027000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264479250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 158825750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158825750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187452250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 235852750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 423305000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187452250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 235852750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 423305000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 7584 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 215130250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85732250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 300862500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181193250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181193250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 215130250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266925500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 482055750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215130250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266925500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 482055750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116798 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116859 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.174866 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.174964 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.174866 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.562080 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58889.143731 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55903.455929 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55650.227751 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55650.227751 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54762.562080 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56668.128304 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54762.562080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56668.128304 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.174964 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62866.817650 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65544.533639 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63607.293869 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63487.473721 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63487.473721 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 40506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 40505 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 40476 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 40475 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77729 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77669 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 87761 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2487296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 87701 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2485376 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2840640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2838720 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 44386 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 44356 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 44386 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 44356 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 44386 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 23203000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 44356 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 23188000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 58996747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 58975248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7500458 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7577708 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4731 # Transaction distribution -system.membus.trans_dist::ReadResp 4731 # Transaction distribution +system.membus.trans_dist::ReadReq 4730 # Transaction distribution +system.membus.trans_dist::ReadResp 4730 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15170 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15170 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15168 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485376 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7585 # Request fanout histogram +system.membus.snoop_fanout::samples 7584 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7585 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7584 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7585 # Request fanout histogram -system.membus.reqLayer0.occupancy 8964000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7584 # Request fanout histogram +system.membus.reqLayer0.occupancy 8969500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 71030500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40264250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 2e0077bb1..869d3326a 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.112624 # Number of seconds simulated -sim_ticks 112623767500 # Number of ticks simulated -final_tick 112623767500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.112554 # Number of seconds simulated +sim_ticks 112553814500 # Number of ticks simulated +final_tick 112553814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123996 # Simulator instruction rate (inst/s) -host_op_rate 148871 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51146556 # Simulator tick rate (ticks/s) -host_mem_usage 325020 # Number of bytes of host memory used -host_seconds 2201.98 # Real time elapsed on the host +host_inst_rate 125235 # Simulator instruction rate (inst/s) +host_op_rate 150358 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51625290 # Simulator tick rate (ticks/s) +host_mem_usage 326264 # Number of bytes of host memory used +host_seconds 2180.21 # Real time elapsed on the host sim_insts 273037219 # Number of instructions simulated sim_ops 327811601 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 169856 # Number of bytes read from this memory -system.physmem.bytes_read::total 469120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2654 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7330 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1661035 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 996166 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1508172 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4165373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1661035 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1661035 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1661035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 996166 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1508172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4165373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7330 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 187136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 114176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 167616 # Number of bytes read from this memory +system.physmem.bytes_read::total 468928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 187136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 187136 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2924 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1784 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2619 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7327 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1662636 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1014413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1489208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4166256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1662636 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1662636 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1662636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1014413 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1489208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4166256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7327 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7330 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7327 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 469120 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 468928 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 469120 # Total read bytes from the system interface side +system.physmem.bytesReadSys 468928 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -48,14 +48,14 @@ system.physmem.neitherReadNorWriteReqs 1 # Nu system.physmem.perBankRdBursts::0 589 # Per bank write bursts system.physmem.perBankRdBursts::1 789 # Per bank write bursts system.physmem.perBankRdBursts::2 601 # Per bank write bursts -system.physmem.perBankRdBursts::3 519 # Per bank write bursts +system.physmem.perBankRdBursts::3 520 # Per bank write bursts system.physmem.perBankRdBursts::4 444 # Per bank write bursts system.physmem.perBankRdBursts::5 346 # Per bank write bursts system.physmem.perBankRdBursts::6 153 # Per bank write bursts -system.physmem.perBankRdBursts::7 257 # Per bank write bursts +system.physmem.perBankRdBursts::7 255 # Per bank write bursts system.physmem.perBankRdBursts::8 219 # Per bank write bursts -system.physmem.perBankRdBursts::9 291 # Per bank write bursts -system.physmem.perBankRdBursts::10 316 # Per bank write bursts +system.physmem.perBankRdBursts::9 290 # Per bank write bursts +system.physmem.perBankRdBursts::10 315 # Per bank write bursts system.physmem.perBankRdBursts::11 411 # Per bank write bursts system.physmem.perBankRdBursts::12 547 # Per bank write bursts system.physmem.perBankRdBursts::13 678 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 112623613500 # Total gap between requests +system.physmem.totGap 112553656000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7330 # Read request sizes (log2) +system.physmem.readPktSize::6 7327 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,19 +94,19 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -190,26 +190,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 340.446389 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 197.878789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.729899 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 488 35.59% 35.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 298 21.74% 57.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 137 9.99% 67.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 90 6.56% 73.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 49 3.57% 77.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 55 4.01% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 23 1.68% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 26 1.90% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 205 14.95% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1371 # Bytes accessed per row activation -system.physmem.totQLat 100359280 # Total ticks spent queuing -system.physmem.totMemAccLat 237796780 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36650000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13691.58 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1397 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 334.064424 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 193.482672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.087808 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 504 36.08% 36.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 315 22.55% 58.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 145 10.38% 69.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 78 5.58% 74.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 51 3.65% 78.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 45 3.22% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 28 2.00% 83.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 21 1.50% 84.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 210 15.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1397 # Bytes accessed per row activation +system.physmem.totQLat 96387273 # Total ticks spent queuing +system.physmem.totMemAccLat 233768523 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36635000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13155.08 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32441.58 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31905.08 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.17 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s @@ -218,51 +218,51 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5950 # Number of row buffer hits during reads +system.physmem.readRowHits 5921 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.17 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.81 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15364749.45 # Average gap between requests -system.physmem.pageHitRate 81.17 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4906440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2677125 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 15361492.56 # Average gap between requests +system.physmem.pageHitRate 80.81 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4883760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2664750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 28688400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7355811840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3232257390 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 64737034500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 75361375695 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.161673 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 107692958200 # Time in different power states -system.physmem_0.memoryStateTime::REF 3760640000 # Time in different power states +system.physmem_0.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3253381020 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64676459250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 75317311980 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.186805 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 107592163396 # Time in different power states +system.physmem_0.memoryStateTime::REF 3758300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1167342300 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1200480604 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5435640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2965875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 28165800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5654880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3085500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28158000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7355811840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3291484950 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 64685080500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 75368944605 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.228880 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 107605030400 # Time in different power states -system.physmem_1.memoryStateTime::REF 3760640000 # Time in different power states +system.physmem_1.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3298234320 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 64637123250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 75323490750 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.241613 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 107525247142 # Time in different power states +system.physmem_1.memoryStateTime::REF 3758300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1254923350 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1266984612 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37762202 # Number of BP lookups -system.cpu.branchPred.condPredicted 20178978 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1746186 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18669843 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17301885 # Number of BTB hits +system.cpu.branchPred.lookups 37745757 # Number of BP lookups +system.cpu.branchPred.condPredicted 20165080 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1746215 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18666199 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17299874 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.672900 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7228775 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3814 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.680218 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7225607 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,234 +381,234 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 225247536 # number of cpu cycles simulated +system.cpu.numCycles 225107630 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12260997 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 334142837 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37762202 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24530660 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 210950106 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3511423 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1112 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 2317 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 89109626 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 21670 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 224970243 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.801560 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12251626 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 334050460 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37745757 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24525481 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 210773788 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3510701 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1259 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 2425 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 89095014 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 21830 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 224784448 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.802641 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228554 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 51235855 22.77% 22.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42807602 19.03% 41.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30290628 13.46% 55.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100636158 44.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 51100209 22.73% 22.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42897495 19.08% 41.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30052167 13.37% 55.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100734577 44.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 224970243 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.167648 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.483447 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27756041 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64007493 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108311444 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 23274289 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1620976 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6880269 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 135184 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 363488172 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6272061 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1620976 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45214868 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13194135 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 339970 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 113472539 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51127755 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355731319 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 2913591 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 6682784 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 150888 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7653578 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 21157029 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 7934488 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 403383639 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2533813915 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 350195205 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 194873173 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 224784448 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.167679 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.483959 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27670459 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63847459 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108576617 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 23069322 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1620591 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6880031 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 135198 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 363530052 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6167703 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1620591 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44985233 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 17899875 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 341878 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 113387886 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46548985 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355747640 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 2899285 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 6598470 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 195112 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7751940 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 21223571 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 2892429 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 403401871 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2533892950 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 350207607 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 194891234 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31153588 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 17052 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 55396743 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 92428788 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 88464605 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1673696 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1845347 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 353205084 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28025 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 346266425 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2344670 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24805703 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73566871 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 5905 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 224970243 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.539165 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101848 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 31171820 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17015 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 17024 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 55320329 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 92416671 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 88482299 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1659115 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1844729 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353235129 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28024 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 346404668 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2300304 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24831082 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73599170 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 5904 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 224784448 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.541053 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.099675 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40745402 18.11% 18.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 78348887 34.83% 52.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 60751762 27.00% 79.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34737500 15.44% 95.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9740629 4.33% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 637380 0.28% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8683 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40431348 17.99% 17.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78272117 34.82% 52.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 61035980 27.15% 79.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34788778 15.48% 95.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9595638 4.27% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 651817 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8770 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 224970243 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 224784448 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9315798 7.51% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7337 0.01% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 233455 0.19% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 152510 0.12% 7.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 103371 0.08% 7.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 37180 0.03% 7.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 820015 0.66% 8.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 318375 0.26% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 687813 0.55% 9.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53407928 43.05% 52.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58972553 47.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9471276 7.62% 7.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7330 0.01% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 257049 0.21% 7.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 126990 0.10% 7.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 92940 0.07% 8.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 68000 0.05% 8.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 719474 0.58% 8.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 316340 0.25% 8.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 682824 0.55% 9.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53604156 43.13% 52.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58946138 47.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 110648263 31.95% 31.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148166 0.62% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6796965 1.96% 34.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8667386 2.50% 37.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3331882 0.96% 38.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592439 0.46% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20937021 6.05% 44.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7180792 2.07% 46.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147105 2.06% 48.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 91783076 26.51% 75.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85858044 24.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 110656025 31.94% 31.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148357 0.62% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6798490 1.96% 34.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8668315 2.50% 37.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3332477 0.96% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592461 0.46% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20930112 6.04% 44.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7182294 2.07% 46.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148952 2.06% 48.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 91886799 26.53% 75.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85885100 24.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 346266425 # Type of FU issued -system.cpu.iq.rate 1.537271 # Inst issue rate -system.cpu.iq.fu_busy_cnt 124056335 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.358268 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 756639732 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 251256110 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 223226406 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 287264366 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 126793395 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 117417412 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302952760 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 167370000 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5033832 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 346404668 # Type of FU issued +system.cpu.iq.rate 1.538840 # Inst issue rate +system.cpu.iq.fu_busy_cnt 124292517 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.358807 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 756686876 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 251306416 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 223263085 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287499729 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 126798006 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117424806 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 303164482 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 167532703 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5066223 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6696513 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13646 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10697 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6088988 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6684396 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13685 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10191 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6106682 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 151171 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 488903 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 154303 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 567640 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1620976 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2121777 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 321028 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 353233977 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1620591 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2121620 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 330440 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353264020 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 92428788 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 88464605 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 16992 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8078 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 328775 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10697 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1220281 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 438299 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1658580 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 342303629 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 90585110 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3962796 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 92416671 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 88482299 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 16991 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 8046 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 336925 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10191 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1220622 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 439103 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1659725 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 342414286 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 90666955 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3990382 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 868 # number of nop insts executed -system.cpu.iew.exec_refs 175167602 # number of memory reference insts executed -system.cpu.iew.exec_branches 31752029 # Number of branches executed -system.cpu.iew.exec_stores 84582492 # Number of stores executed -system.cpu.iew.exec_rate 1.519678 # Inst execution rate -system.cpu.iew.wb_sent 340903564 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 340643818 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153542130 # num instructions producing a value -system.cpu.iew.wb_consumers 265815285 # num instructions consuming a value +system.cpu.iew.exec_nop 867 # number of nop insts executed +system.cpu.iew.exec_refs 175255989 # number of memory reference insts executed +system.cpu.iew.exec_branches 31752931 # Number of branches executed +system.cpu.iew.exec_stores 84589034 # Number of stores executed +system.cpu.iew.exec_rate 1.521114 # Inst execution rate +system.cpu.iew.wb_sent 340946352 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 340687891 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153731206 # num instructions producing a value +system.cpu.iew.wb_consumers 266896125 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.512309 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.577627 # average fanout of values written-back +system.cpu.iew.wb_rate 1.513444 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.575996 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 22999072 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23077118 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1611451 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 221242338 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481688 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.053337 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1611456 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 221059297 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.482915 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.052167 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87860442 39.71% 39.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 69868164 31.58% 71.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20927833 9.46% 80.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13474111 6.09% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8800250 3.98% 90.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4584845 2.07% 92.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2913190 1.32% 94.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2446339 1.11% 95.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10367164 4.69% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87356112 39.52% 39.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 70369552 31.83% 71.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20804455 9.41% 80.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13442204 6.08% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8808979 3.98% 90.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4514912 2.04% 92.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2991653 1.35% 94.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2424695 1.10% 95.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10346735 4.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 221242338 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 221059297 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037831 # Number of instructions committed system.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,387 +654,387 @@ system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction -system.cpu.commit.bw_lim_events 10367164 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 10346735 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 561683936 # The number of ROB reads -system.cpu.rob.rob_writes 705354391 # The number of ROB writes -system.cpu.timesIdled 50923 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 277293 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 561599370 # The number of ROB reads +system.cpu.rob.rob_writes 705507733 # The number of ROB writes +system.cpu.timesIdled 50679 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 323182 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037219 # Number of Instructions Simulated system.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.824970 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.824970 # CPI: Total CPI of All Threads -system.cpu.ipc 1.212165 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.212165 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 331186150 # number of integer regfile reads -system.cpu.int_regfile_writes 136908474 # number of integer regfile writes -system.cpu.fp_regfile_reads 187099872 # number of floating regfile reads -system.cpu.fp_regfile_writes 132166295 # number of floating regfile writes -system.cpu.cc_regfile_reads 1296656595 # number of cc regfile reads -system.cpu.cc_regfile_writes 80246016 # number of cc regfile writes -system.cpu.misc_regfile_reads 1182266137 # number of misc regfile reads +system.cpu.cpi 0.824458 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.824458 # CPI: Total CPI of All Threads +system.cpu.ipc 1.212919 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.212919 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 331300708 # number of integer regfile reads +system.cpu.int_regfile_writes 136940215 # number of integer regfile writes +system.cpu.fp_regfile_reads 187107289 # number of floating regfile reads +system.cpu.fp_regfile_writes 132177847 # number of floating regfile writes +system.cpu.cc_regfile_reads 1297030245 # number of cc regfile reads +system.cpu.cc_regfile_writes 80242169 # number of cc regfile writes +system.cpu.misc_regfile_reads 1182847920 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1533739 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.852624 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 163803903 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1534251 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 106.764736 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 77087500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.852624 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999712 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999712 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1533856 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.843197 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 163689216 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1534368 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 106.681849 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 83394000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.843197 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999694 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999694 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336684823 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336684823 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 82726313 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 82726313 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80985354 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80985354 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 70429 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 70429 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10910 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10910 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 336633502 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336633502 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82631348 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82631348 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80965582 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80965582 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 70480 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 70480 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 163711667 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 163711667 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 163782096 # number of overall hits -system.cpu.dcache.overall_hits::total 163782096 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2704016 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2704016 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1067345 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1067345 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 19 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 19 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 163596930 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 163596930 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 163667410 # number of overall hits +system.cpu.dcache.overall_hits::total 163667410 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2773213 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2773213 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1087117 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1087117 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3771361 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3771361 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3771380 # number of overall misses -system.cpu.dcache.overall_misses::total 3771380 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 21429430210 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 21429430210 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8382362067 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8382362067 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 174750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 174750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29811792277 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29811792277 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29811792277 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29811792277 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 85430329 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 85430329 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3860330 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3860330 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3860348 # number of overall misses +system.cpu.dcache.overall_misses::total 3860348 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22349106216 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22349106216 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8902471046 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8902471046 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 189750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31251577262 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31251577262 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31251577262 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31251577262 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85404561 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85404561 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 70448 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 70448 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10915 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10915 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 70498 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 70498 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167483028 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167483028 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167553476 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167553476 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031652 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.031652 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013008 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013008 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000270 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000270 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 167457260 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167457260 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167527758 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167527758 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032471 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032471 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013249 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013249 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000255 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.022518 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.022518 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.022509 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.022509 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7925.038243 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 7925.038243 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7853.470122 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7853.470122 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 34950 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 34950 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 7904.783519 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 7904.783519 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 7904.743695 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 7904.743695 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023053 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023053 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023043 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023043 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8058.921625 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 8058.921625 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8189.064329 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8189.064329 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37950 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37950 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8095.571431 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8095.571431 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8095.533683 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8095.533683 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 768686 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 918314 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 111802 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 117385 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 6.875423 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.823095 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 966281 # number of writebacks -system.cpu.dcache.writebacks::total 966281 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390263 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1390263 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 846856 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 846856 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 966341 # number of writebacks +system.cpu.dcache.writebacks::total 966341 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1459499 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1459499 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866472 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 866472 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2237119 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2237119 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2237119 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2237119 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313753 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1313753 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220489 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220489 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2325971 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2325971 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2325971 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2325971 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313714 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1313714 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220645 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220645 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1534242 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1534242 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1534253 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1534253 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9313835285 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9313835285 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1599508327 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1599508327 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 613250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 613250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10913343612 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10913343612 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10913956862 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10913956862 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015378 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015378 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002687 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002687 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1534359 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1534359 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1534370 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1534370 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9969290033 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9969290033 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1717345064 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1717345064 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1161750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1161750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686635097 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11686635097 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11687796847 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11687796847 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002689 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009161 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.009161 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009157 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.009157 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7089.487358 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7089.487358 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7254.367914 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7254.367914 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 55750 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 55750 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7113.182674 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7113.182674 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7113.531381 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7113.531381 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7588.630427 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7588.630427 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7783.294722 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7783.294722 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 105613.636364 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 105613.636364 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7616.623683 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7616.623683 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7617.326230 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7617.326230 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 715275 # number of replacements -system.cpu.icache.tags.tagsinuse 511.840362 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 88389408 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 715787 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 123.485629 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 315060000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.840362 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999688 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999688 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 715719 # number of replacements +system.cpu.icache.tags.tagsinuse 511.828705 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88373879 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 716231 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 123.387397 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 326261250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.828705 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999665 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999665 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 68 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 244 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 178935006 # Number of tag accesses -system.cpu.icache.tags.data_accesses 178935006 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 88389408 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88389408 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88389408 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88389408 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88389408 # number of overall hits -system.cpu.icache.overall_hits::total 88389408 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 720201 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 720201 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 720201 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 720201 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 720201 # number of overall misses -system.cpu.icache.overall_misses::total 720201 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5943843584 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5943843584 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5943843584 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5943843584 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5943843584 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5943843584 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 89109609 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 89109609 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 89109609 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 89109609 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 89109609 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 89109609 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008082 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008082 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008082 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008082 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008082 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008082 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8253.034339 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8253.034339 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8253.034339 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8253.034339 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8253.034339 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8253.034339 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 51882 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 52 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1935 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 178906226 # Number of tag accesses +system.cpu.icache.tags.data_accesses 178906226 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 88373879 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88373879 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88373879 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88373879 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88373879 # number of overall hits +system.cpu.icache.overall_hits::total 88373879 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 721118 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 721118 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 721118 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 721118 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 721118 # number of overall misses +system.cpu.icache.overall_misses::total 721118 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5972962690 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5972962690 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5972962690 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5972962690 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5972962690 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5972962690 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 89094997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 89094997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 89094997 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 89094997 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 89094997 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 89094997 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008094 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008094 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008094 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008094 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008094 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008094 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8282.919980 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8282.919980 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8282.919980 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8282.919980 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8282.919980 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8282.919980 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 60262 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2026 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 26.812403 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 17.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.744324 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 31.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4413 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4413 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4413 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4413 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4413 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 4812391061 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 4812391061 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008033 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008033 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008033 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008033 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008033 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008033 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6723.207236 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6723.207236 # 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number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 220487 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 220487 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 714884 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1534251 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2249135 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 714884 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1534251 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2249135 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004104 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72978.393162 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69620.542126 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23499 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23499 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71048.337438 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71048.337438 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68415.834412 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72138.068633 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69862.077500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68415.834412 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72138.068633 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69862.077500 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1044,141 +1044,139 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 33 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 98 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 98 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 34 # 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number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 727 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 727 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2923 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 4676 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2923 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30530 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 35206 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 153898250 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 255210250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 153898250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101312000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 204942291 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 460152541 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000781 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001947 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 765 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 765 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2924 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1784 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4708 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2924 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1784 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30395 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 35103 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175338026 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 66096002 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 241434028 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 176500042 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 176500042 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49863251 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49863251 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175338026 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115959253 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 291297279 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175338026 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115959253 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 176500042 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 467797321 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000776 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001943 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003297 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003297 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001143 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.002079 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001143 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003467 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003467 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001163 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.002093 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001163 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.015653 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52650.786863 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58441.033138 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54155.165865 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6712.816607 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 6712.816607 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56879.642366 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56879.642366 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52650.786863 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57793.496863 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54578.753208 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52650.786863 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57793.496863 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6712.816607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13070.287479 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.015603 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59965.125171 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64863.593719 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61231.049455 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5806.877513 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5806.877513 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65180.720261 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65180.720261 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59965.125171 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64999.581278 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61872.829014 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59965.125171 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64999.581278 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5806.877513 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13326.419993 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2029552 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2029552 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 966281 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 32098 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2029957 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2029957 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 966341 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 31800 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220487 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220487 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430672 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034787 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5465459 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45752576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205786624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 33002 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3248420 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.009881 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.098911 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 220643 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220643 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1431558 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4035081 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5466639 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45780864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160045376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205826240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 32706 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3248743 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.009788 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.098451 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3216322 99.01% 99.01% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 32098 0.99% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3216943 99.02% 99.02% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 31800 0.98% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3248420 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2574443497 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3248743 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2574812500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1074521893 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1075185997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2301598998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2301792968 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 6603 # Transaction distribution -system.membus.trans_dist::ReadResp 6603 # Transaction distribution +system.membus.trans_dist::ReadReq 6562 # Transaction distribution +system.membus.trans_dist::ReadResp 6562 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 727 # Transaction distribution -system.membus.trans_dist::ReadExResp 727 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14662 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14662 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 469120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 469120 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 765 # Transaction distribution +system.membus.trans_dist::ReadExResp 765 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14656 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14656 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 468928 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7331 # Request fanout histogram +system.membus.snoop_fanout::samples 7328 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7331 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7328 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7331 # Request fanout histogram -system.membus.reqLayer0.occupancy 9338317 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7328 # Request fanout histogram +system.membus.reqLayer0.occupancy 9247379 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 68128868 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 38369962 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 8e74d72ee..833e406c9 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu sim_ticks 201717313500 # Number of ticks simulated final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1117455 # Simulator instruction rate (inst/s) -host_op_rate 1341629 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 825564009 # Simulator tick rate (ticks/s) -host_mem_usage 308812 # Number of bytes of host memory used -host_seconds 244.34 # Real time elapsed on the host +host_inst_rate 1235958 # Simulator instruction rate (inst/s) +host_op_rate 1483905 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 913112758 # Simulator tick rate (ticks/s) +host_mem_usage 308700 # Number of bytes of host memory used +host_seconds 220.91 # Real time elapsed on the host sim_insts 273037594 # Number of instructions simulated sim_ops 327811949 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 system.membus.pkt_size::total 2275398071 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 517024351 # Request fanout histogram -system.membus.snoop_fanout::mean 4.674359 # Request fanout histogram +system.membus.snoop_fanout::mean 2.674359 # Request fanout histogram system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 168364078 32.56% 32.56% # Request fanout histogram -system.membus.snoop_fanout::5 348660273 67.44% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 168364078 32.56% 32.56% # Request fanout histogram +system.membus.snoop_fanout::3 348660273 67.44% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 517024351 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index c39fe9424..426aa68c6 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.517235 # Number of seconds simulated -sim_ticks 517235411000 # Number of ticks simulated -final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 517235404500 # Number of ticks simulated +final_tick 517235404500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 761441 # Simulator instruction rate (inst/s) -host_op_rate 914138 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1444030997 # Simulator tick rate (ticks/s) -host_mem_usage 318052 # Number of bytes of host memory used -host_seconds 358.19 # Real time elapsed on the host +host_inst_rate 693666 # Simulator instruction rate (inst/s) +host_op_rate 832772 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1315500911 # Simulator tick rate (ticks/s) +host_mem_usage 318184 # Number of bytes of host memory used +host_seconds 393.19 # Real time elapsed on the host sim_insts 272739285 # Number of instructions simulated sim_ops 327433743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1034470822 # number of cpu cycles simulated +system.cpu.numCycles 1034470809 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 272739285 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 168107847 # nu system.cpu.num_load_insts 85732248 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1034470821.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1034470808.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 30563502 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812213 # Class of executed instruction system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3078.445039 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445039 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id @@ -251,12 +251,12 @@ system.cpu.dcache.overall_misses::cpu.data 4479 # system.cpu.dcache.overall_misses::total 4479 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157422500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157422500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 235776500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235776500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 235776500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235776500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) @@ -283,12 +283,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54812.848189 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54812.848189 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52675.714924 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52675.714924 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52640.433132 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52640.433132 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -315,16 +315,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4475 system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75909500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75909500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 153114500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 153114500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 160500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 160500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 229024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 229024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 229184500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 229184500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -335,24 +335,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47354.647536 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47354.647536 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53312.848189 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53312.848189 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51178.547486 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51178.547486 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51180.102724 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51180.102724 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1766.007658 # Cycle average of tags in use system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007658 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id @@ -376,12 +376,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 312524000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 312524000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 312524000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 312524000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 312524000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 312524000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses @@ -394,12 +394,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.737871 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20029.737871 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.737871 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20029.737871 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.737871 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20029.737871 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -414,34 +414,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 289119500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 289119500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 289119500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 289119500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 289119500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 289119500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18529.737871 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18529.737871 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18529.737871 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18529.737871 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18529.737871 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18529.737871 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3487.765017 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 341.623060 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427163 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714793 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy @@ -479,17 +479,17 @@ system.cpu.l2cache.demand_misses::total 6832 # nu system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses system.cpu.l2cache.overall_misses::total 6832 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137079500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71954500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 209034000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 150074500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 150074500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 137079500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 222029000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 359108500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137079500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 222029000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 359108500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) @@ -514,17 +514,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.340222 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52541.011882 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52636.795903 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52573.943662 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.093838 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.093838 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.011882 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.130713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52562.719555 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.011882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.130713 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52562.719555 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -544,17 +544,17 @@ system.cpu.l2cache.demand_mshr_misses::total 6832 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 105665500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55363500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161029000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115668000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115668000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 105665500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 171031500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 276697000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 105665500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 171031500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 276697000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses @@ -566,17 +566,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500.383289 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.251509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500.383289 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500.383289 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution @@ -591,19 +591,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 21079 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 21079 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) @@ -630,9 +628,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 6833 # Request fanout histogram -system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7260500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 34587500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 7bcf4595f..f83552a37 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.559962 # Number of seconds simulated -sim_ticks 559961514500 # Number of ticks simulated -final_tick 559961514500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.561963 # Number of seconds simulated +sim_ticks 561962991000 # Number of ticks simulated +final_tick 561962991000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 216839 # Simulator instruction rate (inst/s) -host_op_rate 216839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 130731039 # Simulator tick rate (ticks/s) -host_mem_usage 291560 # Number of bytes of host memory used -host_seconds 4283.31 # Real time elapsed on the host +host_inst_rate 333136 # Simulator instruction rate (inst/s) +host_op_rate 333136 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 201563357 # Simulator tick rate (ticks/s) +host_mem_usage 305440 # Number of bytes of host memory used +host_seconds 2788.02 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,45 +25,45 @@ system.physmem.num_reads::cpu.data 288600 # Nu system.physmem.num_reads::total 291519 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 333623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 32985124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33318747 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 333623 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 333623 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7621438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7621438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7621438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 333623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 32985124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40940185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 332435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 32867645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33200080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 332435 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 332435 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7594294 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7594294 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7594294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 332435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 32867645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40794373 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 291519 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted system.physmem.readBursts 291519 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18640064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17152 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 18640576 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 16640 # Total number of bytes read from write queue system.physmem.bytesWritten 4266560 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18657216 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 268 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 260 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17935 # Per bank write bursts -system.physmem.perBankRdBursts::1 18289 # Per bank write bursts -system.physmem.perBankRdBursts::2 18306 # Per bank write bursts +system.physmem.perBankRdBursts::0 17933 # Per bank write bursts +system.physmem.perBankRdBursts::1 18288 # Per bank write bursts +system.physmem.perBankRdBursts::2 18309 # Per bank write bursts system.physmem.perBankRdBursts::3 18250 # Per bank write bursts -system.physmem.perBankRdBursts::4 18167 # Per bank write bursts -system.physmem.perBankRdBursts::5 18240 # Per bank write bursts -system.physmem.perBankRdBursts::6 18320 # Per bank write bursts -system.physmem.perBankRdBursts::7 18299 # Per bank write bursts -system.physmem.perBankRdBursts::8 18230 # Per bank write bursts -system.physmem.perBankRdBursts::9 18226 # Per bank write bursts -system.physmem.perBankRdBursts::10 18219 # Per bank write bursts -system.physmem.perBankRdBursts::11 18391 # Per bank write bursts -system.physmem.perBankRdBursts::12 18259 # Per bank write bursts -system.physmem.perBankRdBursts::13 18042 # Per bank write bursts -system.physmem.perBankRdBursts::14 17977 # Per bank write bursts -system.physmem.perBankRdBursts::15 18101 # Per bank write bursts +system.physmem.perBankRdBursts::4 18165 # Per bank write bursts +system.physmem.perBankRdBursts::5 18241 # Per bank write bursts +system.physmem.perBankRdBursts::6 18322 # Per bank write bursts +system.physmem.perBankRdBursts::7 18300 # Per bank write bursts +system.physmem.perBankRdBursts::8 18229 # Per bank write bursts +system.physmem.perBankRdBursts::9 18227 # Per bank write bursts +system.physmem.perBankRdBursts::10 18214 # Per bank write bursts +system.physmem.perBankRdBursts::11 18389 # Per bank write bursts +system.physmem.perBankRdBursts::12 18260 # Per bank write bursts +system.physmem.perBankRdBursts::13 18047 # Per bank write bursts +system.physmem.perBankRdBursts::14 17980 # Per bank write bursts +system.physmem.perBankRdBursts::15 18105 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 559961438500 # Total gap between requests +system.physmem.totGap 561962908000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 475 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,20 +144,20 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 997 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4043 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 4042 # What write queue length does an incoming req see @@ -193,24 +193,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 104680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 218.802598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.854989 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 269.267896 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39513 37.75% 37.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43924 41.96% 79.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8711 8.32% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 724 0.69% 88.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 705 0.67% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 815 0.78% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1323 1.26% 91.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 784 0.75% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8181 7.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 104680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 106018 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 216.046030 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 139.156746 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 265.673827 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 41726 39.36% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42732 40.31% 79.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8674 8.18% 87.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 811 0.76% 88.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1515 1.43% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1173 1.11% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 577 0.54% 91.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 518 0.49% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8292 7.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 106018 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4042 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.196932 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.193109 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 784.958037 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.199159 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.197763 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 784.963064 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 4035 99.83% 99.83% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.85% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.95% # Reads before turning the bus around for writes @@ -219,92 +219,92 @@ system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # system.physmem.rdPerTurnAround::total 4042 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4042 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 16.493073 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.471357 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.863386 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3047 75.38% 75.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 992 24.54% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.471396 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.862526 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3046 75.36% 75.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 995 24.62% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4042 # Writes before turning the bus around for reads -system.physmem.totQLat 2985206750 # Total ticks spent queuing -system.physmem.totMemAccLat 8446163000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1456255000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10249.60 # Average queueing delay per DRAM burst +system.physmem.totQLat 2975536250 # Total ticks spent queuing +system.physmem.totMemAccLat 8436642500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1456295000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10216.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28999.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 33.29 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.62 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 33.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.62 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28966.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 33.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.59 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 33.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.32 # Data bus utilization in percentage system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing -system.physmem.readRowHits 202789 # Number of row buffer hits during reads -system.physmem.writeRowHits 50437 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes -system.physmem.avgGap 1563256.04 # Average gap between requests -system.physmem.pageHitRate 70.75 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 394057440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 215011500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1136889000 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing +system.physmem.readRowHits 201381 # Number of row buffer hits during reads +system.physmem.writeRowHits 50515 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.75 # Row buffer hit rate for writes +system.physmem.avgGap 1568843.58 # Average gap between requests +system.physmem.pageHitRate 70.37 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 399311640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 217878375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136904600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 36573600960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 108420572385 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 240867963750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 387824533515 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.597962 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 400029552000 # Time in different power states -system.physmem_0.memoryStateTime::REF 18698160000 # Time in different power states +system.physmem_0.refreshEnergy 36704300880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 110801606310 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 239979977250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 389456417535 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.035628 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 398531952000 # Time in different power states +system.physmem_0.memoryStateTime::REF 18764980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 141228516750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 144660363000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 397232640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 216744000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1134299400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 402093720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 219396375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134346200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 215550720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 36573600960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 108773347950 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 240558511500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 387869287170 # Total energy per rank (pJ) -system.physmem_1.averagePower 692.677886 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 399509975000 # Time in different power states -system.physmem_1.memoryStateTime::REF 18698160000 # Time in different power states +system.physmem_1.refreshEnergy 36704300880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 111289898520 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 239551650750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 389517237165 # Total energy per rank (pJ) +system.physmem_1.averagePower 693.143857 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 397813996000 # Time in different power states +system.physmem_1.memoryStateTime::REF 18764980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 141748516500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 145378777500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 125749069 # Number of BP lookups -system.cpu.branchPred.condPredicted 81144276 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12157130 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 103970439 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83513487 # Number of BTB hits +system.cpu.branchPred.lookups 125749002 # Number of BP lookups +system.cpu.branchPred.condPredicted 81144241 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12157248 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 103981751 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83513628 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.324261 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18691097 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 9450 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.315658 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18691101 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 9451 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237537681 # DTB read hits -system.cpu.dtb.read_misses 198468 # DTB read misses +system.cpu.dtb.read_hits 237537715 # DTB read hits +system.cpu.dtb.read_misses 198475 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237736149 # DTB read accesses -system.cpu.dtb.write_hits 98305023 # DTB write hits -system.cpu.dtb.write_misses 7212 # DTB write misses +system.cpu.dtb.read_accesses 237736190 # DTB read accesses +system.cpu.dtb.write_hits 98305031 # DTB write hits +system.cpu.dtb.write_misses 7188 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312235 # DTB write accesses -system.cpu.dtb.data_hits 335842704 # DTB hits -system.cpu.dtb.data_misses 205680 # DTB misses +system.cpu.dtb.write_accesses 98312219 # DTB write accesses +system.cpu.dtb.data_hits 335842746 # DTB hits +system.cpu.dtb.data_misses 205663 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336048384 # DTB accesses -system.cpu.itb.fetch_hits 317138761 # ITB hits +system.cpu.dtb.data_accesses 336048409 # DTB accesses +system.cpu.itb.fetch_hits 317139351 # ITB hits system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 317138881 # ITB accesses +system.cpu.itb.fetch_accesses 317139471 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -318,67 +318,67 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1119923029 # number of cpu cycles simulated +system.cpu.numCycles 1123925982 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 27043480 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 27043469 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.205788 # CPI: cycles per instruction -system.cpu.ipc 0.829333 # IPC: instructions per cycle -system.cpu.tickCycles 1060170406 # Number of cycles that the object actually ticked -system.cpu.idleCycles 59752623 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.210098 # CPI: cycles per instruction +system.cpu.ipc 0.826379 # IPC: instructions per cycle +system.cpu.tickCycles 1060172068 # Number of cycles that the object actually ticked +system.cpu.idleCycles 63753914 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 776532 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.890165 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 323503178 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.699416 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 323503203 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 414.414008 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 845912250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.890165 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999241 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999241 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 414.414040 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 905250250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.699416 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999194 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999194 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 949 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1244 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1640 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 952 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1237 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1647 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 649485148 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 649485148 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 225339131 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 225339131 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164047 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 323503178 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 323503178 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 323503178 # number of overall hits -system.cpu.dcache.overall_hits::total 323503178 # number of overall hits +system.cpu.dcache.tags.tag_accesses 649485188 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 649485188 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 225339151 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 225339151 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98164052 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164052 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 323503203 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 323503203 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 323503203 # number of overall hits +system.cpu.dcache.overall_hits::total 323503203 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137153 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 849082 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 849082 # number of overall misses -system.cpu.dcache.overall_misses::total 849082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 23417135750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23417135750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9028767000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9028767000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32445902750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32445902750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32445902750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32445902750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 226051060 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 226051060 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 137148 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137148 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 849077 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 849077 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 849077 # number of overall misses +system.cpu.dcache.overall_misses::total 849077 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24941013500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24941013500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10047073750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10047073750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34988087250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34988087250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34988087250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34988087250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 226051080 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 226051080 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 324352260 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 324352260 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 324352260 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 324352260 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 324352280 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 324352280 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 324352280 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 324352280 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003149 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003149 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses @@ -387,14 +387,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002618 system.cpu.dcache.demand_miss_rate::total 0.002618 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002618 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002618 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32892.515616 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32892.515616 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65829.890706 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65829.890706 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38212.920248 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38212.920248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38212.920248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38212.920248 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35033.006803 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35033.006803 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73257.165617 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73257.165617 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41207.201761 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41207.201761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41207.201761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41207.201761 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -407,12 +407,12 @@ system.cpu.dcache.writebacks::writebacks 91489 # nu system.cpu.dcache.writebacks::total 91489 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 312 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68142 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68142 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68454 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68454 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68454 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68454 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68137 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68137 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 68449 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68449 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 68449 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68449 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711617 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711617 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses @@ -421,14 +421,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780628 system.cpu.dcache.demand_mshr_misses::total 780628 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780628 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780628 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21915650000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21915650000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4445743250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4445743250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26361393250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26361393250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26361393250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26361393250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23795842750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23795842750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4974141500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4974141500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28769984250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28769984250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28769984250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28769984250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003148 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003148 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -437,69 +437,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002407 system.cpu.dcache.demand_mshr_miss_rate::total 0.002407 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002407 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002407 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30796.973653 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30796.973653 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64420.791613 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64420.791613 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33769.469261 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33769.469261 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33439.115072 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33439.115072 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72077.516628 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72077.516628 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36854.922255 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36854.922255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36854.922255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36854.922255 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 10606 # number of replacements -system.cpu.icache.tags.tagsinuse 1687.447497 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 317126411 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12349 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25680.331282 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 10603 # number of replacements +system.cpu.icache.tags.tagsinuse 1687.326033 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 317127004 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12346 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25686.619472 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1687.447497 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.823949 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.823949 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1687.326033 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.823890 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.823890 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1743 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1575 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.851074 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 634289871 # Number of tag accesses -system.cpu.icache.tags.data_accesses 634289871 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 317126411 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 317126411 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 317126411 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 317126411 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 317126411 # number of overall hits -system.cpu.icache.overall_hits::total 317126411 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12350 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12350 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12350 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12350 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12350 # number of overall misses -system.cpu.icache.overall_misses::total 12350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 333924000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 333924000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 333924000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 333924000 # 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average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28743.196728 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28743.196728 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28743.196728 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28743.196728 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28743.196728 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -508,66 +508,66 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 792975 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.236495 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311902 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.310615 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.310616 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.236437 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.236495 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.369702 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.367627 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.236437 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.367628 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.236495 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.369702 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.367627 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68944.863014 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73471.647406 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73412.867148 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65316.891740 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65316.891740 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68944.863014 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71588.509182 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71562.029192 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68944.863014 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71588.509182 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71562.029192 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.367628 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76632.277397 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80839.635286 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80785.002779 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73227.706505 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73227.706505 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76632.277397 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79081.849446 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79057.313392 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76632.277397 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79081.849446 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79057.313392 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -646,68 +646,68 @@ system.cpu.l2cache.demand_mshr_misses::total 291520 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2920 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 288600 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 291520 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164600500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13505684500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13670285000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3519774750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3519774750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164600500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17025459250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17190059750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164600500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17025459250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17190059750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187160250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15168425250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15355585500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4046889000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4046889000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187160250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19215314250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19402474500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187160250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19215314250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19402474500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311902 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310615 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310616 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.367627 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.367628 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.367627 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56370.034247 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60848.750873 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60790.594775 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52813.785730 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52813.785730 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56370.034247 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58993.275295 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56370.034247 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58993.275295 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.367628 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64095.976027 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68340.092586 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68284.982768 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60723.069998 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60723.069998 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64095.976027 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66581.130457 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66556.237994 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64095.976027 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66581.130457 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66556.237994 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 723967 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 723966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 723964 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723963 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24699 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24693 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652745 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1677444 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1677438 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790144 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56605824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56605632 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 884467 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 884464 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 884467 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 884464 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 884467 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 533722500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 884464 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 533721000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 19152500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 19157750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1222191750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1221759250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.trans_dist::ReadReq 224874 # Transaction distribution system.membus.trans_dist::ReadResp 224874 # Transaction distribution @@ -729,9 +729,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 358202 # Request fanout histogram -system.membus.reqLayer0.occupancy 975503000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2745267250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.reqLayer0.occupancy 667013500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1552224500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 8cb1b2d37..492f134ce 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.278180 # Number of seconds simulated -sim_ticks 278180234500 # Number of ticks simulated -final_tick 278180234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.279669 # Number of seconds simulated +sim_ticks 279668927000 # Number of ticks simulated +final_tick 279668927000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185742 # Simulator instruction rate (inst/s) -host_op_rate 185742 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61337566 # Simulator tick rate (ticks/s) -host_mem_usage 305284 # Number of bytes of host memory used -host_seconds 4535.23 # Real time elapsed on the host +host_inst_rate 180963 # Simulator instruction rate (inst/s) +host_op_rate 180963 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60079385 # Simulator tick rate (ticks/s) +host_mem_usage 306712 # Number of bytes of host memory used +host_seconds 4654.99 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 175680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18477184 # Number of bytes read from this memory -system.physmem.bytes_read::total 18652864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 175680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 175680 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18476288 # Number of bytes read from this memory +system.physmem.bytes_read::total 18652544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176256 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288706 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291451 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2754 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288692 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291446 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 631533 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 66421628 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 67053161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 631533 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 631533 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15341536 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15341536 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15341536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 631533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 66421628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 82394697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291451 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 630231 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 66064858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 66695089 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 630231 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 630231 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15259872 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15259872 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15259872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 630231 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 66064858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 81954961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291446 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 291451 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291446 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18633536 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18652864 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18633664 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue +system.physmem.bytesWritten 4265984 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18652544 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17916 # Per bank write bursts -system.physmem.perBankRdBursts::1 18271 # Per bank write bursts +system.physmem.perBankRdBursts::0 17911 # Per bank write bursts +system.physmem.perBankRdBursts::1 18258 # Per bank write bursts system.physmem.perBankRdBursts::2 18306 # Per bank write bursts -system.physmem.perBankRdBursts::3 18248 # Per bank write bursts -system.physmem.perBankRdBursts::4 18157 # Per bank write bursts -system.physmem.perBankRdBursts::5 18220 # Per bank write bursts -system.physmem.perBankRdBursts::6 18319 # Per bank write bursts -system.physmem.perBankRdBursts::7 18312 # Per bank write bursts -system.physmem.perBankRdBursts::8 18226 # Per bank write bursts -system.physmem.perBankRdBursts::9 18223 # Per bank write bursts -system.physmem.perBankRdBursts::10 18210 # Per bank write bursts -system.physmem.perBankRdBursts::11 18385 # Per bank write bursts -system.physmem.perBankRdBursts::12 18240 # Per bank write bursts -system.physmem.perBankRdBursts::13 18040 # Per bank write bursts -system.physmem.perBankRdBursts::14 17965 # Per bank write bursts -system.physmem.perBankRdBursts::15 18111 # Per bank write bursts +system.physmem.perBankRdBursts::3 18250 # Per bank write bursts +system.physmem.perBankRdBursts::4 18158 # Per bank write bursts +system.physmem.perBankRdBursts::5 18224 # Per bank write bursts +system.physmem.perBankRdBursts::6 18321 # Per bank write bursts +system.physmem.perBankRdBursts::7 18307 # Per bank write bursts +system.physmem.perBankRdBursts::8 18228 # Per bank write bursts +system.physmem.perBankRdBursts::9 18222 # Per bank write bursts +system.physmem.perBankRdBursts::10 18213 # Per bank write bursts +system.physmem.perBankRdBursts::11 18393 # Per bank write bursts +system.physmem.perBankRdBursts::12 18247 # Per bank write bursts +system.physmem.perBankRdBursts::13 18043 # Per bank write bursts +system.physmem.perBankRdBursts::14 17966 # Per bank write bursts +system.physmem.perBankRdBursts::15 18104 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4187 # Per bank write bursts +system.physmem.perBankWrBursts::9 4180 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 278180151500 # Total gap between requests +system.physmem.totGap 279668837500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291451 # Read request sizes (log2) +system.physmem.readPktSize::6 291446 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,13 +97,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 211637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 46647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 32683 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 215531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47086 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,118 +193,117 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 100542 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 227.760100 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.180809 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 278.034024 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 36066 35.87% 35.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 42234 42.01% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10234 10.18% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 483 0.48% 88.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 471 0.47% 89.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 384 0.38% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 767 0.76% 90.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1163 1.16% 91.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8740 8.69% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 100542 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4045 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.840049 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.159268 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 778.757650 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4038 99.83% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 100388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 228.091007 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.320458 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 278.791024 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 35777 35.64% 35.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42525 42.36% 78.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10061 10.02% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 470 0.47% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 508 0.51% 89.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 391 0.39% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 492 0.49% 89.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1510 1.50% 91.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8654 8.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 100388 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 69.235658 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.129419 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 756.508896 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4037 99.83% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-8191 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 5 0.12% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4045 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4045 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.480346 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.459004 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.856073 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3075 76.02% 76.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 0.02% 76.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 965 23.86% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4 0.10% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4045 # Writes before turning the bus around for reads -system.physmem.totQLat 3369536750 # Total ticks spent queuing -system.physmem.totMemAccLat 8828580500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1455745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11573.24 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.482690 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.461191 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.859365 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3072 75.96% 75.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 964 23.84% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 8 0.20% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads +system.physmem.totQLat 3601508250 # Total ticks spent queuing +system.physmem.totMemAccLat 9060589500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1455755000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12369.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30323.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 66.98 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 15.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 67.05 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 15.34 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31119.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 66.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 15.25 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 66.70 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 15.26 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.64 # Data bus utilization in percentage system.physmem.busUtilRead 0.52 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing -system.physmem.readRowHits 206912 # Number of row buffer hits during reads -system.physmem.writeRowHits 50353 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.51 # Row buffer hit rate for writes -system.physmem.avgGap 776748.79 # Average gap between requests -system.physmem.pageHitRate 71.90 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 378604800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 206580000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1136756400 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing +system.physmem.readRowHits 206952 # Number of row buffer hits during reads +system.physmem.writeRowHits 50458 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.67 # Row buffer hit rate for writes +system.physmem.avgGap 780916.48 # Average gap between requests +system.physmem.pageHitRate 71.94 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 378650160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 206604750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136467800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 18169323120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 79832621385 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 96879153000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 196819477185 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.526603 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 160651755000 # Time in different power states -system.physmem_0.memoryStateTime::REF 9289020000 # Time in different power states +system.physmem_0.refreshEnergy 18266458080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 79892908290 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 97718574000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 197816101560 # Total energy per rank (pJ) +system.physmem_0.averagePower 707.327829 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 162042939000 # Time in different power states +system.physmem_0.memoryStateTime::REF 9338680000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 108238852500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 108285182250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 381470040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 208143375 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 380207520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 207454500 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1134088800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215537760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 18169323120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79968075615 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 96760333500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 196836972210 # Total energy per rank (pJ) -system.physmem_1.averagePower 707.589494 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 160452636750 # Time in different power states -system.physmem_1.memoryStateTime::REF 9289020000 # Time in different power states +system.physmem_1.writeEnergy 215492400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 18266458080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80233432560 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 97419868500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 197857002360 # Total energy per rank (pJ) +system.physmem_1.averagePower 707.474077 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 161543146250 # Time in different power states +system.physmem_1.memoryStateTime::REF 9338680000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 108437970750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 108784975000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 192516083 # Number of BP lookups -system.cpu.branchPred.condPredicted 125602202 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11889251 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 155393318 # Number of BTB lookups -system.cpu.branchPred.BTBHits 126938973 # Number of BTB hits +system.cpu.branchPred.lookups 192995150 # Number of BP lookups +system.cpu.branchPred.condPredicted 125739221 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11883936 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 145375032 # Number of BTB lookups +system.cpu.branchPred.BTBHits 127081867 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.688823 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 28938957 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 146 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.416570 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 29018342 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 151 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 244535558 # DTB read hits -system.cpu.dtb.read_misses 309848 # DTB read misses +system.cpu.dtb.read_hits 244533779 # DTB read hits +system.cpu.dtb.read_misses 309591 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 244845406 # DTB read accesses -system.cpu.dtb.write_hits 135688740 # DTB write hits -system.cpu.dtb.write_misses 31438 # DTB write misses +system.cpu.dtb.read_accesses 244843370 # DTB read accesses +system.cpu.dtb.write_hits 135671849 # DTB write hits +system.cpu.dtb.write_misses 31346 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 135720178 # DTB write accesses -system.cpu.dtb.data_hits 380224298 # DTB hits -system.cpu.dtb.data_misses 341286 # DTB misses +system.cpu.dtb.write_accesses 135703195 # DTB write accesses +system.cpu.dtb.data_hits 380205628 # DTB hits +system.cpu.dtb.data_misses 340937 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 380565584 # DTB accesses -system.cpu.itb.fetch_hits 196974389 # ITB hits -system.cpu.itb.fetch_misses 282 # ITB misses +system.cpu.dtb.data_accesses 380546565 # DTB accesses +system.cpu.itb.fetch_hits 197011138 # ITB hits +system.cpu.itb.fetch_misses 297 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 196974671 # ITB accesses +system.cpu.itb.fetch_accesses 197011435 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -318,138 +317,137 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 556360470 # number of cpu cycles simulated +system.cpu.numCycles 559337855 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 202471372 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648161036 # Number of instructions fetch has processed -system.cpu.fetch.Branches 192516083 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 155877930 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 341537101 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 24247434 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 71 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 163 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6713 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 196974389 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6735628 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 556139161 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.963577 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.176192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 202154435 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1649182914 # Number of instructions fetch has processed +system.cpu.fetch.Branches 192995150 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 156100209 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 344813807 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 24235896 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6519 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 197011138 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 7083229 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 559092875 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.949748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.175515 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 236974879 42.61% 42.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30241040 5.44% 48.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22122460 3.98% 52.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 36446378 6.55% 58.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 67887841 12.21% 70.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 21615986 3.89% 74.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 19300231 3.47% 78.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3499506 0.63% 78.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 118050840 21.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 239653225 42.86% 42.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30449692 5.45% 48.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22058642 3.95% 52.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36467190 6.52% 58.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 68017058 12.17% 70.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 21431579 3.83% 74.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 19299153 3.45% 78.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3537365 0.63% 78.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 118178971 21.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 556139161 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.346028 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.962398 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 168673381 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 88906441 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 273702922 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 12739464 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 12116953 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 15366288 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 7026 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1584564231 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 25244 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 12116953 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 176662049 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61884123 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13864 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 278433046 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27029126 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1538057639 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6904 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2373775 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 17934465 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 6832008 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1026949046 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1768413823 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1728631636 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 39782186 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 559092875 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.345042 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.948456 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 168803167 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 91739479 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 273671215 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12767829 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 12111185 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 15522167 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 6976 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1584668893 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25197 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 12111185 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176688622 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61751221 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14050 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 278532777 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 29995020 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1538585292 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9438 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2658750 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 20386888 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7267964 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1027382191 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1769248125 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1729530138 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39717986 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 387981888 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 388415033 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 1375 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 99 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9559876 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 372392006 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 175420299 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40717360 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11158065 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1304772774 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1015651643 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 8789932 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 462366805 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 427709940 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 556139161 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.826254 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.901646 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 100 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9495582 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 372551032 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 175434243 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40723012 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11258595 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1304972518 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 89 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1016009395 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 8790765 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 462565445 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 427723515 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 52 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 559092875 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.817246 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.904787 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 196811929 35.39% 35.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 93156725 16.75% 52.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 91633615 16.48% 68.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 59891442 10.77% 79.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 56837976 10.22% 89.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29662833 5.33% 94.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 17038989 3.06% 98.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 7191857 1.29% 99.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3913795 0.70% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 200119998 35.79% 35.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 93029621 16.64% 52.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 91384631 16.35% 68.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 59843024 10.70% 79.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 56522593 10.11% 89.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29852885 5.34% 94.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 17077557 3.05% 97.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7239227 1.29% 99.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4023339 0.72% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 556139161 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 559092875 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2464081 10.47% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15568992 66.16% 76.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5500305 23.37% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2463450 10.43% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15566876 65.90% 76.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5592414 23.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 579437623 57.05% 57.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7930 0.00% 57.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13181925 1.30% 58.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826542 0.38% 58.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339802 0.33% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 579702610 57.06% 57.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7931 0.00% 57.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13180646 1.30% 58.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826544 0.38% 58.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339801 0.33% 59.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.06% # Type of FU issued @@ -473,84 +471,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.06% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 276912765 27.26% 86.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 138943776 13.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 277022873 27.27% 86.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138927710 13.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1015651643 # Type of FU issued -system.cpu.iq.rate 1.825528 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23533378 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023171 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2548957351 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1725871307 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 940019268 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 70808406 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 41313833 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34425264 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1002821720 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 36362025 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 50456367 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1016009395 # Type of FU issued +system.cpu.iq.rate 1.816450 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23622740 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023251 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2552720615 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1726495098 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 940123896 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 70804555 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 41088088 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34423394 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1003270759 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 36360100 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 50476055 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 134881409 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1145791 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 45978 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 77119099 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 135040435 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1174528 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 45615 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77133043 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2647 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4470 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2509 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4123 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 12116953 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 60932529 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 189663 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1479247252 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16168 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 372392006 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 175420299 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 26629 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 174749 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 45978 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 11882583 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 16645 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11899228 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 976172370 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 244845576 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 39479273 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 12111185 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 60760024 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 216464 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1479434002 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 17901 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 372551032 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 175434243 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 87 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 21559 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 205996 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 45615 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11877701 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 16644 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11894345 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 976302878 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 244843546 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 39706517 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 174474397 # number of nop insts executed -system.cpu.iew.exec_refs 380566182 # number of memory reference insts executed -system.cpu.iew.exec_branches 129102826 # Number of branches executed -system.cpu.iew.exec_stores 135720606 # Number of stores executed -system.cpu.iew.exec_rate 1.754568 # Inst execution rate -system.cpu.iew.wb_sent 974964146 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 974444532 # cumulative count of insts written-back -system.cpu.iew.wb_producers 556292557 # num instructions producing a value -system.cpu.iew.wb_consumers 832443785 # num instructions consuming a value +system.cpu.iew.exec_nop 174461395 # number of nop insts executed +system.cpu.iew.exec_refs 380547191 # number of memory reference insts executed +system.cpu.iew.exec_branches 129259483 # Number of branches executed +system.cpu.iew.exec_stores 135703645 # Number of stores executed +system.cpu.iew.exec_rate 1.745462 # Inst execution rate +system.cpu.iew.wb_sent 975066188 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 974547290 # cumulative count of insts written-back +system.cpu.iew.wb_producers 556173359 # num instructions producing a value +system.cpu.iew.wb_consumers 831980820 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.751463 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.668264 # average fanout of values written-back +system.cpu.iew.wb_rate 1.742323 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.668493 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 543416365 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 543601549 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 11882488 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 483294798 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.921369 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.600805 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 11877174 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 486379014 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.909185 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.596644 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 205311965 42.48% 42.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102147195 21.14% 63.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51748026 10.71% 74.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 25735966 5.33% 79.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 21537447 4.46% 84.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 9139527 1.89% 86.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10425967 2.16% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6656382 1.38% 89.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 50592323 10.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 208258289 42.82% 42.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102386957 21.05% 63.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51676822 10.62% 74.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25636051 5.27% 79.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 21554637 4.43% 84.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 9250657 1.90% 86.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10396507 2.14% 88.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6664753 1.37% 89.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 50554341 10.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 483294798 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 486379014 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -596,330 +594,346 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 50592323 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 50554341 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1902085330 # The number of ROB reads -system.cpu.rob.rob_writes 3016853590 # The number of ROB writes -system.cpu.timesIdled 3284 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 221309 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1905392712 # The number of ROB reads +system.cpu.rob.rob_writes 3017093514 # The number of ROB writes +system.cpu.timesIdled 3164 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 244980 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.660461 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.660461 # CPI: Total CPI of All Threads -system.cpu.ipc 1.514094 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.514094 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1237238749 # number of integer regfile reads -system.cpu.int_regfile_writes 705818584 # number of integer regfile writes -system.cpu.fp_regfile_reads 36691517 # number of floating regfile reads -system.cpu.fp_regfile_writes 24411333 # number of floating regfile writes +system.cpu.cpi 0.663995 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.663995 # CPI: Total CPI of All Threads +system.cpu.ipc 1.506034 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.506034 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1237178642 # number of integer regfile reads +system.cpu.int_regfile_writes 705781417 # number of integer regfile writes +system.cpu.fp_regfile_reads 36689419 # number of floating regfile reads +system.cpu.fp_regfile_writes 24410667 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 777239 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.040110 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 289873961 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 781335 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 370.998305 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 354310000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.040110 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 777209 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.895157 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 289903947 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 781305 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 371.050930 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 374093250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.895157 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999242 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999242 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 964 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2501 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 244 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2495 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 253 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 585528663 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 585528663 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 192492893 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 192492893 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97381046 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97381046 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 289873939 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 289873939 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 289873939 # number of overall hits -system.cpu.dcache.overall_hits::total 289873939 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1579549 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1579549 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 920154 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 920154 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2499703 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2499703 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2499703 # number of overall misses -system.cpu.dcache.overall_misses::total 2499703 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79817656500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79817656500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57409075211 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57409075211 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137226731711 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137226731711 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137226731711 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137226731711 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 194072442 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 194072442 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 585486411 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 585486411 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 192496951 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 192496951 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97406971 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97406971 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 25 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 25 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 289903922 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 289903922 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 289903922 # number of overall hits +system.cpu.dcache.overall_hits::total 289903922 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1554376 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1554376 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 894229 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 894229 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2448605 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2448605 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2448605 # number of overall misses +system.cpu.dcache.overall_misses::total 2448605 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 84529453750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 84529453750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 62304618080 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62304618080 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 100250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 100250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 146834071830 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 146834071830 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 146834071830 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 146834071830 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 194051327 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 194051327 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 292373642 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 292373642 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 292373642 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 292373642 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008139 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008139 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009361 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009361 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008550 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008550 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008550 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008550 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50531.928101 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50531.928101 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62390.725043 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62390.725043 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54897.214473 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54897.214473 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54897.214473 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54897.214473 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21908 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 55699 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 467 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 516 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.912206 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 107.943798 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 26 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 26 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 292352527 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 292352527 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 292352527 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 292352527 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008010 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008010 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009097 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009097 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038462 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038462 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008376 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008376 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008376 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008376 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54381.599915 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54381.599915 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69674.119359 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69674.119359 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 100250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 100250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59966.418361 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59966.418361 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59966.418361 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59966.418361 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21964 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 69527 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 343 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 515 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 64.034985 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 135.003883 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91488 # number of writebacks -system.cpu.dcache.writebacks::total 91488 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867045 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 867045 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 851323 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 851323 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1718368 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1718368 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1718368 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1718368 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712504 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712504 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68831 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68831 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 781335 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 781335 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 781335 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 781335 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21874292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21874292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5221022246 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5221022246 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27095314246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27095314246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27095314246 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27095314246 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003671 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003671 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 91524 # number of writebacks +system.cpu.dcache.writebacks::total 91524 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 841911 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 841911 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 825390 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 825390 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1667301 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1667301 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1667301 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1667301 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712465 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712465 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68839 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68839 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 781304 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 781304 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 781304 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 781304 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23794966500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23794966500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5675142998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5675142998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 98250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 98250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29470109498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29470109498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29470109498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29470109498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003672 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003672 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.038462 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.038462 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002672 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30700.588348 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30700.588348 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75852.773402 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75852.773402 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34678.229244 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34678.229244 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34678.229244 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34678.229244 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33398.084818 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33398.084818 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82440.811139 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82440.811139 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 98250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 98250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37719.133011 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37719.133011 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37719.133011 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37719.133011 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 4662 # number of replacements -system.cpu.icache.tags.tagsinuse 1655.102487 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 196966072 # Total number of references to valid blocks. +system.cpu.icache.tags.replacements 4665 # number of replacements +system.cpu.icache.tags.tagsinuse 1651.262169 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 197002801 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6374 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 30901.486037 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 30907.248353 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1655.102487 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.808156 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.808156 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1712 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1651.262169 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.806280 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.806280 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1709 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1560 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.835938 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 393955150 # Number of tag accesses -system.cpu.icache.tags.data_accesses 393955150 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 196966072 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 196966072 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 196966072 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 196966072 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 196966072 # number of overall hits -system.cpu.icache.overall_hits::total 196966072 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8316 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8316 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8316 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8316 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8316 # number of overall misses -system.cpu.icache.overall_misses::total 8316 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 334444749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 334444749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 334444749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 334444749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 334444749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 334444749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 196974388 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 196974388 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 196974388 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 196974388 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 196974388 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 196974388 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 1547 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.834473 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 394028650 # Number of tag accesses +system.cpu.icache.tags.data_accesses 394028650 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 197002801 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 197002801 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 197002801 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 197002801 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 197002801 # number of overall hits +system.cpu.icache.overall_hits::total 197002801 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8337 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8337 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8337 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8337 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8337 # number of overall misses +system.cpu.icache.overall_misses::total 8337 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 359956749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 359956749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 359956749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 359956749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 359956749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 359956749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 197011138 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 197011138 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 197011138 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 197011138 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 197011138 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 197011138 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40217.021284 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 40217.021284 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 40217.021284 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 40217.021284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 40217.021284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 40217.021284 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 710 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43175.812522 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43175.812522 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43175.812522 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43175.812522 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43175.812522 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43175.812522 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 938 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 64.545455 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62.533333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1941 # 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number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -930,103 +944,103 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2746 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222082 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 224828 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66624 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66624 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2746 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288706 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291452 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2746 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288706 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291452 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 165368000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13488499500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13653867500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4314074750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4314074750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 165368000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17802574250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17967942250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 165368000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17802574250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17967942250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.430745 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311692 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312748 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.967936 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.967936 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.430745 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369503 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.369999 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.430745 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369503 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.369999 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60221.412964 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60736.572527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60730.280481 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64752.562890 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64752.562890 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60221.412964 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61663.333114 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61649.747643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60221.412964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61663.333114 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61649.747643 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2755 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222064 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 224819 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66628 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66628 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288692 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291447 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2755 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288692 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291447 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 185539750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15158114250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15343654000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4753161750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4753161750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 185539750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19911276000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20096815750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 185539750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19911276000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20096815750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.432157 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311684 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312752 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.967882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.967882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.432157 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369500 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.370007 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.432157 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369500 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.370007 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67346.551724 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68260.115327 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68248.920243 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71338.802756 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71338.802756 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67346.551724 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68970.653846 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68955.301478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67346.551724 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68970.653846 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68955.301478 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 718879 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 718878 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91488 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68831 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68831 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 718841 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 718840 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91524 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68839 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68839 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12749 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654158 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1666907 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654134 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1666883 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 407936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55860672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56268608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55861056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56268992 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 879198 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 879204 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 879198 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 879204 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 879198 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 531087000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 879204 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 531126000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10054750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10103500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1207495250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1213595000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224827 # Transaction distribution -system.membus.trans_dist::ReadResp 224827 # Transaction distribution +system.membus.trans_dist::ReadReq 224818 # Transaction distribution +system.membus.trans_dist::ReadResp 224818 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::ReadExReq 66624 # Transaction distribution -system.membus.trans_dist::ReadExResp 66624 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649585 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649585 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22920576 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 66628 # Transaction distribution +system.membus.trans_dist::ReadExResp 66628 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649575 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649575 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22920256 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 358134 # Request fanout histogram +system.membus.snoop_fanout::samples 358129 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 358134 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 358129 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 358134 # Request fanout histogram -system.membus.reqLayer0.occupancy 959207000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2708819750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.snoop_fanout::total 358129 # Request fanout histogram +system.membus.reqLayer0.occupancy 682357500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1548216750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 8acd26381..eff48cf7e 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.286250 # Number of seconds simulated -sim_ticks 1286249820000 # Number of ticks simulated -final_tick 1286249820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1286249817500 # Number of ticks simulated +final_tick 1286249817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1681245 # Simulator instruction rate (inst/s) -host_op_rate 1681245 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2328806930 # Simulator tick rate (ticks/s) -host_mem_usage 298588 # Number of bytes of host memory used -host_seconds 552.32 # Real time elapsed on the host +host_inst_rate 1412500 # Simulator instruction rate (inst/s) +host_op_rate 1412500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1956550284 # Simulator tick rate (ticks/s) +host_mem_usage 303116 # Number of bytes of host memory used +host_seconds 657.41 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,30 +36,6 @@ system.physmem.bw_total::writebacks 3317950 # To system.physmem.bw_total::cpu.inst 107127 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 14356203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 17781280 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 224031 # Transaction distribution -system.membus.trans_dist::ReadResp 224031 # Transaction distribution -system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::ReadExReq 66648 # Transaction distribution -system.membus.trans_dist::ReadExResp 66648 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 357362 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 357362 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 357362 # Request fanout histogram -system.membus.reqLayer0.occupancy 890826000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2616111000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -94,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 2572499640 # number of cpu cycles simulated +system.cpu.numCycles 2572499635 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928587629 # Number of instructions committed @@ -113,7 +89,7 @@ system.cpu.num_mem_refs 336013318 # nu system.cpu.num_load_insts 237705247 # Number of load instructions system.cpu.num_store_insts 98308071 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2572499640 # Number of busy cycles +system.cpu.num_busy_cycles 2572499635 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 123111018 # Number of branches fetched @@ -152,13 +128,122 @@ system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction +system.cpu.dcache.tags.replacements 776432 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.261321 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1046537000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261321 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 993 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits +system.cpu.dcache.overall_hits::total 335031269 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses +system.cpu.dcache.overall_misses::total 780528 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18568558000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18568558000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696398000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3696398000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22264956000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22264956000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22264956000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22264956000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.248965 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.248965 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.505811 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28525.505811 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.505811 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28525.505811 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 91660 # number of writebacks +system.cpu.dcache.writebacks::total 91660 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17501287000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17501287000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3592877000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3592877000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21094164000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21094164000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21094164000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21094164000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24597.248965 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24597.248965 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52060.118237 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52060.118237 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27025.505811 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27025.505811 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27025.505811 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27025.505811 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 4618 # number of replacements -system.cpu.icache.tags.tagsinuse 1474.486239 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1474.486238 # Cycle average of tags in use system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486239 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486238 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.719964 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.719964 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id @@ -181,12 +266,12 @@ system.cpu.icache.demand_misses::cpu.inst 6168 # n system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses system.cpu.icache.overall_misses::total 6168 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 170610000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 170610000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 170610000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 170610000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 170610000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 170610000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 170610500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 170610500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 170610500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 170610500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 170610500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 170610500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses @@ -199,12 +284,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.505837 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27660.505837 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27660.505837 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27660.505837 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.586900 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27660.586900 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.586900 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27660.586900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.586900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27660.586900 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -219,34 +304,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 6168 system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 158274000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 158274000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 158274000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 158274000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 158274000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 158274000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 161358500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 161358500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 161358500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 161358500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 161358500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 161358500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25660.505837 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25660.505837 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25660.505837 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 25660.505837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25660.505837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 25660.505837 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26160.586900 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26160.586900 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26160.586900 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26160.586900 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26160.586900 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26160.586900 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 257900 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32657.894031 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32657.894008 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 518578 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 290634 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.784299 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2768.249737 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2768.249705 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.156527 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.487767 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.487776 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.084480 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001531 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.910629 # Average percentage of cache occupancy @@ -284,17 +369,17 @@ system.cpu.l2cache.demand_misses::total 290679 # nu system.cpu.l2cache.overall_misses::cpu.inst 2153 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 288526 # number of overall misses system.cpu.l2cache.overall_misses::total 290679 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 111956000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11537659000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11649615000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3465696000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3465696000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 111956000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15003355000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15115311000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 111956000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15003355000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15115311000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 113033000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11648595000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11761628000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3499020000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3499020000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 113033000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15147615000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15260648000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 113033000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15147615000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15260648000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6168 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 711514 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 717682 # number of ReadReq accesses(hits+misses) @@ -319,17 +404,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.369493 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.349060 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.369655 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.369493 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.013521 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.013391 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010398 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.010321 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010398 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.010321 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.232234 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.002232 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.232234 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.001720 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.232234 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.001720 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,17 +436,17 @@ system.cpu.l2cache.demand_mshr_misses::total 290679 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2153 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 288526 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 290679 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 86120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8875123000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8961243000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2665920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2665920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 86120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11541043000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11627163000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 86120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11541043000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11627163000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 87196500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8986059000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9073255500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2699244000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2699244000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87196500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11685303000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11772499500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87196500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11685303000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11772499500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311839 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312159 # mshr miss rate for ReadReq accesses @@ -373,127 +458,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.369493 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369655 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.369493 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.013521 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.013391 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.010398 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.010321 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.010398 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.010321 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 776432 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.261324 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1046536000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261324 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 993 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits -system.cpu.dcache.overall_hits::total 335031269 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses -system.cpu.dcache.overall_misses::total 780528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18568561000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18568561000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696398000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3696398000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22264959000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22264959000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22264959000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22264959000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.253181 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.253181 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28525.509655 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28525.509655 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91660 # number of writebacks -system.cpu.dcache.writebacks::total 91660 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17145533000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17145533000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3558370000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3558370000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20703903000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20703903000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20703903000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20703903000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24097.253181 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24097.253181 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51560.118237 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51560.118237 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91660 # Transaction distribution @@ -523,5 +499,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 9252000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 224031 # Transaction distribution +system.membus.trans_dist::ReadResp 224031 # Transaction distribution +system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::ReadExReq 66648 # Transaction distribution +system.membus.trans_dist::ReadExResp 66648 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 357362 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 357362 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 357362 # Request fanout histogram +system.membus.reqLayer0.occupancy 636219000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 1453395500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 7a6d5db32..3406c4e55 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.541786 # Number of seconds simulated -sim_ticks 541786101000 # Number of ticks simulated -final_tick 541786101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.545057 # Number of seconds simulated +sim_ticks 545056655500 # Number of ticks simulated +final_tick 545056655500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115987 # Simulator instruction rate (inst/s) -host_op_rate 142796 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 98087491 # Simulator tick rate (ticks/s) -host_mem_usage 309428 # Number of bytes of host memory used -host_seconds 5523.50 # Real time elapsed on the host +host_inst_rate 182072 # Simulator instruction rate (inst/s) +host_op_rate 224154 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 154902851 # Simulator tick rate (ticks/s) +host_mem_usage 321108 # Number of bytes of host memory used +host_seconds 3518.70 # Real time elapsed on the host sim_insts 640655084 # Number of instructions simulated sim_ops 788730743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 164672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18429184 # Number of bytes read from this memory -system.physmem.bytes_read::total 18593856 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 164864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18429248 # Number of bytes read from this memory +system.physmem.bytes_read::total 18594112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 164864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 164864 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2573 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 287956 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2576 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 287957 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290533 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 303943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 34015609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34319552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 303943 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 303943 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7808011 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7808011 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7808011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 303943 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 34015609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42127563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 290529 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 302471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33811619 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34114090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 302471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 302471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7761160 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7761160 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7761160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 302471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33811619 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41875251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 290533 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 290529 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 290533 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18572736 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21120 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18593856 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18574784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18594112 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 330 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18289 # Per bank write bursts -system.physmem.perBankRdBursts::1 18137 # Per bank write bursts -system.physmem.perBankRdBursts::2 18222 # Per bank write bursts +system.physmem.perBankRdBursts::0 18287 # Per bank write bursts +system.physmem.perBankRdBursts::1 18141 # Per bank write bursts +system.physmem.perBankRdBursts::2 18224 # Per bank write bursts system.physmem.perBankRdBursts::3 18184 # Per bank write bursts -system.physmem.perBankRdBursts::4 18266 # Per bank write bursts -system.physmem.perBankRdBursts::5 18308 # Per bank write bursts -system.physmem.perBankRdBursts::6 18094 # Per bank write bursts -system.physmem.perBankRdBursts::7 17914 # Per bank write bursts -system.physmem.perBankRdBursts::8 17939 # Per bank write bursts -system.physmem.perBankRdBursts::9 17962 # Per bank write bursts -system.physmem.perBankRdBursts::10 18018 # Per bank write bursts -system.physmem.perBankRdBursts::11 18110 # Per bank write bursts +system.physmem.perBankRdBursts::4 18267 # Per bank write bursts +system.physmem.perBankRdBursts::5 18318 # Per bank write bursts +system.physmem.perBankRdBursts::6 18100 # Per bank write bursts +system.physmem.perBankRdBursts::7 17916 # Per bank write bursts +system.physmem.perBankRdBursts::8 17940 # Per bank write bursts +system.physmem.perBankRdBursts::9 17966 # Per bank write bursts +system.physmem.perBankRdBursts::10 18025 # Per bank write bursts +system.physmem.perBankRdBursts::11 18111 # Per bank write bursts system.physmem.perBankRdBursts::12 18143 # Per bank write bursts -system.physmem.perBankRdBursts::13 18270 # Per bank write bursts -system.physmem.perBankRdBursts::14 18077 # Per bank write bursts -system.physmem.perBankRdBursts::15 18266 # Per bank write bursts -system.physmem.perBankWrBursts::0 4174 # Per bank write bursts -system.physmem.perBankWrBursts::1 4101 # Per bank write bursts -system.physmem.perBankWrBursts::2 4137 # Per bank write bursts -system.physmem.perBankWrBursts::3 4147 # Per bank write bursts +system.physmem.perBankRdBursts::13 18269 # Per bank write bursts +system.physmem.perBankRdBursts::14 18078 # Per bank write bursts +system.physmem.perBankRdBursts::15 18262 # Per bank write bursts +system.physmem.perBankWrBursts::0 4173 # Per bank write bursts +system.physmem.perBankWrBursts::1 4099 # Per bank write bursts +system.physmem.perBankWrBursts::2 4136 # Per bank write bursts +system.physmem.perBankWrBursts::3 4146 # Per bank write bursts system.physmem.perBankWrBursts::4 4225 # Per bank write bursts -system.physmem.perBankWrBursts::5 4225 # Per bank write bursts +system.physmem.perBankWrBursts::5 4223 # Per bank write bursts system.physmem.perBankWrBursts::6 4171 # Per bank write bursts -system.physmem.perBankWrBursts::7 4096 # Per bank write bursts -system.physmem.perBankWrBursts::8 4093 # Per bank write bursts +system.physmem.perBankWrBursts::7 4094 # Per bank write bursts +system.physmem.perBankWrBursts::8 4094 # Per bank write bursts system.physmem.perBankWrBursts::9 4093 # Per bank write bursts -system.physmem.perBankWrBursts::10 4090 # Per bank write bursts -system.physmem.perBankWrBursts::11 4094 # Per bank write bursts -system.physmem.perBankWrBursts::12 4096 # Per bank write bursts -system.physmem.perBankWrBursts::13 4094 # Per bank write bursts +system.physmem.perBankWrBursts::10 4093 # Per bank write bursts +system.physmem.perBankWrBursts::11 4097 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4138 # Per bank write bursts +system.physmem.perBankWrBursts::15 4140 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 541786012500 # Total gap between requests +system.physmem.totGap 545056561000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 290529 # Read request sizes (log2) +system.physmem.readPktSize::6 290533 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,8 +97,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 289803 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 289840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 375 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4009 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,97 +193,95 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 111554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 204.382452 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.554579 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 255.928936 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47007 42.14% 42.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43571 39.06% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8721 7.82% 89.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 769 0.69% 89.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1361 1.22% 90.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1221 1.09% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 537 0.48% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 497 0.45% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 111554 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4006 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.553919 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.073633 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 507.732262 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4003 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 112305 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 203.035662 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.214062 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 254.437736 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47268 42.09% 42.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43750 38.96% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8988 8.00% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1909 1.70% 90.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 489 0.44% 91.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 737 0.66% 91.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 726 0.65% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 505 0.45% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7933 7.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 112305 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.526066 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.050433 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 507.549530 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4006 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4006 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.492761 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.471115 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.861913 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3018 75.34% 75.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3 0.07% 75.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 984 24.56% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4006 # Writes before turning the bus around for reads -system.physmem.totQLat 2707676000 # Total ticks spent queuing -system.physmem.totMemAccLat 8148907250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1450995000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9330.41 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.481417 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.460113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.855134 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3044 75.93% 75.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 965 24.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads +system.physmem.totQLat 2737356250 # Total ticks spent queuing +system.physmem.totMemAccLat 8179187500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1451155000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9431.65 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28080.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 34.28 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 34.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.81 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28181.65 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 34.08 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.76 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 34.11 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.76 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.42 # Average write queue length when enqueuing -system.physmem.readRowHits 194608 # Number of row buffer hits during reads -system.physmem.writeRowHits 50098 # Number of row buffer hits during writes -system.physmem.readRowHitRate 67.06 # Row buffer hit rate for reads +system.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing +system.physmem.readRowHits 193898 # Number of row buffer hits during reads +system.physmem.writeRowHits 50093 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes -system.physmem.avgGap 1519195.16 # Average gap between requests -system.physmem.pageHitRate 68.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 421810200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 230154375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1134190200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 215628480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 106352983170 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 231777774000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 375519162345 # Total energy per rank (pJ) -system.physmem_0.averagePower 693.117148 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 384873582500 # Time in different power states -system.physmem_0.memoryStateTime::REF 18091320000 # Time in different power states +system.physmem.avgGap 1528348.80 # Average gap between requests +system.physmem.pageHitRate 68.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 424002600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 231350625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1134369600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 215570160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 106884947925 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 233273273250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 377763731280 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.076638 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 387358600750 # Time in different power states +system.physmem_0.memoryStateTime::REF 18200520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 138818819500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 139494961250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 421477560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 229972875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1129034400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212505120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 105425199585 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 232591619250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 375396430710 # Total energy per rank (pJ) -system.physmem_1.averagePower 692.890615 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 386233048000 # Time in different power states -system.physmem_1.memoryStateTime::REF 18091320000 # Time in different power states +system.physmem_1.actEnergy 424962720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 231874500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1129096800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 105917359815 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 234122034750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 377638135065 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.846209 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 388771820250 # Time in different power states +system.physmem_1.memoryStateTime::REF 18200520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 137458753250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 138081006000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 156937341 # Number of BP lookups -system.cpu.branchPred.condPredicted 106680042 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12891228 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 97536058 # Number of BTB lookups -system.cpu.branchPred.BTBHits 81874318 # Number of BTB hits +system.cpu.branchPred.lookups 155213668 # Number of BP lookups +system.cpu.branchPred.condPredicted 105449696 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12879317 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90304208 # Number of BTB lookups +system.cpu.branchPred.BTBHits 82854286 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.942615 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19487919 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1320 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.750194 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19341274 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -402,75 +400,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1083572202 # number of cpu cycles simulated +system.cpu.numCycles 1090113311 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655084 # Number of instructions committed system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 22655429 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 22623250 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.691350 # CPI: cycles per instruction -system.cpu.ipc 0.591244 # IPC: instructions per cycle -system.cpu.tickCycles 1029141566 # Number of cycles that the object actually ticked -system.cpu.idleCycles 54430636 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 778221 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.645412 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378457747 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 782317 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.765209 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 751751250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.645412 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999181 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999181 # Average percentage of cache occupancy +system.cpu.cpi 1.701560 # CPI: cycles per instruction +system.cpu.ipc 0.587696 # IPC: instructions per cycle +system.cpu.tickCycles 1030411592 # Number of cycles that the object actually ticked +system.cpu.idleCycles 59701719 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 778141 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.460106 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378456482 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782237 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.813067 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 802330000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.460106 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999136 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999136 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 962 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1341 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 963 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1339 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1594 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759400731 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759400731 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 249632505 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249632505 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128813764 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128813764 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 759397955 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759397955 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 249631239 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249631239 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378446269 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378446269 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378446269 # number of overall hits -system.cpu.dcache.overall_hits::total 378446269 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 713747 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 713747 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137713 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137713 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 851460 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 851460 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 851460 # number of overall misses -system.cpu.dcache.overall_misses::total 851460 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 23055853217 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23055853217 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9199211000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9199211000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32255064217 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32255064217 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32255064217 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32255064217 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250346252 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250346252 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 378445004 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378445004 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378445004 # number of overall hits +system.cpu.dcache.overall_hits::total 378445004 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 713665 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 713665 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 851377 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 851377 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 851377 # number of overall misses +system.cpu.dcache.overall_misses::total 851377 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24698082718 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24698082718 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10190251750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10190251750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34888334468 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34888334468 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34888334468 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34888334468 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250344904 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250344904 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379297729 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379297729 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379297729 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379297729 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 379296381 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379296381 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379296381 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379296381 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002851 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses @@ -479,14 +477,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32302.557092 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32302.557092 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66799.873650 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66799.873650 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37882.066353 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37882.066353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37882.066353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37882.066353 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34607.389627 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34607.389627 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73996.832157 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73996.832157 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40978.713858 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40978.713858 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40978.713858 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40978.713858 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -497,99 +495,99 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks system.cpu.dcache.writebacks::total 91420 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 752 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 752 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68391 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68391 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 69143 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 69143 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 69143 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 69143 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712995 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712995 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 750 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 750 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 69140 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 69140 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 69140 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 69140 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712915 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712915 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 782317 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782317 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 782317 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 782317 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21545578028 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21545578028 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4531082000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4531082000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26076660028 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26076660028 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26076660028 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26076660028 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 782237 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782237 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782237 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782237 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23543649027 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23543649027 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5045531250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5045531250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28589180277 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28589180277 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28589180277 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28589180277 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30218.413913 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30218.413913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65362.828539 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65362.828539 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33332.600503 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33332.600503 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33024.482620 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33024.482620 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72783.982718 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72783.982718 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36547.977502 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36547.977502 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36547.977502 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36547.977502 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 23590 # number of replacements -system.cpu.icache.tags.tagsinuse 1712.180561 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 289921723 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 25341 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11440.816187 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 23596 # number of replacements +system.cpu.icache.tags.tagsinuse 1712.064969 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 291953853 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11518.280388 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1712.180561 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.836026 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.836026 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1712.064969 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835969 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835969 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1602 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1600 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 579919471 # Number of tag accesses -system.cpu.icache.tags.data_accesses 579919471 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 289921723 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 289921723 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 289921723 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 289921723 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 289921723 # number of overall hits -system.cpu.icache.overall_hits::total 289921723 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 25342 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 25342 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 25342 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 25342 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 25342 # number of overall misses -system.cpu.icache.overall_misses::total 25342 # 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number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 289947065 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 583983749 # Number of tag accesses +system.cpu.icache.tags.data_accesses 583983749 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 291953853 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 291953853 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 291953853 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 291953853 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 291953853 # number of overall hits +system.cpu.icache.overall_hits::total 291953853 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses +system.cpu.icache.overall_misses::total 25348 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 499968245 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 499968245 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 499968245 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 499968245 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 499968245 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 499968245 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 291979201 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 291979201 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 291979201 # 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average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18968.263989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18968.263989 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19724.169362 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19724.169362 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19724.169362 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19724.169362 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19724.169362 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19724.169362 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # 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number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 428909254 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 428909254 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 428909254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 428909254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 428909254 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 428909254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25348 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 25348 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 25348 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18180.537123 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18180.537123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18180.537123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18180.537123 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 257749 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32583.111771 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 539070 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 290493 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.855707 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 257753 # 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Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994358 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2882.231587 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.601373 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29601.925042 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087959 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002734 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.903379 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994072 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2800 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29426 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 287 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2793 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29433 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7552447 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7552447 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 22764 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 196449750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22617218750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22813668500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 25348 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 712915 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 738263 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 25342 # 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number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 25348 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 782237 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 807585 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101862 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311247 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.304058 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101728 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.368117 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.359758 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68234.968968 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70666.927677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70645.350218 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101862 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.368154 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.359796 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101862 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.368154 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.359796 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76084.333850 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79655.225717 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79614.151910 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74779.951128 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74779.951128 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76084.333850 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78536.372680 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78514.583606 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76084.333850 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78536.372680 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78514.583606 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -725,116 +723,114 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 28 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 27 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 28 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 28 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2574 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221865 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 224439 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2577 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221866 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 224443 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2574 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 287956 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 290530 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2574 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 287956 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 290530 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143321250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13141995500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13285316750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3577310000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3577310000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143321250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16719305500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16862626750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143321250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16719305500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16862626750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311173 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303979 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2577 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 287957 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 290534 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2577 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 287957 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290534 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163845000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14897681250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15061526250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4113937750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4113937750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163845000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19011619000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19175464000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163845000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19011619000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19175464000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.304015 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368081 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.359719 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368081 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.359719 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55680.361305 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59234.198724 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59193.441202 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54127.036964 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54127.036964 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55680.361305 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58062.014683 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55680.361305 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58062.014683 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368120 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.359757 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368120 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.359757 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63579.743888 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67147.202591 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67106.241897 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62246.565342 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62246.565342 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63579.743888 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66022.423487 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66000.757226 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63579.743888 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66022.423487 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66000.757226 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 738337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 738336 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 738263 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 738262 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50683 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656054 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1706737 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1621824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55919168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57540992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655894 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1706589 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55914048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57536256 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 899079 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 899005 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 899079 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 899005 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 899079 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 540959500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 899005 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 540922500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 38562746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 38574245 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1224351972 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1224003723 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224438 # Transaction distribution -system.membus.trans_dist::ReadResp 224438 # Transaction distribution +system.membus.trans_dist::ReadReq 224442 # Transaction distribution +system.membus.trans_dist::ReadResp 224442 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution system.membus.trans_dist::ReadExReq 66091 # Transaction distribution system.membus.trans_dist::ReadExResp 66091 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 647156 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22824128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647164 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 647164 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22824384 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 356627 # Request fanout histogram +system.membus.snoop_fanout::samples 356631 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 356627 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 356631 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 356627 # Request fanout histogram -system.membus.reqLayer0.occupancy 983550500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2739032750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.snoop_fanout::total 356631 # Request fanout histogram +system.membus.reqLayer0.occupancy 731515500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1551221000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 5cb40d175..c41e8c5e9 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.408037 # Number of seconds simulated -sim_ticks 408037199500 # Number of ticks simulated -final_tick 408037199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.409399 # Number of seconds simulated +sim_ticks 409399480000 # Number of ticks simulated +final_tick 409399480000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90640 # Simulator instruction rate (inst/s) -host_op_rate 111590 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57729920 # Simulator tick rate (ticks/s) -host_mem_usage 318440 # Number of bytes of host memory used -host_seconds 7068.04 # Real time elapsed on the host +host_inst_rate 93383 # Simulator instruction rate (inst/s) +host_op_rate 114967 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59675446 # Simulator tick rate (ticks/s) +host_mem_usage 317532 # Number of bytes of host memory used +host_seconds 6860.43 # Real time elapsed on the host sim_insts 640649298 # Number of instructions simulated sim_ops 788724957 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 227200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7008448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12940608 # Number of bytes read from this memory -system.physmem.bytes_read::total 20176256 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 227200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 227200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4244736 # Number of bytes written to this memory -system.physmem.bytes_written::total 4244736 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3550 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 109507 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 202197 # Number of read requests responded to by this memory -system.physmem.num_reads::total 315254 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66324 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66324 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 556812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17176003 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 31714285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 49447099 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 556812 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 556812 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 10402816 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10402816 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 10402816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 556812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17176003 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 31714285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59849916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 315254 # Number of read requests accepted -system.physmem.writeReqs 66324 # Number of write requests accepted -system.physmem.readBursts 315254 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66324 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 20157248 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19008 # Total number of bytes read from write queue -system.physmem.bytesWritten 4240064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 20176256 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4244736 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 297 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 51 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19893 # Per bank write bursts -system.physmem.perBankRdBursts::1 19507 # Per bank write bursts -system.physmem.perBankRdBursts::2 19696 # Per bank write bursts -system.physmem.perBankRdBursts::3 19811 # Per bank write bursts -system.physmem.perBankRdBursts::4 19755 # Per bank write bursts -system.physmem.perBankRdBursts::5 20266 # Per bank write bursts -system.physmem.perBankRdBursts::6 19606 # Per bank write bursts -system.physmem.perBankRdBursts::7 19431 # Per bank write bursts -system.physmem.perBankRdBursts::8 19468 # Per bank write bursts -system.physmem.perBankRdBursts::9 19384 # Per bank write bursts -system.physmem.perBankRdBursts::10 19414 # Per bank write bursts -system.physmem.perBankRdBursts::11 19672 # Per bank write bursts -system.physmem.perBankRdBursts::12 19624 # Per bank write bursts -system.physmem.perBankRdBursts::13 19992 # Per bank write bursts -system.physmem.perBankRdBursts::14 19481 # Per bank write bursts -system.physmem.perBankRdBursts::15 19957 # Per bank write bursts -system.physmem.perBankWrBursts::0 4278 # Per bank write bursts -system.physmem.perBankWrBursts::1 4105 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 232192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7025088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12938560 # Number of bytes read from this memory +system.physmem.bytes_read::total 20195840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 232192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 232192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4244864 # Number of bytes written to this memory +system.physmem.bytes_written::total 4244864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3628 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 109767 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202165 # Number of read requests responded to by this memory +system.physmem.num_reads::total 315560 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66326 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66326 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 567153 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17159494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 31603753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 49330400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 567153 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 567153 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 10368513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10368513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 10368513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 567153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17159494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 31603753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59698913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 315560 # Number of read requests accepted +system.physmem.writeReqs 66326 # Number of write requests accepted +system.physmem.readBursts 315560 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66326 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 20177344 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18496 # Total number of bytes read from write queue +system.physmem.bytesWritten 4238912 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 20195840 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4244864 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 289 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 63 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 16 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19910 # Per bank write bursts +system.physmem.perBankRdBursts::1 19474 # Per bank write bursts +system.physmem.perBankRdBursts::2 19822 # Per bank write bursts +system.physmem.perBankRdBursts::3 19845 # Per bank write bursts +system.physmem.perBankRdBursts::4 19720 # Per bank write bursts +system.physmem.perBankRdBursts::5 20103 # Per bank write bursts +system.physmem.perBankRdBursts::6 19622 # Per bank write bursts +system.physmem.perBankRdBursts::7 19424 # Per bank write bursts +system.physmem.perBankRdBursts::8 19577 # Per bank write bursts +system.physmem.perBankRdBursts::9 19501 # Per bank write bursts +system.physmem.perBankRdBursts::10 19475 # Per bank write bursts +system.physmem.perBankRdBursts::11 19731 # Per bank write bursts +system.physmem.perBankRdBursts::12 19558 # Per bank write bursts +system.physmem.perBankRdBursts::13 20043 # Per bank write bursts +system.physmem.perBankRdBursts::14 19546 # Per bank write bursts +system.physmem.perBankRdBursts::15 19920 # Per bank write bursts +system.physmem.perBankWrBursts::0 4269 # Per bank write bursts +system.physmem.perBankWrBursts::1 4104 # Per bank write bursts system.physmem.perBankWrBursts::2 4141 # Per bank write bursts -system.physmem.perBankWrBursts::3 4152 # Per bank write bursts -system.physmem.perBankWrBursts::4 4250 # Per bank write bursts -system.physmem.perBankWrBursts::5 4232 # Per bank write bursts +system.physmem.perBankWrBursts::3 4150 # Per bank write bursts +system.physmem.perBankWrBursts::4 4244 # Per bank write bursts +system.physmem.perBankWrBursts::5 4227 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts -system.physmem.perBankWrBursts::10 4095 # Per bank write bursts +system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4096 # Per bank write bursts +system.physmem.perBankWrBursts::12 4097 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4151 # Per bank write bursts +system.physmem.perBankWrBursts::15 4154 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 408037145000 # Total gap between requests +system.physmem.totGap 409399425500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 315254 # Read request sizes (log2) +system.physmem.readPktSize::6 315560 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66324 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 128804 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 111420 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6711 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7547 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 8601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 6341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3273 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1270 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66326 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 122658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 117599 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6797 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 8262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 10480 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 3294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1337 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,48 +148,48 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 53 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see @@ -197,113 +197,109 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 136345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.922586 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.860330 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 198.953379 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 53850 39.50% 39.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57322 42.04% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14832 10.88% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1348 0.99% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1343 0.99% 94.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1322 0.97% 95.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1347 0.99% 96.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1288 0.94% 97.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3693 2.71% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 136345 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4024 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.490060 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.867874 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 683.746449 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4004 99.50% 99.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 7 0.17% 99.68% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 3 0.07% 99.75% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 2 0.05% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 2 0.05% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 2 0.05% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-17407 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4024 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4024 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.463966 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.422591 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.272940 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3359 83.47% 83.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 14 0.35% 83.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 449 11.16% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 91 2.26% 97.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 36 0.89% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 19 0.47% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 14 0.35% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 17 0.42% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.20% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 6 0.15% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 4 0.10% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 5 0.12% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4024 # Writes before turning the bus around for reads -system.physmem.totQLat 9384520258 # Total ticks spent queuing -system.physmem.totMemAccLat 15289964008 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1574785000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29796.20 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 136638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.677557 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 128.806703 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.419690 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 53973 39.50% 39.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57563 42.13% 81.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14775 10.81% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1288 0.94% 93.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1420 1.04% 94.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1465 1.07% 95.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1207 0.88% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1190 0.87% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3757 2.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 136638 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4034 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 68.784581 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.732770 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 517.054396 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4014 99.50% 99.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 8 0.20% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 5 0.12% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-6143 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 3 0.07% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::19456-20479 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4034 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4034 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.418691 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.384198 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.147646 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3405 84.41% 84.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 7 0.17% 84.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 450 11.16% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 75 1.86% 97.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 34 0.84% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 21 0.52% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 13 0.32% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 12 0.30% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 6 0.15% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.15% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.07% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4034 # Writes before turning the bus around for reads +system.physmem.totQLat 9487812639 # Total ticks spent queuing +system.physmem.totMemAccLat 15399143889 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1576355000 # Total ticks spent in databus transfers +system.physmem.avgQLat 30094.15 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48546.20 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 49.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 49.45 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 10.40 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48844.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 49.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 10.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 49.33 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 10.37 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.47 # Data bus utilization in percentage system.physmem.busUtilRead 0.39 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing -system.physmem.readRowHits 218395 # Number of row buffer hits during reads -system.physmem.writeRowHits 26455 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.34 # Row buffer hit rate for reads +system.physmem.avgWrQLen 24.86 # Average write queue length when enqueuing +system.physmem.readRowHits 218399 # Number of row buffer hits during reads +system.physmem.writeRowHits 26454 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate 39.92 # Row buffer hit rate for writes -system.physmem.avgGap 1069341.38 # Average gap between requests -system.physmem.pageHitRate 64.23 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 517708800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 282480000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1231869600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216613440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26650578240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96151044510 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 160475521500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 285525816090 # Total energy per rank (pJ) -system.physmem_0.averagePower 699.765171 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 266332221673 # Time in different power states -system.physmem_0.memoryStateTime::REF 13625040000 # Time in different power states +system.physmem.avgGap 1072046.17 # Average gap between requests +system.physmem.pageHitRate 64.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 517640760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 282442875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1231518600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216464400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26739576240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96784987680 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 160736987250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 286509617805 # Total energy per rank (pJ) +system.physmem_0.averagePower 699.839198 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 266762765318 # Time in different power states +system.physmem_0.memoryStateTime::REF 13670540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 128074629327 # Time in different power states +system.physmem_0.memoryStateTime::ACT 128960598682 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 512870400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 279840000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1224147600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212693040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26650578240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96078218175 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 160539404250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 285497751705 # Total energy per rank (pJ) -system.physmem_1.averagePower 699.696391 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 266439995679 # Time in different power states -system.physmem_1.memoryStateTime::REF 13625040000 # Time in different power states +system.physmem_1.actEnergy 515168640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 281094000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1226955600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212725440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26739576240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96280028955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 161179933500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 286435482375 # Total energy per rank (pJ) +system.physmem_1.averagePower 699.658112 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 267502793659 # Time in different power states +system.physmem_1.memoryStateTime::REF 13670540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 127966985321 # Time in different power states +system.physmem_1.memoryStateTime::ACT 128220707341 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 233958621 # Number of BP lookups -system.cpu.branchPred.condPredicted 161821709 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15514987 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 121572023 # Number of BTB lookups -system.cpu.branchPred.BTBHits 108258061 # Number of BTB hits +system.cpu.branchPred.lookups 234006176 # Number of BP lookups +system.cpu.branchPred.condPredicted 161868409 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15514584 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 121529948 # Number of BTB lookups +system.cpu.branchPred.BTBHits 108213709 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.048498 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25035636 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300514 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.042833 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25036783 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300149 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -422,84 +418,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 816074400 # number of cpu cycles simulated +system.cpu.numCycles 818798961 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 84077011 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200073954 # Number of instructions fetch has processed -system.cpu.fetch.Branches 233958621 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133293697 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 716167787 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31064641 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2347 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 84078294 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1200783068 # Number of instructions fetch has processed +system.cpu.fetch.Branches 234006176 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133250492 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 718844861 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31063585 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2466 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 2996 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 370071850 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652472 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 815782492 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.838759 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.161594 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3349 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370656305 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652882 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 818460793 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.833394 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.163540 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 134746116 16.52% 16.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 222503118 27.27% 43.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 98075778 12.02% 55.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 360457480 44.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 136795118 16.71% 16.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 223180654 27.27% 43.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98074923 11.98% 55.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 360410098 44.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 815782492 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.286688 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.470545 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 119982553 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 156985722 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484662665 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38632910 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518642 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 25180928 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13826 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248143840 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39966741 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518642 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 176992343 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 77462427 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 207446 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464957580 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 80644054 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190653894 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 25546220 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24993767 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2267123 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 40253162 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1738390 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1225396904 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5812470532 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358186197 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876541 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 818460793 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285792 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.466518 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 119991092 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 159658898 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484662986 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38629701 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518116 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 25135087 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13824 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248129900 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39966537 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518116 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176998470 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 78894904 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 210510 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464956548 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81882245 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190637892 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 25457774 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24955109 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2267146 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 41533192 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1699566 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1225425199 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5812490436 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358169789 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876588 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 350618674 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 350646969 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 7267 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108147318 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 366118935 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236099157 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1781337 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5349105 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1168566408 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 108140115 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 366205100 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236096667 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1646330 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5328678 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1168639452 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 12360 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017104063 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18374377 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 379747029 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1032159170 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1017122920 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18523621 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 379819992 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1032577011 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 815782492 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.246783 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.084999 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 818460793 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.242727 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.084979 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 258071655 31.63% 31.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 228431382 28.00% 59.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 215339964 26.40% 86.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 97765220 11.98% 98.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16174262 1.98% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 260810349 31.87% 31.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 227739162 27.83% 59.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 216495712 26.45% 86.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 97269955 11.88% 98.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16145606 1.97% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -507,44 +503,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 815782492 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 818460793 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 64513595 19.12% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18145 0.01% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 155496772 46.10% 65.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116668709 34.59% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 64512117 19.12% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18144 0.01% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 155573719 46.11% 65.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116674794 34.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456384260 44.87% 44.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5195827 0.51% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456371749 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5195830 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued @@ -568,88 +564,88 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478997 1.13% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322085949 31.67% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215583681 21.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322115143 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215585851 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017104063 # Type of FU issued -system.cpu.iq.rate 1.246337 # Inst issue rate -system.cpu.iq.fu_busy_cnt 337334110 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.331661 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3143822052 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1504778489 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934283929 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61877053 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565817 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 26152444 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1320627818 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33810355 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9960647 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1017122920 # Type of FU issued +system.cpu.iq.rate 1.242213 # Inst issue rate +system.cpu.iq.fu_busy_cnt 337415663 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.331735 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3146768879 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1504924384 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934270592 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61877038 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565805 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 26152443 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1320728240 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 33810343 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9960122 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 113877997 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1254 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18512 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107118661 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 113964162 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1106 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18388 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 107116171 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065827 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22129 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065787 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22375 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518642 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35326933 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 672265 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1168584324 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 15518116 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35326355 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 41902 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1168657365 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 366118935 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236099157 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 366205100 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236096667 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6620 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 110 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 675878 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18512 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437821 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784778 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19222599 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974764839 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303299768 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42339224 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 109 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 45517 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18388 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15437362 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784555 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19221917 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 974750423 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303297711 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42372497 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 5556 # number of nop insts executed -system.cpu.iew.exec_refs 497763810 # number of memory reference insts executed -system.cpu.iew.exec_branches 150614661 # Number of branches executed -system.cpu.iew.exec_stores 194464042 # Number of stores executed -system.cpu.iew.exec_rate 1.194456 # Inst execution rate -system.cpu.iew.wb_sent 963735760 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960436373 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536684839 # num instructions producing a value -system.cpu.iew.wb_consumers 893296754 # num instructions consuming a value +system.cpu.iew.exec_nop 5553 # number of nop insts executed +system.cpu.iew.exec_refs 497763737 # number of memory reference insts executed +system.cpu.iew.exec_branches 150613650 # Number of branches executed +system.cpu.iew.exec_stores 194466026 # Number of stores executed +system.cpu.iew.exec_rate 1.190464 # Inst execution rate +system.cpu.iew.wb_sent 963723367 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960423035 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536681402 # num instructions producing a value +system.cpu.iew.wb_consumers 893284482 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.176898 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600791 # average fanout of values written-back +system.cpu.iew.wb_rate 1.172966 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600796 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 357425480 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357409752 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15501309 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 764959828 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.031074 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.790810 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15500908 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 767640271 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.027474 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.786859 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 428887379 56.07% 56.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 171843268 22.46% 78.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73566556 9.62% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 31622898 4.13% 92.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 7902308 1.03% 93.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14889162 1.95% 95.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7268582 0.95% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6618939 0.87% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22360736 2.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 430932808 56.14% 56.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 172476946 22.47% 78.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73566678 9.58% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 31624021 4.12% 92.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8540196 1.11% 93.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14250754 1.86% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7269409 0.95% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6618976 0.86% 97.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22360483 2.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 764959828 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 767640271 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654410 # Number of instructions committed system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -695,382 +691,382 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction -system.cpu.commit.bw_lim_events 22360736 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22360483 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1888745890 # The number of ROB reads -system.cpu.rob.rob_writes 2343137518 # The number of ROB writes -system.cpu.timesIdled 647360 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 291908 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1891410858 # The number of ROB reads +system.cpu.rob.rob_writes 2343104087 # The number of ROB writes +system.cpu.timesIdled 647398 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 338168 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649298 # Number of Instructions Simulated system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.273824 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.273824 # CPI: Total CPI of All Threads -system.cpu.ipc 0.785038 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.785038 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995816176 # number of integer regfile reads -system.cpu.int_regfile_writes 567918829 # number of integer regfile writes -system.cpu.fp_regfile_reads 31889844 # number of floating regfile reads +system.cpu.cpi 1.278077 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.278077 # CPI: Total CPI of All Threads +system.cpu.ipc 0.782426 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.782426 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995803851 # number of integer regfile reads +system.cpu.int_regfile_writes 567906934 # number of integer regfile writes +system.cpu.fp_regfile_reads 31889841 # number of floating regfile reads system.cpu.fp_regfile_writes 22959492 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794477294 # number of cc regfile reads -system.cpu.cc_regfile_writes 384905750 # number of cc regfile writes -system.cpu.misc_regfile_reads 715814324 # number of misc regfile reads +system.cpu.cc_regfile_reads 3794434058 # number of cc regfile reads +system.cpu.cc_regfile_writes 384899317 # number of cc regfile writes +system.cpu.misc_regfile_reads 715816288 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2756166 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.936576 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414250087 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756678 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.271481 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 246939500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.936576 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999876 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999876 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2756182 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.932940 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414226912 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756694 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.262202 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 257775000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.932940 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999869 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 189 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839347788 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839347788 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286297988 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286297988 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127937398 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127937398 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3156 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3156 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 839344268 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839344268 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286295518 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286295518 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127916671 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127916671 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3177 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3177 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414235386 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414235386 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414238542 # number of overall hits -system.cpu.dcache.overall_hits::total 414238542 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3030809 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3030809 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1014079 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1014079 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 414212189 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414212189 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414215366 # number of overall hits +system.cpu.dcache.overall_hits::total 414215366 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3031489 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3031489 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1034806 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1034806 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4044888 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4044888 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4045534 # number of overall misses -system.cpu.dcache.overall_misses::total 4045534 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33766010929 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33766010929 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9872401734 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9872401734 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 175500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 175500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 43638412663 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 43638412663 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 43638412663 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 43638412663 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289328797 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289328797 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4066295 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4066295 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4066942 # number of overall misses +system.cpu.dcache.overall_misses::total 4066942 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35316006617 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35316006617 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10004118304 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10004118304 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 202750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 202750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45320124921 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45320124921 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45320124921 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45320124921 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289327007 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289327007 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3802 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3802 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3824 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3824 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418280274 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418280274 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418284076 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418284076 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010475 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010475 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007864 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.007864 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169911 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.169911 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 418278484 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418278484 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418282308 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418282308 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010478 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010478 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008025 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008025 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169195 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.169195 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009670 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009670 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009672 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009672 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11140.923407 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11140.923407 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9735.337912 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9735.337912 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10788.534235 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10788.534235 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10786.811497 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10786.811497 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009722 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009722 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009723 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009723 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11649.722832 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11649.722832 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9667.626883 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9667.626883 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 67583.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 67583.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11145.311622 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11145.311622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11143.538541 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11143.538541 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 383706 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 349732 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 5260 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 5194 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 72.947909 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 67.333847 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 735128 # number of writebacks -system.cpu.dcache.writebacks::total 735128 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 995619 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 995619 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 293215 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 293215 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 735277 # number of writebacks +system.cpu.dcache.writebacks::total 735277 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996280 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 996280 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 313945 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 313945 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1288834 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1288834 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1288834 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1288834 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035190 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035190 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720864 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 720864 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 1310225 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1310225 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1310225 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1310225 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28726022904 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28726022904 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168595 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168595 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.167626 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.167626 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006590 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006590 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10344.289288 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10344.289288 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7292.293831 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7292.293831 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8868.137285 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8868.137285 # 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Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.584092 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 237857250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.721915 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997504 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997504 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 5169874 # number of replacements +system.cpu.icache.tags.tagsinuse 510.641329 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 365482216 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5170384 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.687635 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 247770250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.641329 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997346 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997346 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 328 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 745313375 # Number of tag accesses -system.cpu.icache.tags.data_accesses 745313375 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 364900028 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 364900028 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 364900028 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 364900028 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 364900028 # number of overall hits -system.cpu.icache.overall_hits::total 364900028 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5171791 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5171791 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5171791 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5171791 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5171791 # number of overall misses -system.cpu.icache.overall_misses::total 5171791 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41611685167 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8045.894578 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 67339 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 39 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2239 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 30.075480 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 9.750000 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 746482947 # Number of tag accesses +system.cpu.icache.tags.data_accesses 746482947 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 365482251 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 365482251 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 365482251 # 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number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41654200685 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 41654200685 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41654200685 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 370656273 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 370656273 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 370656273 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 370656273 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 370656273 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 370656273 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013959 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013959 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013959 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013959 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013959 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013959 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8050.642360 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8050.642360 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8050.642360 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8050.642360 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8050.642360 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8050.642360 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 76485 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 100 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3140 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 24.358280 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2054 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2054 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2054 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2054 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2054 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2054 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169737 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5169737 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5169737 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5169737 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5169737 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5169737 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33819004202 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33819004202 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33819004202 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33819004202 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33819004202 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33819004202 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013970 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013970 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013970 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6541.726243 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6541.726243 # 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average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73307.728460 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73307.728460 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74122.964315 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77971.933067 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77851.219959 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74122.964315 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77971.933067 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77851.219959 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1079,145 +1075,143 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66324 # number of writebacks -system.cpu.l2cache.writebacks::total 66324 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1342 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 1353 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1474 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1474 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 2816 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 2827 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 2816 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 2827 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3550 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108130 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 111680 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202272 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 202272 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1377 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6595705626 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18462254833 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25263927480 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053113 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015499 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.writebacks::writebacks 66326 # number of writebacks +system.cpu.l2cache.writebacks::total 66326 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1303 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 1318 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1445 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1445 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 2748 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 2763 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 2748 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 2763 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3628 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108380 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 112008 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202241 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 202241 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1387 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1387 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3628 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 109767 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 113395 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3628 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 109767 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202241 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 315636 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 238098541 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7611970750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7850069291 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 17087057356 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 17087057356 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 219516 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 219516 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114561754 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114561754 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 238098541 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7726532504 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7964631045 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 238098541 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7726532504 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17087057356 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25051688401 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053236 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015543 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823529 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823529 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039724 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039724 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039818 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014305 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039818 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.039782 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58018.879155 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59831.449422 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59773.832799 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91274.397015 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91274.397015 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91598.402324 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91598.402324 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58018.879155 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60230.904198 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60161.446412 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58018.879155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60230.904198 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91274.397015 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80119.264261 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.039817 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65628.043275 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70234.090699 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70084.898320 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84488.592105 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84488.592105 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13719.750000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13719.750000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82596.794521 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82596.794521 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65628.043275 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70390.304044 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.938578 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65628.043275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70390.304044 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84488.592105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79368.919898 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7205568 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7205568 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 735128 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 316987 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 7206252 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7206251 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 735277 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 248818 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10339458 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248518 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16587976 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330862144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223475584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 554337728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 317003 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8978547 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.035305 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.184549 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 720844 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720844 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340787 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248699 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16589486 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330904640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223486144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 554390784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 248834 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 8911208 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.027922 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.164749 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 8661560 96.47% 96.47% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 316987 3.53% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 8662390 97.21% 97.21% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 248818 2.79% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8978547 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5065908000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 8911208 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5066472000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7755114990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7756152507 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4143326908 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4138701196 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 313877 # Transaction distribution -system.membus.trans_dist::ReadResp 313877 # Transaction distribution -system.membus.trans_dist::Writeback 66324 # Transaction distribution -system.membus.trans_dist::UpgradeReq 14 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14 # Transaction distribution -system.membus.trans_dist::ReadExReq 1377 # Transaction distribution -system.membus.trans_dist::ReadExResp 1377 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 696860 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 696860 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24420992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24420992 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 314173 # Transaction distribution +system.membus.trans_dist::ReadResp 314173 # Transaction distribution +system.membus.trans_dist::Writeback 66326 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16 # Transaction distribution +system.membus.trans_dist::UpgradeResp 16 # Transaction distribution +system.membus.trans_dist::ReadExReq 1387 # Transaction distribution +system.membus.trans_dist::ReadExResp 1387 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697478 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 697478 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24440704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24440704 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 381592 # Request fanout histogram +system.membus.snoop_fanout::samples 381902 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 381592 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 381902 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 381592 # Request fanout histogram -system.membus.reqLayer0.occupancy 993954700 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 381902 # Request fanout histogram +system.membus.reqLayer0.occupancy 746879857 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2896150900 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 1648874306 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 4817ec8a9..ba52b772d 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu sim_ticks 395726778000 # Number of ticks simulated final_tick 395726778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1395078 # Simulator instruction rate (inst/s) -host_op_rate 1717525 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 861727739 # Simulator tick rate (ticks/s) -host_mem_usage 309420 # Number of bytes of host memory used -host_seconds 459.22 # Real time elapsed on the host +host_inst_rate 1601804 # Simulator instruction rate (inst/s) +host_op_rate 1972032 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 989420456 # Simulator tick rate (ticks/s) +host_mem_usage 309588 # Number of bytes of host memory used +host_seconds 399.96 # Real time elapsed on the host sim_insts 640654410 # Number of instructions simulated sim_ops 788730069 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 system.membus.pkt_size::total 4241547521 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 1022670352 # Request fanout histogram -system.membus.snoop_fanout::mean 4.629116 # Request fanout histogram +system.membus.snoop_fanout::mean 2.629116 # Request fanout histogram system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 379292454 37.09% 37.09% # Request fanout histogram -system.membus.snoop_fanout::5 643377898 62.91% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 379292454 37.09% 37.09% # Request fanout histogram +system.membus.snoop_fanout::3 643377898 62.91% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 1022670352 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index c5e3a18fc..e078716d2 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.043695 # Number of seconds simulated -sim_ticks 1043695084000 # Number of ticks simulated -final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1043695077500 # Number of ticks simulated +final_tick 1043695077500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 894518 # Simulator instruction rate (inst/s) -host_op_rate 1098969 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1460200235 # Simulator tick rate (ticks/s) -host_mem_usage 317628 # Number of bytes of host memory used -host_seconds 714.76 # Real time elapsed on the host +host_inst_rate 877071 # Simulator instruction rate (inst/s) +host_op_rate 1077535 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1431720298 # Simulator tick rate (ticks/s) +host_mem_usage 317788 # Number of bytes of host memory used +host_seconds 728.98 # Real time elapsed on the host sim_insts 639366786 # Number of instructions simulated sim_ops 785501034 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 2087390168 # number of cpu cycles simulated +system.cpu.numCycles 2087390155 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 639366786 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 381221435 # nu system.cpu.num_load_insts 252240938 # Number of load instructions system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 2087390167.998000 # Number of busy cycles +system.cpu.num_busy_cycles 2087390154.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 137364859 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730743 # Class of executed instruction system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.640576 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4093.640588 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 996417000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640576 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 996414000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640588 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003 system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17513638000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17513638000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3573167500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3573167500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1682500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1682500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21086805500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21086805500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21088488000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21088488000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -342,24 +342,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24574.336308 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24574.336308 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51543.751713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51543.751713 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12104.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12104.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26965.120978 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26965.120978 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26962.479959 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26962.479959 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 8769 # number of replacements -system.cpu.icache.tags.tagsinuse 1391.464499 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1391.464503 # Cycle average of tags in use system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464499 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464503 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id @@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst 10208 # n system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses system.cpu.icache.overall_misses::total 10208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 207122500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 207122500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 207122500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 207122500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 207122500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 207122500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 207116000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 207116000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 207116000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 207116000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 207116000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 207116000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 643377899 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 643377899 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 643377899 # number of demand (read+write) accesses @@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20290.213558 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20290.213558 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20290.213558 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20290.213558 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20289.576803 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20289.576803 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20289.576803 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20289.576803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20289.576803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20289.576803 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,34 +419,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10208 system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 186706500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 186706500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186706500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 186706500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186706500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 186706500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191804000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 191804000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191804000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 191804000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191804000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 191804000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18290.213558 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18290.213558 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18789.576803 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18789.576803 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18789.576803 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18789.576803 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18789.576803 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18789.576803 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 256932 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32626.698092 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32626.698188 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 524746 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 289675 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.811499 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505475 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505447 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.080663 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.111953 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.112078 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.085221 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001498 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.908969 # Average percentage of cache occupancy @@ -484,17 +484,17 @@ system.cpu.l2cache.demand_misses::total 289712 # nu system.cpu.l2cache.overall_misses::cpu.inst 1770 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 287942 # number of overall misses system.cpu.l2cache.overall_misses::total 289712 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 92118500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11536392000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11628510500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3436883000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3436883000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 92118500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 14973275000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15065393500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 92118500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 14973275000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15065393500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 92997000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11647316500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11740313500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3469929500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3469929500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 92997000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15117246000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15210243000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 92997000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15117246000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15210243000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 10208 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 712819 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 723027 # number of ReadReq accesses(hits+misses) @@ -519,17 +519,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.365636 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.173393 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.368145 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.365636 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52044.350282 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52001.099847 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52001.442185 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.711119 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.711119 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52044.350282 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.010620 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52001.275405 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52044.350282 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.010620 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52001.275405 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52540.677966 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52501.099847 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.413118 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.711119 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.711119 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52540.677966 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.010620 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.252968 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52540.677966 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.010620 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.252968 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -551,17 +551,17 @@ system.cpu.l2cache.demand_mshr_misses::total 289712 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1770 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 287942 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 289712 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70811000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8873960000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8944771000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2643720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2643720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70811000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11517680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11588491000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70811000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11517680000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11588491000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 71689000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8984884500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9056573500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2676766500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2676766500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71689000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11661651000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11733340000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71689000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11661651000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11733340000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311228 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309282 # mshr miss rate for ReadReq accesses @@ -573,17 +573,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.365636 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368145 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.365636 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.214689 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.049191 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.214689 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.214689 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.259887 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.017888 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.259887 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.259887 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution @@ -598,19 +598,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 883911 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 883911 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) @@ -638,9 +636,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 355811 # Request fanout histogram -system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 632634000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1448919000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 47efecce5..acacb719c 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058585 # Number of seconds simulated -sim_ticks 58584661500 # Number of ticks simulated -final_tick 58584661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.059745 # Number of seconds simulated +sim_ticks 59744560000 # Number of ticks simulated +final_tick 59744560000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 201524 # Simulator instruction rate (inst/s) -host_op_rate 201524 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 133496887 # Simulator tick rate (ticks/s) -host_mem_usage 290684 # Number of bytes of host memory used -host_seconds 438.85 # Real time elapsed on the host +host_inst_rate 336953 # Simulator instruction rate (inst/s) +host_op_rate 336953 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 227629544 # Simulator tick rate (ticks/s) +host_mem_usage 304552 # Number of bytes of host memory used +host_seconds 262.46 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 516608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 517248 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10147776 # Number of bytes read from this memory -system.physmem.bytes_read::total 10664384 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 516608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 516608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7299072 # Number of bytes written to this memory -system.physmem.bytes_written::total 7299072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8072 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 10665024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 517248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 517248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7299008 # Number of bytes written to this memory +system.physmem.bytes_written::total 7299008 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8082 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 158559 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166631 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114048 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114048 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8818144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 173215578 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 182033722 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8818144 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8818144 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 124590154 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 124590154 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 124590154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8818144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 173215578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 306623876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166631 # Number of read requests accepted -system.physmem.writeReqs 114048 # Number of write requests accepted -system.physmem.readBursts 166631 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114048 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10663872 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue -system.physmem.bytesWritten 7297088 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10664384 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7299072 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 166641 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114047 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114047 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8657659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 169852720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 178510378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8657659 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8657659 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 122170253 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 122170253 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 122170253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8657659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 169852720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 300680631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166641 # Number of read requests accepted +system.physmem.writeReqs 114047 # Number of write requests accepted +system.physmem.readBursts 166641 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114047 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10664448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue +system.physmem.bytesWritten 7297216 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10665024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7299008 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10466 # Per bank write bursts -system.physmem.perBankRdBursts::1 10512 # Per bank write bursts +system.physmem.perBankRdBursts::0 10464 # Per bank write bursts +system.physmem.perBankRdBursts::1 10514 # Per bank write bursts system.physmem.perBankRdBursts::2 10315 # Per bank write bursts -system.physmem.perBankRdBursts::3 10093 # Per bank write bursts -system.physmem.perBankRdBursts::4 10429 # Per bank write bursts +system.physmem.perBankRdBursts::3 10095 # Per bank write bursts +system.physmem.perBankRdBursts::4 10432 # Per bank write bursts system.physmem.perBankRdBursts::5 10431 # Per bank write bursts -system.physmem.perBankRdBursts::6 9849 # Per bank write bursts -system.physmem.perBankRdBursts::7 10302 # Per bank write bursts -system.physmem.perBankRdBursts::8 10595 # Per bank write bursts +system.physmem.perBankRdBursts::6 9850 # Per bank write bursts +system.physmem.perBankRdBursts::7 10303 # Per bank write bursts +system.physmem.perBankRdBursts::8 10594 # Per bank write bursts system.physmem.perBankRdBursts::9 10644 # Per bank write bursts -system.physmem.perBankRdBursts::10 10598 # Per bank write bursts -system.physmem.perBankRdBursts::11 10258 # Per bank write bursts -system.physmem.perBankRdBursts::12 10302 # Per bank write bursts -system.physmem.perBankRdBursts::13 10653 # Per bank write bursts +system.physmem.perBankRdBursts::10 10596 # Per bank write bursts +system.physmem.perBankRdBursts::11 10260 # Per bank write bursts +system.physmem.perBankRdBursts::12 10303 # Per bank write bursts +system.physmem.perBankRdBursts::13 10654 # Per bank write bursts system.physmem.perBankRdBursts::14 10528 # Per bank write bursts -system.physmem.perBankRdBursts::15 10648 # Per bank write bursts +system.physmem.perBankRdBursts::15 10649 # Per bank write bursts system.physmem.perBankWrBursts::0 7087 # Per bank write bursts system.physmem.perBankWrBursts::1 7261 # Per bank write bursts system.physmem.perBankWrBursts::2 7255 # Per bank write bursts system.physmem.perBankWrBursts::3 6998 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7176 # Per bank write bursts +system.physmem.perBankWrBursts::5 7178 # Per bank write bursts system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7084 # Per bank write bursts -system.physmem.perBankWrBursts::8 7223 # Per bank write bursts -system.physmem.perBankWrBursts::9 6938 # Per bank write bursts -system.physmem.perBankWrBursts::10 7096 # Per bank write bursts -system.physmem.perBankWrBursts::11 6991 # Per bank write bursts -system.physmem.perBankWrBursts::12 6966 # Per bank write bursts +system.physmem.perBankWrBursts::7 7080 # Per bank write bursts +system.physmem.perBankWrBursts::8 7224 # Per bank write bursts +system.physmem.perBankWrBursts::9 6940 # Per bank write bursts +system.physmem.perBankWrBursts::10 7097 # Per bank write bursts +system.physmem.perBankWrBursts::11 6990 # Per bank write bursts +system.physmem.perBankWrBursts::12 6967 # Per bank write bursts system.physmem.perBankWrBursts::13 7289 # Per bank write bursts system.physmem.perBankWrBursts::14 7284 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58584634500 # Total gap between requests +system.physmem.totGap 59744533000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166631 # Read request sizes (log2) +system.physmem.readPktSize::6 166641 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114048 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165000 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1595 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114047 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165067 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7023 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -193,122 +193,121 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54549 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 329.259345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.795576 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.998077 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19535 35.81% 35.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11763 21.56% 57.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5616 10.30% 67.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3566 6.54% 74.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2684 4.92% 79.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2055 3.77% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1672 3.07% 85.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1540 2.82% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6118 11.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54549 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7016 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.746152 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 348.264922 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7014 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 54673 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 328.521940 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.158907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.861003 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19447 35.57% 35.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11824 21.63% 57.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5661 10.35% 67.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3636 6.65% 74.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2772 5.07% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2160 3.95% 83.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1686 3.08% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1520 2.78% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5967 10.91% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54673 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7019 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.740134 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 348.174119 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7017 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7016 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7016 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.250998 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.234711 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.764594 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6252 89.11% 89.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 8 0.11% 89.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 591 8.42% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 125 1.78% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 23 0.33% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 8 0.11% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 5 0.07% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7016 # Writes before turning the bus around for reads -system.physmem.totQLat 1948128750 # Total ticks spent queuing -system.physmem.totMemAccLat 5072310000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 833115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11691.84 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7019 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.245939 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.230597 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.737975 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6255 89.13% 89.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 17 0.24% 89.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 574 8.18% 97.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 144 2.05% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 20 0.28% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 4 0.06% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7018 # Writes before turning the bus around for reads +system.physmem.totQLat 1983100250 # Total ticks spent queuing +system.physmem.totMemAccLat 5107450250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 833160000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11901.08 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30441.84 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 182.02 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 124.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 182.03 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 124.59 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30651.08 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 178.50 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 122.14 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 178.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 122.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.40 # Data bus utilization in percentage -system.physmem.busUtilRead 1.42 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.97 # Data bus utilization in percentage for writes +system.physmem.busUtil 2.35 # Data bus utilization in percentage +system.physmem.busUtilRead 1.39 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.95 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.07 # Average write queue length when enqueuing -system.physmem.readRowHits 144841 # Number of row buffer hits during reads -system.physmem.writeRowHits 81248 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.93 # Row buffer hit rate for reads +system.physmem.avgWrQLen 24.05 # Average write queue length when enqueuing +system.physmem.readRowHits 144723 # Number of row buffer hits during reads +system.physmem.writeRowHits 81251 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.85 # Row buffer hit rate for reads system.physmem.writeRowHitRate 71.24 # Row buffer hit rate for writes -system.physmem.avgGap 208724.68 # Average gap between requests -system.physmem.pageHitRate 80.55 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 199077480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 108623625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 642681000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 367791840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3826405440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12184332255 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24462392250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41791303890 # Total energy per rank (pJ) -system.physmem_0.averagePower 713.356895 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40549753500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1956240000 # Time in different power states +system.physmem.avgGap 212850.33 # Average gap between requests +system.physmem.pageHitRate 80.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 199115280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 108644250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 642735600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 367778880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3902180880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12699594585 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24706498500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42626547975 # Total energy per rank (pJ) +system.physmem_0.averagePower 713.484810 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 40950314500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1994980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16078529000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16799112000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 213282720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116374500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 656908200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371038320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3826405440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 12703202685 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24007242750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41894454615 # Total energy per rank (pJ) -system.physmem_1.averagePower 715.117627 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 39789307500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1956240000 # Time in different power states +system.physmem_1.actEnergy 214197480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116873625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 656962800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371031840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3902180880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13192492680 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24274131750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42727871055 # Total energy per rank (pJ) +system.physmem_1.averagePower 715.180760 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40226086750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1994980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 16838471250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17523103250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14678313 # Number of BP lookups -system.cpu.branchPred.condPredicted 9498021 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 389703 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9975544 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6390264 # Number of BTB hits +system.cpu.branchPred.lookups 14679718 # Number of BP lookups +system.cpu.branchPred.condPredicted 9498983 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 392764 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10434122 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6393495 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 64.059303 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1709596 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 85905 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.274873 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1709689 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 85822 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20567455 # DTB read hits -system.cpu.dtb.read_misses 96888 # DTB read misses +system.cpu.dtb.read_hits 20566953 # DTB read hits +system.cpu.dtb.read_misses 96874 # DTB read misses system.cpu.dtb.read_acv 11 # DTB read access violations -system.cpu.dtb.read_accesses 20664343 # DTB read accesses -system.cpu.dtb.write_hits 14665775 # DTB write hits -system.cpu.dtb.write_misses 9411 # DTB write misses +system.cpu.dtb.read_accesses 20663827 # DTB read accesses +system.cpu.dtb.write_hits 14666692 # DTB write hits +system.cpu.dtb.write_misses 9419 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14675186 # DTB write accesses -system.cpu.dtb.data_hits 35233230 # DTB hits -system.cpu.dtb.data_misses 106299 # DTB misses +system.cpu.dtb.write_accesses 14676111 # DTB write accesses +system.cpu.dtb.data_hits 35233645 # DTB hits +system.cpu.dtb.data_misses 106293 # DTB misses system.cpu.dtb.data_acv 11 # DTB access violations -system.cpu.dtb.data_accesses 35339529 # DTB accesses -system.cpu.itb.fetch_hits 25627333 # ITB hits -system.cpu.itb.fetch_misses 5261 # ITB misses +system.cpu.dtb.data_accesses 35339938 # DTB accesses +system.cpu.itb.fetch_hits 25640132 # ITB hits +system.cpu.itb.fetch_misses 5244 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25632594 # ITB accesses +system.cpu.itb.fetch_accesses 25645376 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -322,81 +321,81 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 117169323 # number of cpu cycles simulated +system.cpu.numCycles 119489120 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1098705 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1100288 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.324874 # CPI: cycles per instruction -system.cpu.ipc 0.754789 # IPC: instructions per cycle -system.cpu.tickCycles 91571156 # Number of cycles that the object actually ticked -system.cpu.idleCycles 25598167 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 200776 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.523211 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34616515 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204872 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 168.966550 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 644809250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4071.523211 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.994024 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994024 # Average percentage of cache occupancy +system.cpu.cpi 1.351105 # CPI: cycles per instruction +system.cpu.ipc 0.740135 # IPC: instructions per cycle +system.cpu.tickCycles 91601603 # Number of cycles that the object actually ticked +system.cpu.idleCycles 27887517 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 200784 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.582702 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34615842 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204880 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 168.956667 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 693853250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.582702 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993795 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993795 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 745 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3298 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 678 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3372 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70176892 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70176892 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20283193 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20283193 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333322 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333322 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34616515 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34616515 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34616515 # number of overall hits -system.cpu.dcache.overall_hits::total 34616515 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89440 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89440 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280055 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280055 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 369495 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369495 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 369495 # number of overall misses -system.cpu.dcache.overall_misses::total 369495 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4407640500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4407640500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19996177500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19996177500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24403818000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24403818000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24403818000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24403818000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20372633 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20372633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70175650 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70175650 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20282569 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20282569 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333273 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333273 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34615842 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34615842 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34615842 # number of overall hits +system.cpu.dcache.overall_hits::total 34615842 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89439 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89439 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280104 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280104 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 369543 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369543 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 369543 # number of overall misses +system.cpu.dcache.overall_misses::total 369543 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4793461000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4793461000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21859170750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21859170750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26652631750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26652631750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26652631750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26652631750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20372008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20372008 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34986010 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34986010 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34986010 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34986010 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34985385 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34985385 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34985385 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34985385 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004390 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004390 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019164 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019164 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010561 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010561 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010561 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010561 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49280.417039 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49280.417039 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71400.894467 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71400.894467 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66046.409288 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66046.409288 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66046.409288 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66046.409288 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010563 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010563 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010563 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010563 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53594.751730 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53594.751730 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78039.480871 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 78039.480871 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72123.221790 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72123.221790 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72123.221790 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72123.221790 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -405,32 +404,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168546 # number of writebacks -system.cpu.dcache.writebacks::total 168546 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28125 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 28125 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136498 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136498 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 164623 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 164623 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 164623 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 164623 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61315 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61315 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143557 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143557 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204872 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204872 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204872 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204872 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2422248250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2422248250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9931035500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9931035500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12353283750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12353283750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12353283750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12353283750 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168547 # number of writebacks +system.cpu.dcache.writebacks::total 168547 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28118 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 28118 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136545 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136545 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 164663 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 164663 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 164663 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 164663 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61321 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61321 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143559 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143559 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204880 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204880 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204880 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204880 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2650982250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2650982250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10919810750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10919810750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13570793000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13570793000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13570793000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13570793000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses @@ -439,68 +438,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39504.986545 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39504.986545 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69178.343794 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69178.343794 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60297.569946 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60297.569946 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60297.569946 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60297.569946 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43231.229921 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43231.229921 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76064.968062 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76064.968062 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66237.763569 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66237.763569 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66237.763569 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66237.763569 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 153786 # number of replacements -system.cpu.icache.tags.tagsinuse 1934.126530 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25471498 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 155834 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 163.452764 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 41649701250 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16222.023236 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16222.023236 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16222.023236 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16580.645782 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16580.645782 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16580.645782 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16580.645782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16580.645782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16580.645782 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60838.418191 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60760.494683 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::total 166642 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 538585250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1889755250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2428340500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9006674250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9006674250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 538585250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10896429500 # 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Transaction distribution +system.membus.trans_dist::ReadReq 35759 # Transaction distribution +system.membus.trans_dist::ReadResp 35759 # Transaction distribution +system.membus.trans_dist::Writeback 114047 # Transaction distribution system.membus.trans_dist::ReadExReq 130882 # Transaction distribution system.membus.trans_dist::ReadExResp 130882 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447310 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 447310 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17963456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17963456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447329 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 447329 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17964032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17964032 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 280679 # Request fanout histogram +system.membus.snoop_fanout::samples 280688 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 280679 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 280688 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 280679 # Request fanout histogram -system.membus.reqLayer0.occupancy 1304618000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1602414250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.7 # Layer utilization (%) +system.membus.snoop_fanout::total 280688 # Request fanout histogram +system.membus.reqLayer0.occupancy 817068000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 879892750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 6d3efb0ae..c7130e3ac 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022282 # Number of seconds simulated -sim_ticks 22281815500 # Number of ticks simulated -final_tick 22281815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022578 # Number of seconds simulated +sim_ticks 22578120000 # Number of ticks simulated +final_tick 22578120000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 227860 # Simulator instruction rate (inst/s) -host_op_rate 227860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63789654 # Simulator tick rate (ticks/s) -host_mem_usage 305428 # Number of bytes of host memory used -host_seconds 349.30 # Real time elapsed on the host +host_inst_rate 224564 # Simulator instruction rate (inst/s) +host_op_rate 224564 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63702871 # Simulator tick rate (ticks/s) +host_mem_usage 305848 # Number of bytes of host memory used +host_seconds 354.43 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 487168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10151488 # Number of bytes read from this memory -system.physmem.bytes_read::total 10638656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 487168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 487168 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7296384 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296384 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7612 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158617 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166229 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114006 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114006 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 21863928 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 455595192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 477459119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 21863928 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 21863928 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 327459134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 327459134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 327459134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 21863928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 455595192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 804918253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166229 # Number of read requests accepted -system.physmem.writeReqs 114006 # Number of write requests accepted -system.physmem.readBursts 166229 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114006 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytes_read::cpu.inst 487616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10151104 # Number of bytes read from this memory +system.physmem.bytes_read::total 10638720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 487616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 487616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7296832 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296832 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7619 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158611 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166230 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114013 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114013 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 21596838 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 449599169 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 471196007 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 21596838 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 21596838 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 323181558 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 323181558 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 323181558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 21596838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 449599169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 794377566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166230 # Number of read requests accepted +system.physmem.writeReqs 114013 # Number of write requests accepted +system.physmem.readBursts 166230 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114013 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 10638144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue -system.physmem.bytesWritten 7294656 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10638656 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7296384 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue +system.physmem.bytesWritten 7294912 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10638720 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7296832 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10438 # Per bank write bursts -system.physmem.perBankRdBursts::1 10454 # Per bank write bursts -system.physmem.perBankRdBursts::2 10317 # Per bank write bursts -system.physmem.perBankRdBursts::3 10059 # Per bank write bursts -system.physmem.perBankRdBursts::4 10417 # Per bank write bursts -system.physmem.perBankRdBursts::5 10393 # Per bank write bursts +system.physmem.perBankRdBursts::0 10435 # Per bank write bursts +system.physmem.perBankRdBursts::1 10460 # Per bank write bursts +system.physmem.perBankRdBursts::2 10318 # Per bank write bursts +system.physmem.perBankRdBursts::3 10058 # Per bank write bursts +system.physmem.perBankRdBursts::4 10413 # Per bank write bursts +system.physmem.perBankRdBursts::5 10396 # Per bank write bursts system.physmem.perBankRdBursts::6 9837 # Per bank write bursts -system.physmem.perBankRdBursts::7 10310 # Per bank write bursts -system.physmem.perBankRdBursts::8 10606 # Per bank write bursts -system.physmem.perBankRdBursts::9 10643 # Per bank write bursts -system.physmem.perBankRdBursts::10 10543 # Per bank write bursts -system.physmem.perBankRdBursts::11 10224 # Per bank write bursts -system.physmem.perBankRdBursts::12 10268 # Per bank write bursts -system.physmem.perBankRdBursts::13 10616 # Per bank write bursts -system.physmem.perBankRdBursts::14 10478 # Per bank write bursts -system.physmem.perBankRdBursts::15 10618 # Per bank write bursts +system.physmem.perBankRdBursts::7 10308 # Per bank write bursts +system.physmem.perBankRdBursts::8 10587 # Per bank write bursts +system.physmem.perBankRdBursts::9 10644 # Per bank write bursts +system.physmem.perBankRdBursts::10 10547 # Per bank write bursts +system.physmem.perBankRdBursts::11 10228 # Per bank write bursts +system.physmem.perBankRdBursts::12 10270 # Per bank write bursts +system.physmem.perBankRdBursts::13 10618 # Per bank write bursts +system.physmem.perBankRdBursts::14 10481 # Per bank write bursts +system.physmem.perBankRdBursts::15 10621 # Per bank write bursts system.physmem.perBankWrBursts::0 7083 # Per bank write bursts -system.physmem.perBankWrBursts::1 7253 # Per bank write bursts +system.physmem.perBankWrBursts::1 7259 # Per bank write bursts system.physmem.perBankWrBursts::2 7255 # Per bank write bursts system.physmem.perBankWrBursts::3 6997 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7169 # Per bank write bursts -system.physmem.perBankWrBursts::6 6770 # Per bank write bursts -system.physmem.perBankWrBursts::7 7085 # Per bank write bursts -system.physmem.perBankWrBursts::8 7220 # Per bank write bursts -system.physmem.perBankWrBursts::9 6943 # Per bank write bursts -system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::5 7171 # Per bank write bursts +system.physmem.perBankWrBursts::6 6772 # Per bank write bursts +system.physmem.perBankWrBursts::7 7083 # Per bank write bursts +system.physmem.perBankWrBursts::8 7219 # Per bank write bursts +system.physmem.perBankWrBursts::9 6939 # Per bank write bursts +system.physmem.perBankWrBursts::10 7083 # Per bank write bursts system.physmem.perBankWrBursts::11 6988 # Per bank write bursts system.physmem.perBankWrBursts::12 6964 # Per bank write bursts -system.physmem.perBankWrBursts::13 7287 # Per bank write bursts -system.physmem.perBankWrBursts::14 7283 # Per bank write bursts +system.physmem.perBankWrBursts::13 7288 # Per bank write bursts +system.physmem.perBankWrBursts::14 7284 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22281781500 # Total gap between requests +system.physmem.totGap 22578086500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166229 # Read request sizes (log2) +system.physmem.readPktSize::6 166230 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114006 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 51659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54099 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45462 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14988 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114013 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 52462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32153 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -193,124 +193,121 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52189 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.580755 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.430431 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 344.457165 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18353 35.17% 35.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10742 20.58% 55.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5641 10.81% 66.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3092 5.92% 72.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2629 5.04% 77.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1694 3.25% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1790 3.43% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1288 2.47% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6960 13.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52189 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6966 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.861757 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 342.246517 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6964 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 52260 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 343.127440 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.641716 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 343.309325 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18423 35.25% 35.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10477 20.05% 55.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5934 11.35% 66.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2978 5.70% 72.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2855 5.46% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1509 2.89% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2072 3.96% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 924 1.77% 86.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7088 13.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52260 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6982 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.804927 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 342.249057 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6981 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6966 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6965 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.363676 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.332802 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.079402 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6068 87.12% 87.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 30 0.43% 87.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 495 7.11% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 185 2.66% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 91 1.31% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 46 0.66% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 21 0.30% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.14% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 10 0.14% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 5 0.07% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6965 # Writes before turning the bus around for reads -system.physmem.totQLat 5436579750 # Total ticks spent queuing -system.physmem.totMemAccLat 8553223500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.rdPerTurnAround::total 6982 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6982 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.325265 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.299310 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.979398 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6150 88.08% 88.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 25 0.36% 88.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 468 6.70% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 181 2.59% 97.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 78 1.12% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 46 0.66% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 19 0.27% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.14% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 4 0.06% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6982 # Writes before turning the bus around for reads +system.physmem.totQLat 5742111500 # Total ticks spent queuing +system.physmem.totMemAccLat 8858755250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 831105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32706.94 # Average queueing delay per DRAM burst +system.physmem.avgQLat 34545.04 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51456.94 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 477.44 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 327.38 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 477.46 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 327.46 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53295.04 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 471.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 323.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 471.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 323.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.29 # Data bus utilization in percentage -system.physmem.busUtilRead 3.73 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.56 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing -system.physmem.readRowHits 146012 # Number of row buffer hits during reads -system.physmem.writeRowHits 81986 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.91 # Row buffer hit rate for writes -system.physmem.avgGap 79511.06 # Average gap between requests -system.physmem.pageHitRate 81.36 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 190496880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 103941750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 641043000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 367539120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1454990160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6553751985 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 7617131250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 16928894145 # Total energy per rank (pJ) -system.physmem_0.averagePower 759.936312 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12590169250 # Time in different power states -system.physmem_0.memoryStateTime::REF 743860000 # Time in different power states +system.physmem.busUtil 6.21 # Data bus utilization in percentage +system.physmem.busUtilRead 3.68 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.52 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing +system.physmem.readRowHits 146222 # Number of row buffer hits during reads +system.physmem.writeRowHits 81709 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.97 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.67 # Row buffer hit rate for writes +system.physmem.avgGap 80566.10 # Average gap between requests +system.physmem.pageHitRate 81.34 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 190685880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 104044875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 641035200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 367584480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1474315440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6555814245 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7792863750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 17126343870 # Total energy per rank (pJ) +system.physmem_0.averagePower 758.721685 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12883309000 # Time in different power states +system.physmem_0.memoryStateTime::REF 753740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8942711000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8935594000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 203779800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 111189375 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 204104880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 111366750 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 654919200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 370694880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1454990160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6762785805 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 7433764500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 16992123720 # Total energy per rank (pJ) -system.physmem_1.averagePower 762.774895 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 12284853000 # Time in different power states -system.physmem_1.memoryStateTime::REF 743860000 # Time in different power states +system.physmem_1.writeEnergy 370701360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1474315440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6889050495 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 7500532500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 17204990625 # Total energy per rank (pJ) +system.physmem_1.averagePower 762.206905 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 12395641000 # Time in different power states +system.physmem_1.memoryStateTime::REF 753740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9248437000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9423231500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16624924 # Number of BP lookups -system.cpu.branchPred.condPredicted 10755300 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 362268 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10924107 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7374828 # Number of BTB hits +system.cpu.branchPred.lookups 16619938 # Number of BP lookups +system.cpu.branchPred.condPredicted 10751763 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 361573 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10694449 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7373128 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 67.509665 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1991560 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2903 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 68.943505 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1990233 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3119 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22639897 # DTB read hits -system.cpu.dtb.read_misses 226363 # DTB read misses -system.cpu.dtb.read_acv 23 # DTB read access violations -system.cpu.dtb.read_accesses 22866260 # DTB read accesses -system.cpu.dtb.write_hits 15870343 # DTB write hits -system.cpu.dtb.write_misses 44837 # DTB write misses +system.cpu.dtb.read_hits 22587975 # DTB read hits +system.cpu.dtb.read_misses 226213 # DTB read misses +system.cpu.dtb.read_acv 17 # DTB read access violations +system.cpu.dtb.read_accesses 22814188 # DTB read accesses +system.cpu.dtb.write_hits 15866557 # DTB write hits +system.cpu.dtb.write_misses 44947 # DTB write misses system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 15915180 # DTB write accesses -system.cpu.dtb.data_hits 38510240 # DTB hits -system.cpu.dtb.data_misses 271200 # DTB misses -system.cpu.dtb.data_acv 24 # DTB access violations -system.cpu.dtb.data_accesses 38781440 # DTB accesses -system.cpu.itb.fetch_hits 13919462 # ITB hits -system.cpu.itb.fetch_misses 31654 # ITB misses +system.cpu.dtb.write_accesses 15911504 # DTB write accesses +system.cpu.dtb.data_hits 38454532 # DTB hits +system.cpu.dtb.data_misses 271160 # DTB misses +system.cpu.dtb.data_acv 18 # DTB access violations +system.cpu.dtb.data_accesses 38725692 # DTB accesses +system.cpu.itb.fetch_hits 13913083 # ITB hits +system.cpu.itb.fetch_misses 32600 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13951116 # ITB accesses +system.cpu.itb.fetch_accesses 13945683 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -324,240 +321,240 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 44563634 # number of cpu cycles simulated +system.cpu.numCycles 45156244 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15791560 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106158478 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16624924 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9366388 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27217966 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 963396 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 137 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4946 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 337279 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 111 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13919462 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 206375 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 43833697 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.421846 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.133787 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15767330 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106100961 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16619938 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9363361 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27775290 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 962592 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 208 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5030 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 339291 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 71 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13913083 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 207051 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 44368516 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.391357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.125574 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24095007 54.97% 54.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1538131 3.51% 58.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1406372 3.21% 61.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1524721 3.48% 65.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4235690 9.66% 74.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1846144 4.21% 79.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 685371 1.56% 80.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1070354 2.44% 83.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7431907 16.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24640012 55.53% 55.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1537852 3.47% 59.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1401576 3.16% 62.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1522530 3.43% 65.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4244947 9.57% 75.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1845094 4.16% 79.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 677475 1.53% 80.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1069981 2.41% 83.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7429049 16.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43833697 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.373060 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.382177 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15105656 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9282610 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18470395 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 592044 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 382992 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3741910 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 100605 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 104048931 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 315835 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 382992 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15490766 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6387964 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 95966 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18655378 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2820631 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102900646 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4493 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 152365 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 320462 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2296242 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61929819 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124171537 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123841536 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 330000 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44368516 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.368054 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.349641 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15099347 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9823247 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18465046 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 597969 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 382907 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3741515 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 100209 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 104016227 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 314595 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 382907 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15487504 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6707215 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 96849 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18654699 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3039342 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102867556 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4643 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 101006 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 348263 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2491758 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61906530 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124122948 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123794647 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 328300 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9382938 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5791 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5849 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2464589 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23265416 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16459353 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1262626 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 544604 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91320451 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5681 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89124415 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 80151 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11242959 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4725710 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1098 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43833697 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.033240 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.247678 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9359649 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5745 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5793 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2522683 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23265731 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16453437 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1244012 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 539260 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91299347 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5639 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89055311 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 77552 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11218941 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4714239 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1056 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44368516 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.007174 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.246117 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17209661 39.26% 39.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5800175 13.23% 52.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5098270 11.63% 64.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4410681 10.06% 74.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4347575 9.92% 84.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2649961 6.05% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1950790 4.45% 94.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1381860 3.15% 97.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 984724 2.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17795444 40.11% 40.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5774110 13.01% 53.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5077311 11.44% 64.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4396727 9.91% 74.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4357066 9.82% 84.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2650893 5.97% 90.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1948119 4.39% 94.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1385813 3.12% 97.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 983033 2.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43833697 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44368516 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 244354 9.65% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1175209 46.41% 56.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1112799 43.94% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 243204 9.64% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1172094 46.45% 56.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1108166 43.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49663354 55.72% 55.72% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 44187 0.05% 55.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 122171 0.14% 55.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 55.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121874 0.14% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39065 0.04% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23057459 25.87% 81.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16076160 18.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49651741 55.75% 55.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 44157 0.05% 55.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121956 0.14% 55.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 55.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121436 0.14% 56.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39055 0.04% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23004684 25.83% 81.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16072139 18.05% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89124415 # Type of FU issued -system.cpu.iq.rate 1.999936 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2532362 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028414 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 224079080 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102152200 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87178162 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 615960 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 437940 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 301333 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 91348643 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 308134 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1658507 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89055311 # Type of FU issued +system.cpu.iq.rate 1.972159 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2523465 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028336 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 224465346 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102111433 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87163804 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 614809 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 433572 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 300747 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 91271228 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 307548 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1661543 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2988778 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6943 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 21591 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1845976 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2989093 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6317 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21548 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1840060 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3051 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 325532 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3023 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 186080 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 382992 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1216204 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4841557 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100851766 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 147146 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23265416 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16459353 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5598 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3356 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4819285 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 21591 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 151679 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 156559 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 308238 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88344034 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22866899 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 780381 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 382907 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1413856 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4974138 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100829471 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 151929 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23265731 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16453437 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5565 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4999 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4957861 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 21548 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 151078 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 158072 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 309150 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88275465 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22814985 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 779846 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9525634 # number of nop insts executed -system.cpu.iew.exec_refs 38782381 # number of memory reference insts executed -system.cpu.iew.exec_branches 15172546 # Number of branches executed -system.cpu.iew.exec_stores 15915482 # Number of stores executed -system.cpu.iew.exec_rate 1.982424 # Inst execution rate -system.cpu.iew.wb_sent 87895909 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87479495 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33899568 # num instructions producing a value -system.cpu.iew.wb_consumers 44349597 # num instructions consuming a value +system.cpu.iew.exec_nop 9524485 # number of nop insts executed +system.cpu.iew.exec_refs 38726852 # number of memory reference insts executed +system.cpu.iew.exec_branches 15171568 # Number of branches executed +system.cpu.iew.exec_stores 15911867 # Number of stores executed +system.cpu.iew.exec_rate 1.954889 # Inst execution rate +system.cpu.iew.wb_sent 87882002 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87464551 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33900833 # num instructions producing a value +system.cpu.iew.wb_consumers 44342613 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.963024 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764372 # average fanout of values written-back +system.cpu.iew.wb_rate 1.936931 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764520 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9308985 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9282281 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 263562 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42463328 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.080399 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.884681 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 263184 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43000551 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.054408 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.876009 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20917493 49.26% 49.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6333939 14.92% 64.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2944595 6.93% 71.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1757333 4.14% 75.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1653620 3.89% 79.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1138333 2.68% 81.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1205391 2.84% 84.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 793939 1.87% 86.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5718685 13.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21467431 49.92% 49.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6329802 14.72% 64.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2918642 6.79% 71.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1760390 4.09% 75.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1670777 3.89% 79.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1138707 2.65% 82.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1203989 2.80% 84.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 794665 1.85% 86.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5716148 13.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42463328 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43000551 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -603,344 +600,344 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5718685 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5716148 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133076958 # The number of ROB reads -system.cpu.rob.rob_writes 196673244 # The number of ROB writes -system.cpu.timesIdled 48172 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 729937 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133590014 # The number of ROB reads +system.cpu.rob.rob_writes 196617452 # The number of ROB writes +system.cpu.timesIdled 47547 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 787728 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.559903 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.559903 # CPI: Total CPI of All Threads -system.cpu.ipc 1.786025 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.786025 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116925772 # number of integer regfile reads -system.cpu.int_regfile_writes 57936362 # number of integer regfile writes -system.cpu.fp_regfile_reads 255891 # number of floating regfile reads -system.cpu.fp_regfile_writes 241873 # number of floating regfile writes -system.cpu.misc_regfile_reads 38152 # number of misc regfile reads +system.cpu.cpi 0.567348 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.567348 # CPI: Total CPI of All Threads +system.cpu.ipc 1.762586 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.762586 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116851082 # number of integer regfile reads +system.cpu.int_regfile_writes 57926468 # number of integer regfile writes +system.cpu.fp_regfile_reads 255690 # number of floating regfile reads +system.cpu.fp_regfile_writes 241313 # number of floating regfile writes +system.cpu.misc_regfile_reads 38160 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 201381 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.852002 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34090259 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205477 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.907907 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 215961000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4071.852002 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.994104 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994104 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 201362 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.706489 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34086491 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205458 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.904910 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 231989000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.706489 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993825 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993825 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2773 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2590 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1430 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 71020605 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 71020605 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20525911 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20525911 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13564288 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13564288 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 60 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 60 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34090199 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34090199 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34090199 # number of overall hits -system.cpu.dcache.overall_hits::total 34090199 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 268215 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 268215 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1049089 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1049089 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 71020044 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 71020044 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20525035 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20525035 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13561393 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13561393 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 63 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 63 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34086428 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34086428 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34086428 # number of overall hits +system.cpu.dcache.overall_hits::total 34086428 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 268817 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 268817 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1051984 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1051984 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1317304 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1317304 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1317304 # number of overall misses -system.cpu.dcache.overall_misses::total 1317304 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 16911598996 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 16911598996 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 85714857886 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 85714857886 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102626456882 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102626456882 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102626456882 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102626456882 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20794126 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20794126 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1320801 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1320801 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1320801 # number of overall misses +system.cpu.dcache.overall_misses::total 1320801 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17503667749 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17503667749 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 89467046923 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 89467046923 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 99750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 99750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106970714672 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106970714672 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106970714672 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106970714672 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20793852 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20793852 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35407503 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35407503 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35407503 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35407503 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012899 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012899 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071790 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071790 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016393 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016393 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037204 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037204 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037204 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037204 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63052.398248 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63052.398248 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81704.086008 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81704.086008 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77906.433809 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77906.433809 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77906.433809 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77906.433809 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6293239 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 254 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 146230 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 64 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 64 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35407229 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35407229 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35407229 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35407229 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012928 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012928 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071988 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071988 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.015625 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.015625 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037303 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037303 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037303 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037303 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65113.693513 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 65113.693513 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85046.014885 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 85046.014885 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 99750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 99750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80989.274442 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80989.274442 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80989.274442 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80989.274442 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6831456 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 275 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 88055 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.036579 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 127 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.581693 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 137.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168920 # number of writebacks -system.cpu.dcache.writebacks::total 168920 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206147 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 206147 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 905681 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 905681 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1111828 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1111828 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1111828 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1111828 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62068 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62068 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143408 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143408 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168921 # number of writebacks +system.cpu.dcache.writebacks::total 168921 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206754 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 206754 # 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number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14187677704 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 97750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 97750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17379598205 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17379598205 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17379598205 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17379598205 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002985 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002985 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # 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average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48596.511133 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93222.007670 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93222.007670 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79742.013320 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 79742.013320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79742.013320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 79742.013320 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51430.328875 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51430.328875 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98941.920192 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98941.920192 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 97750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 97750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84589.954127 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84589.954127 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84589.954127 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84589.954127 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # 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Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 94996 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 145.323593 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19026930250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1916.254210 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.935671 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.935671 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1489 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 370 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1478 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 379 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27934642 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27934642 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13810732 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13810732 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13810732 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13810732 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13810732 # 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number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13805160 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13805160 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13805160 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13805160 # number of overall hits +system.cpu.icache.overall_hits::total 13805160 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 107922 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 107922 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 107922 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 107922 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 107922 # number of overall misses +system.cpu.icache.overall_misses::total 107922 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2071977734 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2071977734 # 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miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007757 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007757 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007757 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007757 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007757 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19198.844851 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19198.844851 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19198.844851 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19198.844851 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19198.844851 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19198.844851 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 448 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 66.312500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 44.800000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 13005 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 13005 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 13005 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 13005 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 13005 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 13005 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 95723 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 95723 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 95723 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 95723 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 95723 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 95723 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1546277535 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1546277535 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1546277535 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1546277535 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1546277535 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1546277535 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006877 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006877 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006877 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006877 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006877 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006877 # 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number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 472609250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2266008500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2738617750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11494650500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11494650500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 472609250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13760659000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14233268250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 472609250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13760659000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14233268250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.079532 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448386 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.224621 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911980 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911980 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.079532 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771945 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.551892 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.079532 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771945 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.551892 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62079.239459 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 81423.230327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77268.226448 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87888.326057 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87888.326057 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62079.239459 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86753.998626 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85623.944234 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62079.239459 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86753.998626 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85623.944234 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::total 35450 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130781 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130781 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7620 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158611 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166231 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7620 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158611 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166231 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 527900750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2422370000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2950270750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12290499750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12290499750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 527900750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14712869750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15240770500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 527900750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14712869750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15240770500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.080213 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448415 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.225710 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912033 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912033 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.080213 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771987 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.553264 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.080213 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771987 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.553264 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69278.313648 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 87041.681639 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 83223.434415 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93977.716564 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93977.716564 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69278.313648 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 92760.714894 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91684.285723 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69278.313648 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 92760.714894 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91684.285723 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 157790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 157789 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168920 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 191445 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579874 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 771319 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6126208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23961408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30087616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 157060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 157059 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168921 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143395 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189993 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579837 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 769830 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6079744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23960256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30040000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 470120 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 469376 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 470120 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 469376 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 470120 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 403980000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 469376 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 403609000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 144944965 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 321950247 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 143899236 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 325469999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 35442 # Transaction distribution -system.membus.trans_dist::ReadResp 35442 # Transaction distribution -system.membus.trans_dist::Writeback 114006 # Transaction distribution -system.membus.trans_dist::ReadExReq 130787 # Transaction distribution -system.membus.trans_dist::ReadExResp 130787 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446464 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446464 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17935040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17935040 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 35449 # Transaction distribution +system.membus.trans_dist::ReadResp 35449 # Transaction distribution +system.membus.trans_dist::Writeback 114013 # Transaction distribution +system.membus.trans_dist::ReadExReq 130781 # Transaction distribution +system.membus.trans_dist::ReadExResp 130781 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446473 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446473 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17935552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17935552 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 280235 # Request fanout histogram +system.membus.snoop_fanout::samples 280243 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 280235 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 280243 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 280235 # Request fanout histogram -system.membus.reqLayer0.occupancy 1235714000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1525262750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.8 # Layer utilization (%) +system.membus.snoop_fanout::total 280243 # Request fanout histogram +system.membus.reqLayer0.occupancy 786749500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 865056500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 06edb9753..987ba828d 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133635 # Number of seconds simulated -sim_ticks 133634727000 # Number of ticks simulated -final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133634 # Number of seconds simulated +sim_ticks 133634149500 # Number of ticks simulated +final_tick 133634149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1471745 # Simulator instruction rate (inst/s) -host_op_rate 1471745 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2226337698 # Simulator tick rate (ticks/s) -host_mem_usage 297712 # Number of bytes of host memory used -host_seconds 60.02 # Real time elapsed on the host +host_inst_rate 1329181 # Simulator instruction rate (inst/s) +host_op_rate 1329181 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2010669405 # Simulator tick rate (ticks/s) +host_mem_usage 301232 # Number of bytes of host memory used +host_seconds 66.46 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,41 +25,17 @@ system.physmem.num_reads::cpu.data 158389 # Nu system.physmem.num_reads::total 165153 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113982 # Number of write requests responded to by this memory system.physmem.num_writes::total 113982 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 3239397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75855253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 79094650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3239397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3239397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54587966 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54587966 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54587966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3239397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75855253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 133682617 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 34272 # Transaction distribution -system.membus.trans_dist::ReadResp 34272 # Transaction distribution -system.membus.trans_dist::Writeback 113982 # Transaction distribution -system.membus.trans_dist::ReadExReq 130881 # Transaction distribution -system.membus.trans_dist::ReadExResp 130881 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 279135 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 279135 # Request fanout histogram -system.membus.reqLayer0.occupancy 1190991000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 1486377000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.1 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 3239411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75855581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 79094992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3239411 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3239411 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54588202 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54588202 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54588202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3239411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75855581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 133683195 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -94,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 267269454 # number of cpu cycles simulated +system.cpu.numCycles 267268299 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88340673 # Number of instructions committed @@ -113,7 +89,7 @@ system.cpu.num_mem_refs 34987415 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_store_insts 14620629 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 267269454 # Number of busy cycles +system.cpu.num_busy_cycles 267268299 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 13754477 # Number of branches fetched @@ -152,13 +128,120 @@ system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 88438073 # Class of executed instruction +system.cpu.dcache.tags.replacements 200248 # number of replacements +system.cpu.dcache.tags.tagsinuse 4078.863526 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 936464000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863526 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 482 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3562 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits +system.cpu.dcache.overall_hits::total 34685671 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses +system.cpu.dcache.overall_misses::total 204344 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945427000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1945427000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363527000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7363527000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9308954000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9308954000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9308954000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9308954000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32015.057763 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32015.057763 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51285.900347 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51285.900347 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45555.308695 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45555.308695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45555.308695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45555.308695 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks +system.cpu.dcache.writebacks::total 168375 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1854278000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1854278000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7148160000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7148160000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9002438000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9002438000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9002438000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9002438000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30515.057763 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30515.057763 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49785.900347 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49785.900347 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44055.308695 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44055.308695 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44055.308695 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44055.308695 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 74391 # number of replacements -system.cpu.icache.tags.tagsinuse 1871.686406 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1871.686268 # Cycle average of tags in use system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686268 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id @@ -181,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1278112000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1278112000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1278112000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1278112000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1278112000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1278112000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1277887500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1277887500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1277887500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1277887500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1277887500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1277887500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses @@ -199,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16721.335496 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16721.335496 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16721.335496 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16721.335496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16721.335496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16721.335496 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16718.398399 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16718.398399 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16718.398399 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16718.398399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16718.398399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16718.398399 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -219,43 +302,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 76436 system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1125240000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1125240000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1125240000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1125240000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1125240000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1125240000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1163233500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1163233500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1163233500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1163233500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1163233500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1163233500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14721.335496 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14721.335496 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15218.398399 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15218.398399 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15218.398399 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15218.398399 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15218.398399 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15218.398399 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 131235 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30728.810101 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30728.805700 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 142024 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 163291 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.869760 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27298.448351 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.833083 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 27298.442194 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.509533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853974 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.833082 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.937769 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32056 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 655 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9976 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21194 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 654 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9977 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21193 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 117 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978271 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3900109 # Number of tag accesses @@ -284,17 +367,17 @@ system.cpu.l2cache.demand_misses::total 165153 # nu system.cpu.l2cache.overall_misses::cpu.inst 6764 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 158389 # number of overall misses system.cpu.l2cache.overall_misses::total 165153 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 352084000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1430874000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1782958000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6805851000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6805851000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 352084000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8236725000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8588809000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 352084000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8236725000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8588809000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 355241500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1444303000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1799544500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6871263500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6871263500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 355241500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8315566500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8670808000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 355241500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8315566500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8670808000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 76436 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60766 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 137202 # number of ReadReq accesses(hits+misses) @@ -319,17 +402,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.588194 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088492 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.775110 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.588194 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52052.631579 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52016.649702 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52023.751167 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.297981 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.297981 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52052.631579 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52003.137844 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52005.164908 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52052.631579 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.137844 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52005.164908 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.441159 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.834957 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52507.717670 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.084046 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.084046 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.441159 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.909154 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.668150 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.441159 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.909154 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.668150 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,17 +434,17 @@ system.cpu.l2cache.demand_mshr_misses::total 165153 system.cpu.l2cache.overall_mshr_misses::cpu.inst 6764 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158389 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 165153 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 270916000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1100778000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1371694000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5235279000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5235279000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 270916000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6336057000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6606973000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 270916000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6336057000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6606973000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 274073000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1114207000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1388280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5300691500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5300691500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 274073000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6414898500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6688971500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 274073000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6414898500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6688971500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.452687 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.249792 # mshr miss rate for ReadReq accesses @@ -373,125 +456,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.588194 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.588194 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40052.631579 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40016.649702 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40023.751167 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.297981 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.297981 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40052.631579 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40052.631579 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40519.367238 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40504.834957 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40507.703081 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.084046 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.084046 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 200248 # number of replacements -system.cpu.dcache.tags.tagsinuse 4078.863631 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 936463000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 482 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3562 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits -system.cpu.dcache.overall_hits::total 34685671 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses -system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945752000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1945752000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363555000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7363555000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9309307000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9309307000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9309307000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9309307000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32020.406148 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32020.406148 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51286.095363 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 51286.095363 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45557.036174 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45557.036174 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks -system.cpu.dcache.writebacks::total 168375 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1824220000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1824220000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7076399000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7076399000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8900619000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8900619000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8900619000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8900619000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30020.406148 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.406148 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49286.095363 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49286.095363 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution @@ -521,5 +497,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 114654000 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 34272 # Transaction distribution +system.membus.trans_dist::ReadResp 34272 # Transaction distribution +system.membus.trans_dist::Writeback 113982 # Transaction distribution +system.membus.trans_dist::ReadExReq 130881 # Transaction distribution +system.membus.trans_dist::ReadExResp 130881 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 279135 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 279135 # Request fanout histogram +system.membus.reqLayer0.occupancy 748161500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 825765500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index b9814d1e2..20f3ef2c3 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057816 # Number of seconds simulated -sim_ticks 57815555000 # Number of ticks simulated -final_tick 57815555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058730 # Number of seconds simulated +sim_ticks 58730125500 # Number of ticks simulated +final_tick 58730125500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131971 # Simulator instruction rate (inst/s) -host_op_rate 168772 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 107593052 # Simulator tick rate (ticks/s) -host_mem_usage 309228 # Number of bytes of host memory used -host_seconds 537.35 # Real time elapsed on the host +host_inst_rate 197162 # Simulator instruction rate (inst/s) +host_op_rate 252141 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 163284235 # Simulator tick rate (ticks/s) +host_mem_usage 321164 # Number of bytes of host memory used +host_seconds 359.68 # Real time elapsed on the host sim_insts 70915127 # Number of instructions simulated sim_ops 90690083 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 324480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7923328 # Number of bytes read from this memory -system.physmem.bytes_read::total 8247808 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 324480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 324480 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 324352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7923392 # Number of bytes read from this memory +system.physmem.bytes_read::total 8247744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5070 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123802 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128872 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 5068 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123803 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128871 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5612330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 137044918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 142657249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5612330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5612330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 92931115 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 92931115 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 92931115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5612330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 137044918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 235588364 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128872 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 5522753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 134911886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 140434639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5522753 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5522753 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 91483952 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 91483952 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 91483952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5522753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 134911886 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 231918592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128871 # Number of read requests accepted system.physmem.writeReqs 83951 # Number of write requests accepted -system.physmem.readBursts 128872 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 128871 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8247424 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 5370880 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8247808 # Total read bytes from the system interface side +system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8247744 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 8159 # Per bank write bursts -system.physmem.perBankRdBursts::1 8375 # Per bank write bursts -system.physmem.perBankRdBursts::2 8229 # Per bank write bursts +system.physmem.perBankRdBursts::1 8376 # Per bank write bursts +system.physmem.perBankRdBursts::2 8228 # Per bank write bursts system.physmem.perBankRdBursts::3 8171 # Per bank write bursts -system.physmem.perBankRdBursts::4 8320 # Per bank write bursts +system.physmem.perBankRdBursts::4 8319 # Per bank write bursts system.physmem.perBankRdBursts::5 8450 # Per bank write bursts system.physmem.perBankRdBursts::6 8088 # Per bank write bursts -system.physmem.perBankRdBursts::7 7970 # Per bank write bursts +system.physmem.perBankRdBursts::7 7969 # Per bank write bursts system.physmem.perBankRdBursts::8 8071 # Per bank write bursts system.physmem.perBankRdBursts::9 7640 # Per bank write bursts -system.physmem.perBankRdBursts::10 7820 # Per bank write bursts -system.physmem.perBankRdBursts::11 7830 # Per bank write bursts +system.physmem.perBankRdBursts::10 7818 # Per bank write bursts +system.physmem.perBankRdBursts::11 7832 # Per bank write bursts system.physmem.perBankRdBursts::12 7881 # Per bank write bursts system.physmem.perBankRdBursts::13 7879 # Per bank write bursts system.physmem.perBankRdBursts::14 7977 # Per bank write bursts -system.physmem.perBankRdBursts::15 8006 # Per bank write bursts -system.physmem.perBankWrBursts::0 5183 # Per bank write bursts +system.physmem.perBankRdBursts::15 8007 # Per bank write bursts +system.physmem.perBankWrBursts::0 5180 # Per bank write bursts system.physmem.perBankWrBursts::1 5376 # Per bank write bursts system.physmem.perBankWrBursts::2 5285 # Per bank write bursts system.physmem.perBankWrBursts::3 5155 # Per bank write bursts system.physmem.perBankWrBursts::4 5266 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5194 # Per bank write bursts -system.physmem.perBankWrBursts::7 5048 # Per bank write bursts +system.physmem.perBankWrBursts::6 5197 # Per bank write bursts +system.physmem.perBankWrBursts::7 5050 # Per bank write bursts system.physmem.perBankWrBursts::8 5033 # Per bank write bursts -system.physmem.perBankWrBursts::9 5086 # Per bank write bursts -system.physmem.perBankWrBursts::10 5252 # Per bank write bursts +system.physmem.perBankWrBursts::9 5087 # Per bank write bursts +system.physmem.perBankWrBursts::10 5251 # Per bank write bursts system.physmem.perBankWrBursts::11 5143 # Per bank write bursts system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5225 # Per bank write bursts +system.physmem.perBankWrBursts::15 5227 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57815523000 # Total gap between requests +system.physmem.totGap 58730091000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128872 # Read request sizes (log2) +system.physmem.readPktSize::6 128871 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,8 +98,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 83951 # Write request sizes (log2) system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5167 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5161 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,100 +193,98 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38442 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 354.194267 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.182491 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.610229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12218 31.78% 31.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8019 20.86% 52.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4166 10.84% 63.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2872 7.47% 70.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2487 6.47% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1677 4.36% 81.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1283 3.34% 85.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1207 3.14% 88.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4513 11.74% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38442 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.976343 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 360.782218 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 353.122851 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.043714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.345734 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12150 31.51% 31.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8188 21.23% 52.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4125 10.70% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2946 7.64% 71.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2498 6.48% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1699 4.41% 81.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1309 3.39% 85.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1159 3.01% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4485 11.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38559 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5160 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.968217 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 360.537784 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5158 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.273027 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.256397 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.767804 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4530 87.84% 87.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 6 0.12% 87.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 497 9.64% 97.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 105 2.04% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 11 0.21% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.06% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads -system.physmem.totQLat 1505377000 # Total ticks spent queuing -system.physmem.totMemAccLat 3921614500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 644330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11681.72 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5160 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5160 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.264341 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.248462 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.748642 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4548 88.14% 88.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 7 0.14% 88.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 485 9.40% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 104 2.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 10 0.19% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.06% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5160 # Writes before turning the bus around for reads +system.physmem.totQLat 1533027250 # Total ticks spent queuing +system.physmem.totMemAccLat 3949246000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11896.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30431.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 142.65 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 92.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 142.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 92.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30646.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 140.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 91.45 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 140.43 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 91.48 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.84 # Data bus utilization in percentage -system.physmem.busUtilRead 1.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.81 # Data bus utilization in percentage +system.physmem.busUtilRead 1.10 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.71 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing -system.physmem.readRowHits 112203 # Number of row buffer hits during reads -system.physmem.writeRowHits 62134 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.01 # Row buffer hit rate for writes -system.physmem.avgGap 271660.13 # Average gap between requests -system.physmem.pageHitRate 81.92 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 150995880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 82388625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512779800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 272315520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11724732990 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24403046250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 40922317065 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.837327 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40469303500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1930500000 # Time in different power states +system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing +system.physmem.readRowHits 112070 # Number of row buffer hits during reads +system.physmem.writeRowHits 62147 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.97 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.03 # Row buffer hit rate for writes +system.physmem.avgGap 275958.74 # Average gap between requests +system.physmem.pageHitRate 81.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 152069400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 82974375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512499000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 272270160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12264762105 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24475931250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41596065810 # Total energy per rank (pJ) +system.physmem_0.averagePower 708.329716 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 40585694500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1960920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15413376500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16178034500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139625640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76184625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 492086400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 271486080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11316053250 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24761537250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 40833031245 # Total energy per rank (pJ) -system.physmem_1.averagePower 706.292941 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 41066657000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1930500000 # Time in different power states +system.physmem_1.actEnergy 139308120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76011375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 492024000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 271453680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11655970470 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 25009959000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41480286165 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.358131 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 41477231750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1960920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14816189000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15286019500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14822198 # Number of BP lookups -system.cpu.branchPred.condPredicted 9914609 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 394622 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9489453 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6747157 # Number of BTB hits +system.cpu.branchPred.lookups 14827059 # Number of BP lookups +system.cpu.branchPred.condPredicted 9919255 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 395881 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9555564 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6751205 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.101643 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1719210 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 70.652083 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1718768 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -406,89 +404,89 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 115631110 # number of cpu cycles simulated +system.cpu.numCycles 117460251 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915127 # Number of instructions committed system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1144126 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1148249 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.630556 # CPI: cycles per instruction -system.cpu.ipc 0.613288 # IPC: instructions per cycle -system.cpu.tickCycles 96933125 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18697985 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156428 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.581764 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42664902 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160524 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.785191 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 784159000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.581764 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993306 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993306 # Average percentage of cache occupancy +system.cpu.cpi 1.656350 # CPI: cycles per instruction +system.cpu.ipc 0.603737 # IPC: instructions per cycle +system.cpu.tickCycles 97003390 # Number of cycles that the object actually ticked +system.cpu.idleCycles 20456861 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156434 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.721714 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42666461 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160530 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.784969 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 833735250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.721714 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993096 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993096 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 749 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3299 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 710 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3342 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86014590 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86014590 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22989229 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22989229 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19643835 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19643835 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 86017904 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86017904 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22990876 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22990876 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19643747 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19643747 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42633064 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42633064 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42633064 # number of overall hits -system.cpu.dcache.overall_hits::total 42633064 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 56065 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56065 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 206066 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 206066 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 262131 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 262131 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 262131 # number of overall misses -system.cpu.dcache.overall_misses::total 262131 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2147242437 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2147242437 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15196521000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15196521000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17343763437 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17343763437 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17343763437 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17343763437 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23045294 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23045294 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42634623 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42634623 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42634623 # number of overall hits +system.cpu.dcache.overall_hits::total 42634623 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 56072 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 56072 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 206154 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 206154 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 262226 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 262226 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 262226 # number of overall misses +system.cpu.dcache.overall_misses::total 262226 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2301185937 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2301185937 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16676998250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16676998250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18978184187 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18978184187 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18978184187 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18978184187 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23046948 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23046948 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42895195 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42895195 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42895195 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42895195 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 42896849 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42896849 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42896849 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42896849 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002433 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002433 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010381 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006111 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006111 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006111 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006111 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38299.160564 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38299.160564 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73745.892093 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73745.892093 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66164.488126 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66164.488126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66164.488126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66164.488126 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010386 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010386 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006113 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006113 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006113 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006113 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41039.840509 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41039.840509 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80895.826664 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80895.826664 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72373.388554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72373.388554 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -497,32 +495,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128441 # number of writebacks -system.cpu.dcache.writebacks::total 128441 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2577 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2577 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99030 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 99030 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 101607 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 101607 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 101607 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 101607 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53488 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53488 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107036 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107036 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 160524 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 160524 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160524 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160524 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1987609313 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1987609313 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7609976000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7609976000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9597585313 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9597585313 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9597585313 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9597585313 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 128445 # number of writebacks +system.cpu.dcache.writebacks::total 128445 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2576 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2576 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99120 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 99120 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 101696 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 101696 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 101696 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 101696 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53496 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53496 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 160530 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 160530 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160530 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160530 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2163468813 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2163468813 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402400750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402400750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10565869563 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10565869563 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10565869563 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10565869563 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -531,68 +529,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003742 system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37159.910877 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37159.910877 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71097.350424 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71097.350424 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59789.098907 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59789.098907 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40441.693080 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40441.693080 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78502.165200 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78502.165200 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42682 # number of replacements -system.cpu.icache.tags.tagsinuse 1858.929385 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25083355 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44724 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 560.847755 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 42774 # number of replacements +system.cpu.icache.tags.tagsinuse 1856.910000 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25093452 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44816 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 559.921724 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1858.929385 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.907680 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.907680 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1856.910000 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.906694 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.906694 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 803 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1117 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 730 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1192 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50300884 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50300884 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25083355 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25083355 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25083355 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25083355 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25083355 # number of overall hits -system.cpu.icache.overall_hits::total 25083355 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44725 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44725 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44725 # 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average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20031.917026 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20031.917026 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20031.917026 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20031.917026 # average overall miss latency +system.cpu.icache.tags.tag_accesses 50321354 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50321354 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25093452 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25093452 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25093452 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25093452 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25093452 # number of overall hits +system.cpu.icache.overall_hits::total 25093452 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 44817 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 44817 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 44817 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 44817 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 44817 # number of overall misses +system.cpu.icache.overall_misses::total 44817 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 937886990 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 937886990 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 937886990 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 937886990 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 937886990 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 937886990 # 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miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001783 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20927.036392 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20927.036392 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20927.036392 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20927.036392 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20927.036392 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20927.036392 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,123 +599,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804564511 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 804564511 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001780 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17989.145020 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17989.145020 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17989.145020 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17989.145020 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17989.145020 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17989.145020 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44817 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 44817 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 44817 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 44817 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 44817 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 44817 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 868759010 # 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Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126852 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.785932 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 29885.598621 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 99802 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126851 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.786766 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26707.516998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1563.058609 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1666.382853 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.815049 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9129 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20264 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 591 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 2904221 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2904221 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 39738 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 31910 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 71648 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 128445 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 128445 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4754 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4754 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 39738 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 36664 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 76402 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 39738 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 36664 # number of overall hits +system.cpu.l2cache.overall_hits::total 76402 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 5079 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 21586 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 26665 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102281 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 5081 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 123865 # 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Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 333690 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 333792 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 333690 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 295286000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 333792 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 295341000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68043489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68175990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 268450687 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 268644937 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) system.membus.trans_dist::ReadReq 26591 # Transaction distribution system.membus.trans_dist::ReadResp 26591 # Transaction distribution system.membus.trans_dist::Writeback 83951 # Transaction distribution -system.membus.trans_dist::ReadExReq 102281 # Transaction distribution -system.membus.trans_dist::ReadExResp 102281 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341695 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 341695 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13620672 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 102280 # Transaction distribution +system.membus.trans_dist::ReadExResp 102280 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341693 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 341693 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13620608 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 212823 # Request fanout histogram +system.membus.snoop_fanout::samples 212822 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 212823 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 212822 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 212823 # Request fanout histogram -system.membus.reqLayer0.occupancy 929408000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1213401000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.1 # Layer utilization (%) +system.membus.snoop_fanout::total 212822 # Request fanout histogram +system.membus.reqLayer0.occupancy 579596500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 680391500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 6394c9beb..c55c80533 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033020 # Number of seconds simulated -sim_ticks 33019504000 # Number of ticks simulated -final_tick 33019504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033359 # Number of seconds simulated +sim_ticks 33359312000 # Number of ticks simulated +final_tick 33359312000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123822 # Simulator instruction rate (inst/s) -host_op_rate 158353 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57659893 # Simulator tick rate (ticks/s) -host_mem_usage 322352 # Number of bytes of host memory used -host_seconds 572.66 # Real time elapsed on the host +host_inst_rate 125450 # Simulator instruction rate (inst/s) +host_op_rate 160435 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59019201 # Simulator tick rate (ticks/s) +host_mem_usage 322444 # Number of bytes of host memory used +host_seconds 565.23 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 90682584 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 588736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2517376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6201600 # Number of bytes read from this memory -system.physmem.bytes_read::total 9307712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 588736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 588736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6262016 # Number of bytes written to this memory -system.physmem.bytes_written::total 6262016 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9199 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 39334 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96900 # Number of read requests responded to by this memory -system.physmem.num_reads::total 145433 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97844 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97844 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 17829947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 76239062 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 187816268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 281885276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 17829947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 17829947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 189645974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 189645974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 189645974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 17829947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 76239062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 187816268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 471531250 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 145433 # Number of read requests accepted -system.physmem.writeReqs 97844 # Number of write requests accepted -system.physmem.readBursts 145433 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97844 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9300480 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue -system.physmem.bytesWritten 6260352 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9307712 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6262016 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 593600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2515776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6204544 # Number of bytes read from this memory +system.physmem.bytes_read::total 9313920 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 593600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 593600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6264768 # Number of bytes written to this memory +system.physmem.bytes_written::total 6264768 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9275 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 39309 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96946 # Number of read requests responded to by this memory +system.physmem.num_reads::total 145530 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97887 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97887 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 17794132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75414505 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 185991366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 279200003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 17794132 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 17794132 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 187796679 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 187796679 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 187796679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 17794132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75414505 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 185991366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 466996681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 145530 # Number of read requests accepted +system.physmem.writeReqs 97887 # Number of write requests accepted +system.physmem.readBursts 145530 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97887 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9306560 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue +system.physmem.bytesWritten 6263296 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9313920 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6264768 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9146 # Per bank write bursts -system.physmem.perBankRdBursts::1 9381 # Per bank write bursts -system.physmem.perBankRdBursts::2 9349 # Per bank write bursts -system.physmem.perBankRdBursts::3 9489 # Per bank write bursts -system.physmem.perBankRdBursts::4 9691 # Per bank write bursts -system.physmem.perBankRdBursts::5 9742 # Per bank write bursts -system.physmem.perBankRdBursts::6 9065 # Per bank write bursts -system.physmem.perBankRdBursts::7 9033 # Per bank write bursts -system.physmem.perBankRdBursts::8 9160 # Per bank write bursts -system.physmem.perBankRdBursts::9 8585 # Per bank write bursts -system.physmem.perBankRdBursts::10 8818 # Per bank write bursts -system.physmem.perBankRdBursts::11 8754 # Per bank write bursts -system.physmem.perBankRdBursts::12 8666 # Per bank write bursts -system.physmem.perBankRdBursts::13 8713 # Per bank write bursts -system.physmem.perBankRdBursts::14 8726 # Per bank write bursts -system.physmem.perBankRdBursts::15 9002 # Per bank write bursts -system.physmem.perBankWrBursts::0 5993 # Per bank write bursts -system.physmem.perBankWrBursts::1 6194 # Per bank write bursts -system.physmem.perBankWrBursts::2 6159 # Per bank write bursts -system.physmem.perBankWrBursts::3 6198 # Per bank write bursts -system.physmem.perBankWrBursts::4 6133 # Per bank write bursts -system.physmem.perBankWrBursts::5 6325 # Per bank write bursts -system.physmem.perBankWrBursts::6 6074 # Per bank write bursts -system.physmem.perBankWrBursts::7 6046 # Per bank write bursts -system.physmem.perBankWrBursts::8 6012 # Per bank write bursts -system.physmem.perBankWrBursts::9 6139 # Per bank write bursts -system.physmem.perBankWrBursts::10 6243 # Per bank write bursts -system.physmem.perBankWrBursts::11 5934 # Per bank write bursts -system.physmem.perBankWrBursts::12 6049 # Per bank write bursts -system.physmem.perBankWrBursts::13 6103 # Per bank write bursts -system.physmem.perBankWrBursts::14 6164 # Per bank write bursts -system.physmem.perBankWrBursts::15 6052 # Per bank write bursts +system.physmem.perBankRdBursts::0 9160 # Per bank write bursts +system.physmem.perBankRdBursts::1 9419 # Per bank write bursts +system.physmem.perBankRdBursts::2 9305 # Per bank write bursts +system.physmem.perBankRdBursts::3 9483 # Per bank write bursts +system.physmem.perBankRdBursts::4 9789 # Per bank write bursts +system.physmem.perBankRdBursts::5 9711 # Per bank write bursts +system.physmem.perBankRdBursts::6 9074 # Per bank write bursts +system.physmem.perBankRdBursts::7 9074 # Per bank write bursts +system.physmem.perBankRdBursts::8 9205 # Per bank write bursts +system.physmem.perBankRdBursts::9 8628 # Per bank write bursts +system.physmem.perBankRdBursts::10 8849 # Per bank write bursts +system.physmem.perBankRdBursts::11 8741 # Per bank write bursts +system.physmem.perBankRdBursts::12 8642 # Per bank write bursts +system.physmem.perBankRdBursts::13 8695 # Per bank write bursts +system.physmem.perBankRdBursts::14 8691 # Per bank write bursts +system.physmem.perBankRdBursts::15 8949 # Per bank write bursts +system.physmem.perBankWrBursts::0 5976 # Per bank write bursts +system.physmem.perBankWrBursts::1 6255 # Per bank write bursts +system.physmem.perBankWrBursts::2 6149 # Per bank write bursts +system.physmem.perBankWrBursts::3 6169 # Per bank write bursts +system.physmem.perBankWrBursts::4 6151 # Per bank write bursts +system.physmem.perBankWrBursts::5 6334 # Per bank write bursts +system.physmem.perBankWrBursts::6 6086 # Per bank write bursts +system.physmem.perBankWrBursts::7 6007 # Per bank write bursts +system.physmem.perBankWrBursts::8 5979 # Per bank write bursts +system.physmem.perBankWrBursts::9 6153 # Per bank write bursts +system.physmem.perBankWrBursts::10 6241 # Per bank write bursts +system.physmem.perBankWrBursts::11 5938 # Per bank write bursts +system.physmem.perBankWrBursts::12 6061 # Per bank write bursts +system.physmem.perBankWrBursts::13 6105 # Per bank write bursts +system.physmem.perBankWrBursts::14 6219 # Per bank write bursts +system.physmem.perBankWrBursts::15 6041 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33019298500 # Total gap between requests +system.physmem.totGap 33359040500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 145433 # Read request sizes (log2) +system.physmem.readPktSize::6 145530 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97844 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 47136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 46826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17078 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97887 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 42093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 51689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6081 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4669 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see @@ -148,33 +148,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -197,102 +197,104 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88783 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 175.237151 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 110.501041 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 239.251674 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 52191 58.78% 58.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22671 25.54% 84.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4463 5.03% 89.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1678 1.89% 91.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 979 1.10% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 876 0.99% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 737 0.83% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 796 0.90% 95.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4392 4.95% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88783 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5909 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.589101 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 21.077809 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 187.247746 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5908 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 88927 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.072858 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 110.491943 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 238.713124 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52339 58.86% 58.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22656 25.48% 84.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4441 4.99% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1741 1.96% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1037 1.17% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 849 0.95% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 689 0.77% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 765 0.86% 95.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4410 4.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88927 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5911 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.598207 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 21.088924 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 187.219466 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5910 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5909 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5909 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.554070 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.510446 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.278697 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4738 80.18% 80.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 25 0.42% 80.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 725 12.27% 92.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 165 2.79% 95.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 107 1.81% 97.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 76 1.29% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 36 0.61% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 24 0.41% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.14% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 4 0.07% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5909 # Writes before turning the bus around for reads -system.physmem.totQLat 7598607995 # Total ticks spent queuing -system.physmem.totMemAccLat 10323357995 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 726600000 # Total ticks spent in databus transfers -system.physmem.avgQLat 52288.80 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5911 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5911 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.556251 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.512708 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.281856 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4715 79.77% 79.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 33 0.56% 80.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 741 12.54% 92.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 193 3.27% 96.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 104 1.76% 97.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 53 0.90% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 34 0.58% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 17 0.29% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 11 0.19% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 4 0.07% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5911 # Writes before turning the bus around for reads +system.physmem.totQLat 7478329771 # Total ticks spent queuing +system.physmem.totMemAccLat 10204861021 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 727075000 # Total ticks spent in databus transfers +system.physmem.avgQLat 51427.50 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 71038.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 281.67 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 189.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 281.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 189.65 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 70177.50 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 278.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 187.75 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 279.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 187.80 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.68 # Data bus utilization in percentage -system.physmem.busUtilRead 2.20 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.48 # Data bus utilization in percentage for writes +system.physmem.busUtil 3.65 # Data bus utilization in percentage +system.physmem.busUtilRead 2.18 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing -system.physmem.readRowHits 118226 # Number of row buffer hits during reads -system.physmem.writeRowHits 36119 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.91 # Row buffer hit rate for writes -system.physmem.avgGap 135727.17 # Average gap between requests -system.physmem.pageHitRate 63.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 342362160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 186804750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 583720800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 318193920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2156294400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11787255720 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 9468687000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 24843318750 # Total energy per rank (pJ) -system.physmem_0.averagePower 752.509165 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 15653624306 # Time in different power states -system.physmem_0.memoryStateTime::REF 1102400000 # Time in different power states +system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing +system.physmem.readRowHits 118188 # Number of row buffer hits during reads +system.physmem.writeRowHits 36158 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.28 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 36.94 # Row buffer hit rate for writes +system.physmem.avgGap 137044.83 # Average gap between requests +system.physmem.pageHitRate 63.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 343556640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 187456500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 584859600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 318226320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2178671040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11869125390 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 9602419500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25084314990 # Total energy per rank (pJ) +system.physmem_0.averagePower 752.005565 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 15876395968 # Time in different power states +system.physmem_0.memoryStateTime::REF 1113840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16257963444 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16366332782 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 328376160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179173500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 549010800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 315414000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2156294400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11313288180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 9884473500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 24726030540 # Total energy per rank (pJ) -system.physmem_1.averagePower 748.955517 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 16351310453 # Time in different power states -system.physmem_1.memoryStateTime::REF 1102400000 # Time in different power states +system.physmem_1.actEnergy 328413960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179194125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 548948400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 315725040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2178671040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11416289175 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 9999644250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 24966885990 # Total energy per rank (pJ) +system.physmem_1.averagePower 748.485148 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 16542747198 # Time in different power states +system.physmem_1.memoryStateTime::REF 1113840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15560341797 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15699981552 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17204705 # Number of BP lookups -system.cpu.branchPred.condPredicted 11516912 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 648025 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9345879 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7673903 # Number of BTB hits +system.cpu.branchPred.lookups 17207670 # Number of BP lookups +system.cpu.branchPred.condPredicted 11518844 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 648137 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9345275 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7675164 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.110019 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1872530 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101564 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.128819 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1873048 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101561 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,234 +413,234 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 66039009 # number of cpu cycles simulated +system.cpu.numCycles 66718625 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4981802 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88178088 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17204705 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9546433 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59635234 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1322107 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 10977 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22758925 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 68935 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 65294039 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.709071 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.292735 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 4981358 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88194612 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17207670 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9548212 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60206161 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1322349 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5969 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 25 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13195 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22764676 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 68972 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 65867882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.694526 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.296864 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19515211 29.89% 29.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8274054 12.67% 42.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9196195 14.08% 56.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28308579 43.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20086614 30.50% 30.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8263984 12.55% 43.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9201027 13.97% 57.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28316257 42.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 65294039 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.260523 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.335242 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8590503 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 19016582 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31530881 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5663983 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 492090 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3178633 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 170869 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101389113 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3042046 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 492090 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13367671 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5222790 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 763292 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32193949 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13254247 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99181436 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 981589 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3720885 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 53337 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4029509 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5185175 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103906436 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457606733 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115387380 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 65867882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.257914 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.321889 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8560400 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 19609685 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31575881 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5629864 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 492052 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3179520 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171002 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101414286 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3048471 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 492052 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13316863 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5341740 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 787564 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32235527 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13694136 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99203918 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 983561 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3871797 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 66642 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4317748 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5384160 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103925780 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457714134 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115415425 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10277210 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18665 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18651 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12765420 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24319642 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21987038 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1312197 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2209009 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98145273 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34526 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94858951 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 691771 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7393055 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20168064 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 740 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 65294039 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.452796 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.148580 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 10296554 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18659 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18650 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12695794 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24322207 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21994092 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1403605 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2365005 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98166864 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34522 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94891849 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 694587 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7414208 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20250811 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 736 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 65867882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.440639 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150059 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17159256 26.28% 26.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17193875 26.33% 52.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17194261 26.33% 78.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11711028 17.94% 96.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2034625 3.12% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 994 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17597825 26.72% 26.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17436284 26.47% 53.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17101122 25.96% 79.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11678255 17.73% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2053424 3.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 972 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 65294039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 65867882 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6670808 22.11% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 41 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11293243 37.42% 59.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12213472 40.47% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6717330 22.42% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 38 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11201861 37.39% 59.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12041280 40.19% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49494148 52.18% 52.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89879 0.09% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24035201 25.34% 77.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21239685 22.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49497025 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89873 0.09% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24063293 25.36% 77.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21241620 22.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94858951 # Type of FU issued -system.cpu.iq.rate 1.436408 # Inst issue rate -system.cpu.iq.fu_busy_cnt 30177564 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.318131 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 285881069 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105584154 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93463006 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 94891849 # Type of FU issued +system.cpu.iq.rate 1.422269 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29960509 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315733 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 286306469 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105626883 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93465742 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 125036397 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 124852240 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1353483 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 1363033 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1453380 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2068 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11797 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1431300 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1455945 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2039 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11790 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1438354 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 120407 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 169543 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 142055 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 176720 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 492090 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 617243 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 370435 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98189662 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 492052 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 623106 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 467581 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98211247 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24319642 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21987038 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18606 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1603 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 365951 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11797 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 302833 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221503 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 524336 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93942350 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23727911 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 916601 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24322207 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21994092 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18602 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1655 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 463043 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11790 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 303168 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221686 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 524854 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93974313 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23756309 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 917536 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9863 # number of nop insts executed -system.cpu.iew.exec_refs 44710370 # number of memory reference insts executed -system.cpu.iew.exec_branches 14251746 # Number of branches executed -system.cpu.iew.exec_stores 20982459 # Number of stores executed -system.cpu.iew.exec_rate 1.422528 # Inst execution rate -system.cpu.iew.wb_sent 93584307 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93463063 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44927637 # num instructions producing a value -system.cpu.iew.wb_consumers 76497349 # num instructions consuming a value +system.cpu.iew.exec_nop 9861 # number of nop insts executed +system.cpu.iew.exec_refs 44740784 # number of memory reference insts executed +system.cpu.iew.exec_branches 14252664 # Number of branches executed +system.cpu.iew.exec_stores 20984475 # Number of stores executed +system.cpu.iew.exec_rate 1.408517 # Inst execution rate +system.cpu.iew.wb_sent 93587501 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93465799 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44986533 # num instructions producing a value +system.cpu.iew.wb_consumers 76576760 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.415271 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587310 # average fanout of values written-back +system.cpu.iew.wb_rate 1.400895 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587470 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6519180 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6538748 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 479062 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 64238392 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.411744 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.175817 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 479015 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 64808930 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.399315 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.164562 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 30786432 47.93% 47.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16709618 26.01% 73.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4274980 6.65% 80.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4124415 6.42% 87.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1949899 3.04% 90.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1296449 2.02% 92.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 706597 1.10% 93.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 586126 0.91% 94.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3803876 5.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31222194 48.18% 48.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16795938 25.92% 74.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4338232 6.69% 80.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4159188 6.42% 87.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1936724 2.99% 90.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1268170 1.96% 92.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 738929 1.14% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 579590 0.89% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3769965 5.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 64238392 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 64808930 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -684,381 +686,381 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction -system.cpu.commit.bw_lim_events 3803876 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3769965 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 157616533 # The number of ROB reads -system.cpu.rob.rob_writes 195472136 # The number of ROB writes -system.cpu.timesIdled 23660 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 744970 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 158240550 # The number of ROB reads +system.cpu.rob.rob_writes 195514428 # The number of ROB writes +system.cpu.timesIdled 23835 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 850743 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.931339 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.931339 # CPI: Total CPI of All Threads -system.cpu.ipc 1.073723 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.073723 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102238235 # number of integer regfile reads -system.cpu.int_regfile_writes 56792997 # number of integer regfile writes +system.cpu.cpi 0.940923 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.940923 # CPI: Total CPI of All Threads +system.cpu.ipc 1.062786 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.062786 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102271067 # number of integer regfile reads +system.cpu.int_regfile_writes 56793819 # number of integer regfile writes system.cpu.fp_regfile_reads 36 # number of floating regfile reads system.cpu.fp_regfile_writes 21 # number of floating regfile writes -system.cpu.cc_regfile_reads 345997909 # number of cc regfile reads -system.cpu.cc_regfile_writes 38804494 # number of cc regfile writes -system.cpu.misc_regfile_reads 44208348 # number of misc regfile reads +system.cpu.cc_regfile_reads 346093039 # number of cc regfile reads +system.cpu.cc_regfile_writes 38805147 # number of cc regfile writes +system.cpu.misc_regfile_reads 44210055 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.replacements 485280 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.769602 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40441610 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485792 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.248818 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 148406000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.769602 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997597 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997597 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 485079 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.744077 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40428139 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485591 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.255536 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 152734000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.744077 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997547 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997547 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84635072 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84635072 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21513403 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21513403 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18834640 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18834640 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 62245 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 62245 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 84616103 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84616103 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21501727 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21501727 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18833421 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18833421 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 61667 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 61667 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15379 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15379 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40348043 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40348043 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40410288 # number of overall hits -system.cpu.dcache.overall_hits::total 40410288 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 550665 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 550665 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1015261 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1015261 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 66581 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 66581 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 40335148 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40335148 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40396815 # number of overall hits +system.cpu.dcache.overall_hits::total 40396815 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 552941 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 552941 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1016480 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1016480 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 67175 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 67175 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 547 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 547 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1565926 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1565926 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1632507 # number of overall misses -system.cpu.dcache.overall_misses::total 1632507 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8659099753 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8659099753 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14372727937 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14372727937 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4891750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4891750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23031827690 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23031827690 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23031827690 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23031827690 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22064068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22064068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1569421 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1569421 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1636596 # number of overall misses +system.cpu.dcache.overall_misses::total 1636596 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9116754245 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9116754245 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14723087903 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14723087903 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5168250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5168250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23839842148 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23839842148 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23839842148 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23839842148 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22054668 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22054668 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128826 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128826 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128842 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128842 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41913969 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41913969 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42042795 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42042795 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024958 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.024958 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051147 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051147 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.516829 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.516829 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41904569 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41904569 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42033411 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42033411 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025071 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025071 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051208 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051208 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.521375 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.521375 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034346 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034346 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037360 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037360 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038830 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038830 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15724.805014 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15724.805014 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14156.682801 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14156.682801 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8942.870201 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8942.870201 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14708.120109 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14708.120109 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14108.256620 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14108.256620 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2883834 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 127457 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.625937 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.037452 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037452 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038936 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038936 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16487.752301 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16487.752301 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14484.385234 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14484.385234 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9448.354662 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9448.354662 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15190.214830 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15190.214830 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14566.723949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14566.723949 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 97 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3023244 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 128456 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.818182 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 23.535249 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 264417 # number of writebacks -system.cpu.dcache.writebacks::total 264417 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 250985 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 250985 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866735 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 866735 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 262833 # number of writebacks +system.cpu.dcache.writebacks::total 262833 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 253459 # 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number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1121414 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1121414 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299482 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299482 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148525 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148525 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37595 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37595 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 448007 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 448007 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485602 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485602 # 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number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013579 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013579 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291843 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291843 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010693 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010693 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011555 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011555 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9454.643633 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9454.643633 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14503.938354 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14503.938354 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51461.030322 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51461.030322 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11127.873237 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11127.873237 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14249.314864 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14249.314864 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291791 # 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average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54214.369411 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11905.354503 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11905.354503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15180.891703 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15180.891703 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 322868 # number of replacements -system.cpu.icache.tags.tagsinuse 510.284584 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22426703 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 323380 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 69.350928 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 9934.445695 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 9934.445695 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 9934.445695 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 226617 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 46 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 14091 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 45852448 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45852448 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22431720 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22431720 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22431720 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22431720 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22431720 # 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miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014621 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014621 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10165.898051 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10165.898051 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10165.898051 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10165.898051 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10165.898051 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10165.898051 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 260603 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 49 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 14904 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.082393 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 23 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 17.485440 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 24.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8733 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 8733 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 8733 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 8733 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 8733 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2699093031 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2699093031 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014209 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014209 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014209 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014209 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014209 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014209 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8346.221852 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8346.221852 # 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number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 262833 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 11 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 11 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 148567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 148567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 323376 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 485792 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 809168 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 323376 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 485792 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 809168 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1067,145 +1069,143 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97844 # number of writebacks -system.cpu.l2cache.writebacks::total 97844 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 33 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 152 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 185 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3161 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3161 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 33 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.092170 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.060976 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8270 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 8270 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 9275 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 39309 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 48584 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 9275 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 39309 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112789 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 161373 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 645635507 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2465712994 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3111348501 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10913543372 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10913543372 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 83006 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 83006 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 614828776 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 614828776 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 645635507 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3080541770 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3726177277 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 645635507 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3080541770 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10913543372 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14639720649 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.028687 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.092096 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.061050 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.545455 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.545455 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055463 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055463 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.080944 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059964 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.080944 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055667 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055667 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028687 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.080951 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060062 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028687 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.080951 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.199118 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61887.244483 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74114.210894 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71321.930066 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 101210.121999 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 101210.121999 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6501 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6501 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65413.264199 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65413.264199 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61887.244483 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72290.910940 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70318.500484 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61887.244483 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72290.910940 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 101210.121999 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91907.165398 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.199496 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69610.297251 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 79439.189214 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77177.866275 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96760.706913 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96760.706913 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13834.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13834.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74344.471100 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74344.471100 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69610.297251 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78367.340049 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76695.563910 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69610.297251 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78367.340049 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96760.706913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90719.765072 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 660616 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 660616 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 264417 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 169278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 660352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 660352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 262833 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 151427 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646767 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1236023 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1882790 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20696064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 48013376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 68709440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 169293 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1242889 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.136197 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.342998 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 148563 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148563 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646637 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234037 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1880674 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20692032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47899136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 68591168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 151438 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1223186 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.123797 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.329350 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 1073611 86.38% 86.38% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 169278 13.62% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 1071759 87.62% 87.62% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 151427 12.38% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1242889 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 801222500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1223186 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 798712500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 486660171 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 486658187 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 734282302 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 734620345 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 137181 # Transaction distribution -system.membus.trans_dist::ReadResp 137181 # Transaction distribution -system.membus.trans_dist::Writeback 97844 # Transaction distribution +system.membus.trans_dist::ReadReq 137260 # Transaction distribution +system.membus.trans_dist::ReadResp 137260 # Transaction distribution +system.membus.trans_dist::Writeback 97887 # Transaction distribution system.membus.trans_dist::UpgradeReq 6 # Transaction distribution system.membus.trans_dist::UpgradeResp 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 8252 # Transaction distribution -system.membus.trans_dist::ReadExResp 8252 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 388722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 388722 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15569728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15569728 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 8270 # Transaction distribution +system.membus.trans_dist::ReadExResp 8270 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 388959 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 388959 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15578688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15578688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 243283 # Request fanout histogram +system.membus.snoop_fanout::samples 243423 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 243283 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 243423 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 243283 # Request fanout histogram -system.membus.reqLayer0.occupancy 1077095188 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1335208239 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 4.0 # Layer utilization (%) +system.membus.snoop_fanout::total 243423 # Request fanout histogram +system.membus.reqLayer0.occupancy 692237323 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 758965490 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 23c0d1c87..93e5e3e06 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.048960 # Nu sim_ticks 48960011000 # Number of ticks simulated final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1376675 # Simulator instruction rate (inst/s) -host_op_rate 1760576 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 950486092 # Simulator tick rate (ticks/s) -host_mem_usage 308184 # Number of bytes of host memory used -host_seconds 51.51 # Real time elapsed on the host +host_inst_rate 1566427 # Simulator instruction rate (inst/s) +host_op_rate 2003243 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1081494789 # Simulator tick rate (ticks/s) +host_mem_usage 308080 # Number of bytes of host memory used +host_seconds 45.27 # Real time elapsed on the host sim_insts 70913181 # Number of instructions simulated sim_ops 90688136 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 120930618 # Request fanout histogram -system.membus.snoop_fanout::mean 4.646198 # Request fanout histogram +system.membus.snoop_fanout::mean 2.646198 # Request fanout histogram system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 42785550 35.38% 35.38% # Request fanout histogram -system.membus.snoop_fanout::5 78145068 64.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 42785550 35.38% 35.38% # Request fanout histogram +system.membus.snoop_fanout::3 78145068 64.62% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 120930618 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 938385651..6d597c67f 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.127294 # Number of seconds simulated -sim_ticks 127293983000 # Number of ticks simulated -final_tick 127293983000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.127293 # Number of seconds simulated +sim_ticks 127293405500 # Number of ticks simulated +final_tick 127293405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 894668 # Simulator instruction rate (inst/s) -host_op_rate 1142240 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1618302823 # Simulator tick rate (ticks/s) -host_mem_usage 317432 # Number of bytes of host memory used -host_seconds 78.66 # Real time elapsed on the host +host_inst_rate 802256 # Simulator instruction rate (inst/s) +host_op_rate 1024256 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1451138855 # Simulator tick rate (ticks/s) +host_mem_usage 317568 # Number of bytes of host memory used +host_seconds 87.72 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 89847362 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 123820 # Nu system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2007071 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 62253375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64260445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2007071 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2007071 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 42187194 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 42187194 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 42187194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2007071 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 62253375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106447639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2007080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 62253657 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64260737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2007080 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2007080 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 42187386 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 42187386 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 42187386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2007080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 62253657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106448122 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 254587966 # number of cpu cycles simulated +system.cpu.numCycles 254586811 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373628 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 43422001 # nu system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 254587965.998000 # Number of busy cycles +system.cpu.num_busy_cycles 254586810.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 13741485 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690083 # Class of executed instruction system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.389354 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42608166 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4076.389361 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42608169 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 266.304366 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1061073000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389354 # Average occupied blocks per requestor +system.cpu.dcache.tags.avg_refs 266.304385 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1061070000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389361 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -230,8 +230,8 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22749836 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22749836 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 22749839 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22749839 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits @@ -240,28 +240,28 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42492705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42492705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42576328 # number of overall hits -system.cpu.dcache.overall_hits::total 42576328 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 30231 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 30231 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 42492708 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42492708 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42576331 # number of overall hits +system.cpu.dcache.overall_hits::total 42576331 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 30228 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 30228 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 137263 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 137263 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 177384 # number of overall misses -system.cpu.dcache.overall_misses::total 177384 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 516746500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 516746500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689859500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5689859500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6206606000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6206606000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6206606000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6206606000 # number of overall miss cycles +system.cpu.dcache.demand_misses::cpu.data 137260 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 137260 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 177381 # number of overall misses +system.cpu.dcache.overall_misses::total 177381 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 517066000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 517066000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689116000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5689116000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6206182000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6206182000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6206182000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6206182000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17093.265191 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17093.265191 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53160.358584 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53160.358584 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45216.890203 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45216.890203 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34989.660849 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34989.660849 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17105.531295 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17105.531295 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.412064 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.412064 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45214.789451 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45214.789451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34987.862285 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34987.862285 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,12 +304,12 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks system.cpu.dcache.writebacks::total 128239 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1123 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1123 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1123 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1123 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1123 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1120 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1120 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1120 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1120 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1120 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1120 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses @@ -320,16 +320,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136140 system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 443576500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 443576500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475795500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475795500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1053888500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1053888500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5919372000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5919372000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6973260500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6973260500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 457995500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 457995500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5528568000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5528568000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1058278000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1058278000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5986563500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5986563500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7044841500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7044841500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -340,26 +340,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15238.989281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15238.989281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51160.358584 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51160.358584 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44173.379998 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44173.379998 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43480.035258 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15734.351381 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15734.351381 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51653.412064 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51653.412064 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44357.364406 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44357.364406 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43973.582342 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43973.582342 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44030.809760 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44030.809760 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1733.675052 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1733.672975 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1733.675052 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.846521 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.846521 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672975 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id @@ -380,12 +380,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 414091500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 414091500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 414091500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 414091500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 414091500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 414091500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 413935000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 413935000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 413935000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 413935000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 413935000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 413935000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses @@ -398,12 +398,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21900.333192 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21900.333192 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21900.333192 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21900.333192 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21900.333192 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21900.333192 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21892.056272 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21892.056272 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21892.056272 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21892.056272 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -418,43 +418,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 376275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 376275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 376275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 376275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 376275500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 376275500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 385573000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 385573000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 385573000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 385573000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 385573000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 385573000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19900.333192 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19900.333192 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19900.333192 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19900.333192 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19900.333192 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19900.333192 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20392.056272 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20392.056272 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20392.056272 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20392.056272 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 94693 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30351.010864 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30351.006010 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27796.806295 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.765897 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.438673 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.848291 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 27796.868072 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.768401 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.369537 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.848293 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035149 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.042799 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.042797 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.926239 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15086 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13934 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15103 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13917 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 607 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2689980 # Number of tag accesses @@ -483,17 +483,17 @@ system.cpu.l2cache.demand_misses::total 127812 # nu system.cpu.l2cache.overall_misses::cpu.inst 3992 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses system.cpu.l2cache.overall_misses::total 127812 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 208207500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1130236000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1338443500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5321243500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5321243500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 208207500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6451479500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6659687000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 208207500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6451479500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6659687000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210047000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1133331500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1343378500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371640000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5371640000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 210047000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6504971500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6715018500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 210047000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6504971500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6715018500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses) @@ -518,17 +518,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.714409 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.211128 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.714409 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52156.187375 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52471.494893 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52422.195676 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52026.236801 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52026.236801 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52156.187375 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52103.694880 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52105.334397 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52156.187375 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52103.694880 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52105.334397 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52616.983968 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52615.204271 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52615.482532 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52518.967540 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52518.967540 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52616.983968 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52535.709094 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52538.247582 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52616.983968 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52535.709094 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52538.247582 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -550,17 +550,17 @@ system.cpu.l2cache.demand_mshr_misses::total 127812 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159943500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 868345500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028289000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4091943000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4091943000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159943500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4960288500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5120232000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159943500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4960288500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5120232000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 161778000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 873989500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1035767500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4142346500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4142346500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161778000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5016336000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5178114000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161778000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5016336000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5178114000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses @@ -572,17 +572,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40066.007014 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40313.161560 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40274.518252 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.264372 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.264372 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40066.007014 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40060.478921 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40060.651582 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40066.007014 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40060.478921 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40060.651582 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40525.551102 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40575.185701 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40567.425192 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.063551 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.063551 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution @@ -597,19 +597,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 307145 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 307145 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) @@ -627,19 +625,19 @@ system.membus.pkt_count::total 339533 # Pa system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 214631 # Request fanout histogram +system.membus.snoop_fanout::samples 214640 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 214631 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 214640 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 214631 # Request fanout histogram -system.membus.reqLayer0.occupancy 895030780 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 1156019000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.snoop_fanout::total 214640 # Request fanout histogram +system.membus.reqLayer0.occupancy 566253984 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 642220500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 3c1945f38..718e317fa 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.202242 # Number of seconds simulated -sim_ticks 202242260000 # Number of ticks simulated -final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 202242028500 # Number of ticks simulated +final_tick 202242028500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1318449 # Simulator instruction rate (inst/s) -host_op_rate 1335520 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1983988186 # Simulator tick rate (ticks/s) -host_mem_usage 297988 # Number of bytes of host memory used -host_seconds 101.94 # Real time elapsed on the host +host_inst_rate 1201078 # Simulator instruction rate (inst/s) +host_op_rate 1216630 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1807368744 # Simulator tick rate (ticks/s) +host_mem_usage 300888 # Number of bytes of host memory used +host_seconds 111.90 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,44 +25,20 @@ system.physmem.num_reads::cpu.data 122291 # Nu system.physmem.num_reads::total 131533 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 82868 # Number of write requests responded to by this memory system.physmem.num_writes::total 82868 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2924651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38699251 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 41623902 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2924651 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2924651 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26223758 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26223758 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26223758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2924651 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 38699251 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 67847660 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 30277 # Transaction distribution -system.membus.trans_dist::ReadResp 30277 # Transaction distribution -system.membus.trans_dist::Writeback 82868 # Transaction distribution -system.membus.trans_dist::ReadExReq 101256 # Transaction distribution -system.membus.trans_dist::ReadExResp 101256 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 214401 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 214401 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 214401 # Request fanout histogram -system.membus.reqLayer0.occupancy 877345000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 1183797000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.6 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 2924654 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38699295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 41623950 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2924654 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2924654 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26223788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26223788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26223788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2924654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38699295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 67847737 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 404484520 # number of cpu cycles simulated +system.cpu.numCycles 404484057 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 134398962 # Number of instructions committed @@ -81,7 +57,7 @@ system.cpu.num_mem_refs 58160248 # nu system.cpu.num_load_insts 37275867 # Number of load instructions system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 404484519.998000 # Number of busy cycles +system.cpu.num_busy_cycles 404484056.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 12719095 # Number of branches fetched @@ -120,13 +96,140 @@ system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 136293798 # Class of executed instruction +system.cpu.dcache.tags.replacements 146582 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.648320 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 769041000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648320 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 529 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3530 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits +system.cpu.dcache.overall_hits::total 57944941 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses +system.cpu.dcache.overall_misses::total 150663 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475000000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1475000000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5619674000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5619674000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7094674000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7094674000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7094674000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7094674000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32418.294908 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32418.294908 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.240881 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.240881 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47089.690236 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47089.690236 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47089.690236 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47089.690236 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks +system.cpu.dcache.writebacks::total 123970 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1406751500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1406751500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5461928000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5461928000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 382500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 382500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6868679500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6868679500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6868679500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6868679500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30918.294908 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30918.294908 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51937.240881 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51937.240881 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25500 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45589.690236 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45589.690236 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45589.690236 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45589.690236 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 184976 # number of replacements -system.cpu.icache.tags.tagsinuse 2004.815325 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 2004.815289 # Cycle average of tags in use system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor +system.cpu.icache.tags.warmup_cycle 143972077000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815289 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.978914 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id @@ -150,12 +253,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2819681000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2819681000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2819681000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2819681000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2819681000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2819681000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2819561500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2819561500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2819561500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2819561500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2819561500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2819561500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses @@ -168,12 +271,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15076.573060 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15076.573060 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15076.573060 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15076.573060 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15076.573060 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15076.573060 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15075.934105 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15075.934105 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15075.934105 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15075.934105 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15075.934105 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15075.934105 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -188,34 +291,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024 system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2445633000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2445633000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2445633000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2445633000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2445633000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2445633000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2539025500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2539025500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2539025500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2539025500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2539025500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2539025500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13076.573060 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13076.573060 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13575.934105 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13575.934105 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13575.934105 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13575.934105 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13575.934105 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13575.934105 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 98540 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30850.759699 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30850.758845 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 226933 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 129534 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.751918 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26245.550341 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.944777 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264582 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 26245.549112 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.945467 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264265 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy @@ -253,17 +356,17 @@ system.cpu.l2cache.demand_misses::total 131533 # nu system.cpu.l2cache.overall_misses::cpu.inst 9242 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 122291 # number of overall misses system.cpu.l2cache.overall_misses::total 131533 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 480789000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1093974000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1574763000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5265313000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5265313000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 480789000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6359287000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6840076000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 480789000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6359287000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6840076000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 485290500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1104380500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1589671000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5315940000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5315940000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 485290500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6420320500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6905611000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 485290500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6420320500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6905611000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187024 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 45499 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 232523 # number of ReadReq accesses(hits+misses) @@ -288,17 +391,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.389494 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.049416 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.811605 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.389494 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.181346 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52007.321131 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52011.857185 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.009876 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.009876 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.181346 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.267469 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52002.736956 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.181346 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.267469 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52002.736956 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52509.251244 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52502.044212 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52504.244146 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52509.251244 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.351620 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.976941 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52509.251244 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.351620 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.976941 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -320,17 +423,17 @@ system.cpu.l2cache.demand_mshr_misses::total 131533 system.cpu.l2cache.overall_mshr_misses::cpu.inst 9242 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122291 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 131533 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 369885000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 841554000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1211439000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4050241000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4050241000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 369885000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4891795000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5261680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 369885000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4891795000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5261680000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 374386000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 851960500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1226346500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4100868000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4100868000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 374386000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4952828500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5327214500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 374386000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4952828500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5327214500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.462318 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.130211 # mshr miss rate for ReadReq accesses @@ -342,145 +445,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.389494 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.389494 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40022.181346 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40007.321131 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40011.857185 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.009876 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.009876 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.181346 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.181346 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40509.197143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40502.044212 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40504.227632 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40509.197143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.351620 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.973140 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40509.197143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.351620 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.973140 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 146582 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.648350 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 769040000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 529 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3530 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits -system.cpu.dcache.overall_hits::total 57944941 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses -system.cpu.dcache.overall_misses::total 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475111000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1475111000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5619675000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5619675000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7094786000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7094786000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7094786000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7094786000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32420.734522 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32420.734522 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.250390 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.250390 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47090.433617 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47090.433617 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks -system.cpu.dcache.writebacks::total 123970 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1384113000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1384113000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5409347000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5409347000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 375000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 375000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793460000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6793460000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6793460000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6793460000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30420.734522 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30420.734522 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51437.250390 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51437.250390 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 232523 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution @@ -510,5 +486,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 280536000 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 30277 # Transaction distribution +system.membus.trans_dist::ReadResp 30277 # Transaction distribution +system.membus.trans_dist::Writeback 82868 # Transaction distribution +system.membus.trans_dist::ReadExReq 101256 # Transaction distribution +system.membus.trans_dist::ReadExResp 101256 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 214401 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 214401 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 214401 # Request fanout histogram +system.membus.reqLayer0.occupancy 558284500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 657665500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 0dacf1436..520a2b090 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.199774 # Number of seconds simulated -sim_ticks 1199774280000 # Number of ticks simulated -final_tick 1199774280000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.211624 # Number of seconds simulated +sim_ticks 1211624479500 # Number of ticks simulated +final_tick 1211624479500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 216625 # Simulator instruction rate (inst/s) -host_op_rate 216625 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 142303871 # Simulator tick rate (ticks/s) -host_mem_usage 282608 # Number of bytes of host memory used -host_seconds 8431.08 # Real time elapsed on the host +host_inst_rate 333436 # Simulator instruction rate (inst/s) +host_op_rate 333436 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 221202175 # Simulator tick rate (ticks/s) +host_mem_usage 295444 # Number of bytes of host memory used +host_seconds 5477.45 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125444608 # Number of bytes read from this memory -system.physmem.bytes_read::total 125505984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65167488 # Number of bytes written to this memory -system.physmem.bytes_written::total 65167488 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 959 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1960072 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961031 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018242 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018242 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 51156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 104556840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 104607997 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 51156 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 51156 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54316457 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54316457 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54316457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 51156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 104556840 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 158924454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961031 # Number of read requests accepted -system.physmem.writeReqs 1018242 # Number of write requests accepted -system.physmem.readBursts 1961031 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1018242 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125423808 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 82176 # Total number of bytes read from write queue -system.physmem.bytesWritten 65166208 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125505984 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65167488 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1284 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125444544 # Number of bytes read from this memory +system.physmem.bytes_read::total 125505792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65167616 # Number of bytes written to this memory +system.physmem.bytes_written::total 65167616 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 957 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1960071 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961028 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018244 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018244 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 50550 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 103534178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 103584728 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 50550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 50550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 53785325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 53785325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 53785325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 50550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 103534178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 157370053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961028 # Number of read requests accepted +system.physmem.writeReqs 1018244 # Number of write requests accepted +system.physmem.readBursts 1961028 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1018244 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125424064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 81728 # Total number of bytes read from write queue +system.physmem.bytesWritten 65166336 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125505792 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65167616 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1277 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118757 # Per bank write bursts -system.physmem.perBankRdBursts::1 114096 # Per bank write bursts -system.physmem.perBankRdBursts::2 116226 # Per bank write bursts -system.physmem.perBankRdBursts::3 117770 # Per bank write bursts -system.physmem.perBankRdBursts::4 117824 # Per bank write bursts -system.physmem.perBankRdBursts::5 117523 # Per bank write bursts -system.physmem.perBankRdBursts::6 119882 # Per bank write bursts -system.physmem.perBankRdBursts::7 124516 # Per bank write bursts -system.physmem.perBankRdBursts::8 126973 # Per bank write bursts -system.physmem.perBankRdBursts::9 130090 # Per bank write bursts -system.physmem.perBankRdBursts::10 128654 # Per bank write bursts -system.physmem.perBankRdBursts::11 130347 # Per bank write bursts -system.physmem.perBankRdBursts::12 126055 # Per bank write bursts -system.physmem.perBankRdBursts::13 125249 # Per bank write bursts -system.physmem.perBankRdBursts::14 122591 # Per bank write bursts -system.physmem.perBankRdBursts::15 123194 # Per bank write bursts -system.physmem.perBankWrBursts::0 61222 # Per bank write bursts -system.physmem.perBankWrBursts::1 61485 # Per bank write bursts -system.physmem.perBankWrBursts::2 60564 # Per bank write bursts +system.physmem.perBankRdBursts::0 118746 # Per bank write bursts +system.physmem.perBankRdBursts::1 114093 # Per bank write bursts +system.physmem.perBankRdBursts::2 116238 # Per bank write bursts +system.physmem.perBankRdBursts::3 117765 # Per bank write bursts +system.physmem.perBankRdBursts::4 117832 # Per bank write bursts +system.physmem.perBankRdBursts::5 117522 # Per bank write bursts +system.physmem.perBankRdBursts::6 119888 # Per bank write bursts +system.physmem.perBankRdBursts::7 124523 # Per bank write bursts +system.physmem.perBankRdBursts::8 126979 # Per bank write bursts +system.physmem.perBankRdBursts::9 130092 # Per bank write bursts +system.physmem.perBankRdBursts::10 128645 # Per bank write bursts +system.physmem.perBankRdBursts::11 130343 # Per bank write bursts +system.physmem.perBankRdBursts::12 126054 # Per bank write bursts +system.physmem.perBankRdBursts::13 125251 # Per bank write bursts +system.physmem.perBankRdBursts::14 122593 # Per bank write bursts +system.physmem.perBankRdBursts::15 123187 # Per bank write bursts +system.physmem.perBankWrBursts::0 61219 # Per bank write bursts +system.physmem.perBankWrBursts::1 61484 # Per bank write bursts +system.physmem.perBankWrBursts::2 60571 # Per bank write bursts system.physmem.perBankWrBursts::3 61239 # Per bank write bursts -system.physmem.perBankWrBursts::4 61658 # Per bank write bursts -system.physmem.perBankWrBursts::5 63101 # Per bank write bursts -system.physmem.perBankWrBursts::6 64148 # Per bank write bursts -system.physmem.perBankWrBursts::7 65617 # Per bank write bursts -system.physmem.perBankWrBursts::8 65332 # Per bank write bursts -system.physmem.perBankWrBursts::9 65778 # Per bank write bursts -system.physmem.perBankWrBursts::10 65295 # Per bank write bursts -system.physmem.perBankWrBursts::11 65646 # Per bank write bursts -system.physmem.perBankWrBursts::12 64171 # Per bank write bursts -system.physmem.perBankWrBursts::13 64211 # Per bank write bursts -system.physmem.perBankWrBursts::14 64568 # Per bank write bursts +system.physmem.perBankWrBursts::4 61659 # Per bank write bursts +system.physmem.perBankWrBursts::5 63100 # Per bank write bursts +system.physmem.perBankWrBursts::6 64152 # Per bank write bursts +system.physmem.perBankWrBursts::7 65616 # Per bank write bursts +system.physmem.perBankWrBursts::8 65335 # Per bank write bursts +system.physmem.perBankWrBursts::9 65774 # Per bank write bursts +system.physmem.perBankWrBursts::10 65298 # Per bank write bursts +system.physmem.perBankWrBursts::11 65641 # Per bank write bursts +system.physmem.perBankWrBursts::12 64170 # Per bank write bursts +system.physmem.perBankWrBursts::13 64210 # Per bank write bursts +system.physmem.perBankWrBursts::14 64569 # Per bank write bursts system.physmem.perBankWrBursts::15 64187 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1199774169500 # Total gap between requests +system.physmem.totGap 1211624362000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961031 # Read request sizes (log2) +system.physmem.readPktSize::6 1961028 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1018242 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1834284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 125445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1018244 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1838105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,35 +144,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 59999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 59968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 60029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 60015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 59979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 59955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 59970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 60003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -193,129 +193,130 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1838370 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.671596 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.054008 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 129.842659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1459678 79.40% 79.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 262161 14.26% 93.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49287 2.68% 96.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20645 1.12% 97.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12893 0.70% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7143 0.39% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5357 0.29% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4451 0.24% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16755 0.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1838370 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59429 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.975652 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 161.968947 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59388 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1839318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.618163 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.033976 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 129.636069 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1460921 79.43% 79.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 261839 14.24% 93.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49211 2.68% 96.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20654 1.12% 97.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12987 0.71% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7330 0.40% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5324 0.29% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4553 0.25% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16499 0.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1839318 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59419 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.981269 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 162.030420 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59379 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59429 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59429 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.133420 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.097680 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.110939 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27565 46.38% 46.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1269 2.14% 48.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 26249 44.17% 92.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3908 6.58% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 362 0.61% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 56 0.09% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 12 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59429 # Writes before turning the bus around for reads -system.physmem.totQLat 36751953000 # Total ticks spent queuing -system.physmem.totMemAccLat 73497209250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9798735000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18753.42 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59419 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59419 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.136337 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.100269 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.116106 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27590 46.43% 46.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1250 2.10% 48.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 26098 43.92% 92.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3967 6.68% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 431 0.73% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 63 0.11% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 13 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59419 # Writes before turning the bus around for reads +system.physmem.totQLat 36831870500 # Total ticks spent queuing +system.physmem.totMemAccLat 73577201750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9798755000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18794.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37503.42 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 104.54 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 54.32 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 104.61 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 54.32 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37544.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 103.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 53.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 103.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 53.79 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.24 # Data bus utilization in percentage -system.physmem.busUtilRead 0.82 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.23 # Data bus utilization in percentage +system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing -system.physmem.readRowHits 726418 # Number of row buffer hits during reads -system.physmem.writeRowHits 413172 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.58 # Row buffer hit rate for writes -system.physmem.avgGap 402707.03 # Average gap between requests -system.physmem.pageHitRate 38.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6745500720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3680580750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7383386400 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing +system.physmem.readRowHits 725319 # Number of row buffer hits during reads +system.physmem.writeRowHits 413326 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.59 # Row buffer hit rate for writes +system.physmem.avgGap 406684.71 # Average gap between requests +system.physmem.pageHitRate 38.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6747405840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3681620250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7383487800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 3233733840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 78362993280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 409753789290 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 360427621500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 869587605780 # Total energy per rank (pJ) -system.physmem_0.averagePower 724.796496 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 596865139750 # Time in different power states -system.physmem_0.memoryStateTime::REF 40062880000 # Time in different power states +system.physmem_0.refreshEnergy 79137021600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 416124660195 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 361949541750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 878257471275 # Total energy per rank (pJ) +system.physmem_0.averagePower 724.862968 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 599359370250 # Time in different power states +system.physmem_0.memoryStateTime::REF 40458600000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 562842538250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 571802499750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7152516000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3902662500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7901961600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3364241040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 78362993280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 422708761260 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 349063611000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 872456746680 # Total energy per rank (pJ) -system.physmem_1.averagePower 727.187909 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 577877428500 # Time in different power states -system.physmem_1.memoryStateTime::REF 40062880000 # Time in different power states +system.physmem_1.actEnergy 7157785320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3905537625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7902000600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3364254000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 79137021600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 427714080030 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 351783384000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 880964063175 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.096833 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 582370760250 # Time in different power states +system.physmem_1.memoryStateTime::REF 40458600000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 581827655250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 588789276000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 246222594 # Number of BP lookups -system.cpu.branchPred.condPredicted 186441188 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15682162 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 167748253 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165224895 # Number of BTB hits +system.cpu.branchPred.lookups 246245862 # Number of BP lookups +system.cpu.branchPred.condPredicted 186459693 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15680292 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 167860438 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165233261 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.495747 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18427327 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104678 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.434904 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18428492 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104737 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452533853 # DTB read hits -system.cpu.dtb.read_misses 4979561 # DTB read misses +system.cpu.dtb.read_hits 452534136 # DTB read hits +system.cpu.dtb.read_misses 4979812 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457513414 # DTB read accesses -system.cpu.dtb.write_hits 161377742 # DTB write hits -system.cpu.dtb.write_misses 1710117 # DTB write misses +system.cpu.dtb.read_accesses 457513948 # DTB read accesses +system.cpu.dtb.write_hits 161377662 # DTB write hits +system.cpu.dtb.write_misses 1710258 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163087859 # DTB write accesses -system.cpu.dtb.data_hits 613911595 # DTB hits -system.cpu.dtb.data_misses 6689678 # DTB misses +system.cpu.dtb.write_accesses 163087920 # DTB write accesses +system.cpu.dtb.data_hits 613911798 # DTB hits +system.cpu.dtb.data_misses 6690070 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 620601273 # DTB accesses -system.cpu.itb.fetch_hits 598493672 # ITB hits +system.cpu.dtb.data_accesses 620601868 # DTB accesses +system.cpu.itb.fetch_hits 598519306 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 598493691 # ITB accesses +system.cpu.itb.fetch_accesses 598519325 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -329,82 +330,82 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2399548560 # number of cpu cycles simulated +system.cpu.numCycles 2423248959 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 52395177 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 52407440 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.313829 # CPI: cycles per instruction -system.cpu.ipc 0.761134 # IPC: instructions per cycle -system.cpu.tickCycles 2077217503 # Number of cycles that the object actually ticked -system.cpu.idleCycles 322331057 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9121997 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.675710 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 601828569 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126093 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.945917 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 16789907000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4080.675710 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996259 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996259 # Average percentage of cache occupancy +system.cpu.cpi 1.326805 # CPI: cycles per instruction +system.cpu.ipc 0.753690 # IPC: instructions per cycle +system.cpu.tickCycles 2077336659 # Number of cycles that the object actually ticked +system.cpu.idleCycles 345912300 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9122013 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.749026 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 601822613 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126109 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.945148 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 16826930000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4080.749026 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996277 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1613 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2310 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2418 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1231839903 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1231839903 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 443338834 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 443338834 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158489735 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158489735 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 601828569 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 601828569 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 601828569 # number of overall hits -system.cpu.dcache.overall_hits::total 601828569 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7289569 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7289569 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2238767 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2238767 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9528336 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9528336 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9528336 # number of overall misses -system.cpu.dcache.overall_misses::total 9528336 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 178039686000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 178039686000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 100958450500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 100958450500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 278998136500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 278998136500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 278998136500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 278998136500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 450628403 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 450628403 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1231838683 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1231838683 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 443338219 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 443338219 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158484394 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158484394 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 601822613 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 601822613 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 601822613 # number of overall hits +system.cpu.dcache.overall_hits::total 601822613 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7289566 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289566 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2244108 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2244108 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9533674 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9533674 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9533674 # number of overall misses +system.cpu.dcache.overall_misses::total 9533674 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 186798880750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 186798880750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 108940864000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 108940864000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 295739744750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 295739744750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 295739744750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 295739744750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 450627785 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 450627785 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 611356905 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 611356905 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 611356905 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 611356905 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 611356287 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 611356287 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 611356287 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 611356287 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016176 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016176 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013929 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013929 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015586 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015586 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015586 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015586 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24423.897490 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24423.897490 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45095.559520 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45095.559520 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29280.887712 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29280.887712 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29280.887712 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29280.887712 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013962 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013962 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015594 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015594 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015594 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015594 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25625.514708 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25625.514708 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48545.285699 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48545.285699 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31020.543051 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31020.543051 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31020.543051 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31020.543051 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -413,32 +414,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700624 # number of writebacks -system.cpu.dcache.writebacks::total 3700624 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50811 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50811 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 351432 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 351432 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 402243 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 402243 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 402243 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 402243 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238758 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238758 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887335 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887335 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9126093 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126093 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9126093 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126093 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 162083992000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 162083992000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75948494500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 75948494500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 238032486500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 238032486500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 238032486500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 238032486500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3700625 # number of writebacks +system.cpu.dcache.writebacks::total 3700625 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50791 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50791 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 356774 # 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number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126109 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 174334776000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 174334776000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82397045250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 82397045250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 256731821250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 256731821250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 256731821250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 256731821250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016064 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016064 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses @@ -447,66 +448,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014928 system.cpu.dcache.demand_mshr_miss_rate::total 0.014928 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014928 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014928 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22391.132844 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22391.132844 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40241.130748 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40241.130748 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26082.627747 # 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Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1196988303 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1196988303 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 598492713 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 598492713 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 598492713 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 598492713 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 598492713 # number of overall hits -system.cpu.icache.overall_hits::total 598492713 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 959 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 959 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 959 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 959 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 959 # 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number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 598493672 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.465820 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1197039569 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1197039569 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 598518349 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 598518349 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 598518349 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 598518349 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 598518349 # number of overall hits +system.cpu.icache.overall_hits::total 598518349 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 957 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 957 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 957 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 957 # number of overall misses +system.cpu.icache.overall_misses::total 957 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 77501250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 77501250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 77501250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 77501250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 77501250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 77501250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 598519306 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 598519306 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 598519306 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 598519306 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 598519306 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 598519306 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74063.868613 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74063.868613 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74063.868613 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74063.868613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74063.868613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74063.868613 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80983.542320 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 80983.542320 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80983.542320 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80983.542320 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80983.542320 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80983.542320 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -515,120 +516,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 959 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 959 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 959 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 959 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 959 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 959 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68715750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 68715750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68715750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 68715750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68715750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 68715750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 957 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 957 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 957 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 957 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 957 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 957 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75665250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 75665250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75665250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 75665250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75665250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 75665250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71653.545360 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71653.545360 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71653.545360 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71653.545360 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71653.545360 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71653.545360 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79065.047022 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79065.047022 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79065.047022 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79065.047022 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79065.047022 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79065.047022 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1928296 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30756.810610 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8981713 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1958100 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.586953 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 89009074750 # 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mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214777 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214776 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.214859 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58081.074035 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67267.837631 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67260.381430 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68154.174097 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68154.174097 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58081.074035 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67620.301703 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58081.074035 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67620.301703 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65538.923720 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74998.570670 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74990.908995 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75649.873372 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75649.873372 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65538.923720 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75257.569751 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75252.826961 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65538.923720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75257.569751 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75252.826961 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7239717 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7239717 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700624 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887335 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887335 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1918 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952810 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21954728 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820909888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 820971264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7239732 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7239732 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700625 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887334 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887334 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1914 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952843 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21954757 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820910976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820972224 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12827676 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12827691 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12827676 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12827691 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12827676 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10114462000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12827691 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10114470500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1635250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1635750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14011262000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14015207750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1181581 # Transaction distribution -system.membus.trans_dist::ReadResp 1181581 # Transaction distribution -system.membus.trans_dist::Writeback 1018242 # Transaction distribution -system.membus.trans_dist::ReadExReq 779450 # Transaction distribution -system.membus.trans_dist::ReadExResp 779450 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940304 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4940304 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190673472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190673472 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1181580 # Transaction distribution +system.membus.trans_dist::ReadResp 1181580 # Transaction distribution +system.membus.trans_dist::Writeback 1018244 # Transaction distribution +system.membus.trans_dist::ReadExReq 779448 # Transaction distribution +system.membus.trans_dist::ReadExResp 779448 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940300 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4940300 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190673408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190673408 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2979273 # Request fanout histogram +system.membus.snoop_fanout::samples 2979272 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2979273 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2979272 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2979273 # Request fanout histogram -system.membus.reqLayer0.occupancy 11833185000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 18446289250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.5 # Layer utilization (%) +system.membus.snoop_fanout::total 2979272 # Request fanout histogram +system.membus.reqLayer0.occupancy 7744840000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 10727612750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 9b6ff7bd3..47b73b46e 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.662030 # Number of seconds simulated -sim_ticks 662030381000 # Number of ticks simulated -final_tick 662030381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.672882 # Number of seconds simulated +sim_ticks 672881519500 # Number of ticks simulated +final_tick 672881519500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173779 # Simulator instruction rate (inst/s) -host_op_rate 173779 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66269486 # Simulator tick rate (ticks/s) -host_mem_usage 296312 # Number of bytes of host memory used -host_seconds 9989.97 # Real time elapsed on the host +host_inst_rate 171066 # Simulator instruction rate (inst/s) +host_op_rate 171066 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66304234 # Simulator tick rate (ticks/s) +host_mem_usage 296744 # Number of bytes of host memory used +host_seconds 10148.39 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125964224 # Number of bytes read from this memory -system.physmem.bytes_read::total 126026048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65301568 # Number of bytes written to this memory -system.physmem.bytes_written::total 65301568 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 966 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1968191 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1969157 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1020337 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1020337 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 93385 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 190269552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 190362937 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 93385 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 93385 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 98638325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 98638325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 98638325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 93385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 190269552 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 289001263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1969157 # Number of read requests accepted -system.physmem.writeReqs 1020337 # Number of write requests accepted -system.physmem.readBursts 1969157 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1020337 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125945216 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 80832 # Total number of bytes read from write queue -system.physmem.bytesWritten 65299584 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 126026048 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65301568 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1263 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 62400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125964544 # Number of bytes read from this memory +system.physmem.bytes_read::total 126026944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 62400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 62400 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65296192 # Number of bytes written to this memory +system.physmem.bytes_written::total 65296192 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 975 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1968196 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1969171 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1020253 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1020253 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 187201670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 187294405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92735 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92735 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 97039657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 97039657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 97039657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 187201670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 284334062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1969171 # Number of read requests accepted +system.physmem.writeReqs 1020253 # Number of write requests accepted +system.physmem.readBursts 1969171 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1020253 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125945600 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 81344 # Total number of bytes read from write queue +system.physmem.bytesWritten 65294336 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 126026944 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65296192 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1271 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119107 # Per bank write bursts -system.physmem.perBankRdBursts::1 114513 # Per bank write bursts -system.physmem.perBankRdBursts::2 116588 # Per bank write bursts -system.physmem.perBankRdBursts::3 118130 # Per bank write bursts -system.physmem.perBankRdBursts::4 118281 # Per bank write bursts -system.physmem.perBankRdBursts::5 117894 # Per bank write bursts -system.physmem.perBankRdBursts::6 120372 # Per bank write bursts -system.physmem.perBankRdBursts::7 125027 # Per bank write bursts -system.physmem.perBankRdBursts::8 127642 # Per bank write bursts -system.physmem.perBankRdBursts::9 130604 # Per bank write bursts -system.physmem.perBankRdBursts::10 129295 # Per bank write bursts -system.physmem.perBankRdBursts::11 130929 # Per bank write bursts -system.physmem.perBankRdBursts::12 126770 # Per bank write bursts -system.physmem.perBankRdBursts::13 125862 # Per bank write bursts -system.physmem.perBankRdBursts::14 123081 # Per bank write bursts -system.physmem.perBankRdBursts::15 123799 # Per bank write bursts -system.physmem.perBankWrBursts::0 61289 # Per bank write bursts -system.physmem.perBankWrBursts::1 61597 # Per bank write bursts -system.physmem.perBankWrBursts::2 60658 # Per bank write bursts -system.physmem.perBankWrBursts::3 61339 # Per bank write bursts -system.physmem.perBankWrBursts::4 61821 # Per bank write bursts -system.physmem.perBankWrBursts::5 63209 # Per bank write bursts -system.physmem.perBankWrBursts::6 64289 # Per bank write bursts -system.physmem.perBankWrBursts::7 65739 # Per bank write bursts -system.physmem.perBankWrBursts::8 65503 # Per bank write bursts -system.physmem.perBankWrBursts::9 65920 # Per bank write bursts -system.physmem.perBankWrBursts::10 65439 # Per bank write bursts -system.physmem.perBankWrBursts::11 65771 # Per bank write bursts -system.physmem.perBankWrBursts::12 64363 # Per bank write bursts -system.physmem.perBankWrBursts::13 64352 # Per bank write bursts -system.physmem.perBankWrBursts::14 64685 # Per bank write bursts -system.physmem.perBankWrBursts::15 64332 # Per bank write bursts +system.physmem.perBankRdBursts::0 119102 # Per bank write bursts +system.physmem.perBankRdBursts::1 114505 # Per bank write bursts +system.physmem.perBankRdBursts::2 116613 # Per bank write bursts +system.physmem.perBankRdBursts::3 118153 # Per bank write bursts +system.physmem.perBankRdBursts::4 118234 # Per bank write bursts +system.physmem.perBankRdBursts::5 117885 # Per bank write bursts +system.physmem.perBankRdBursts::6 120369 # Per bank write bursts +system.physmem.perBankRdBursts::7 125035 # Per bank write bursts +system.physmem.perBankRdBursts::8 127648 # Per bank write bursts +system.physmem.perBankRdBursts::9 130593 # Per bank write bursts +system.physmem.perBankRdBursts::10 129299 # Per bank write bursts +system.physmem.perBankRdBursts::11 130947 # Per bank write bursts +system.physmem.perBankRdBursts::12 126747 # Per bank write bursts +system.physmem.perBankRdBursts::13 125863 # Per bank write bursts +system.physmem.perBankRdBursts::14 123089 # Per bank write bursts +system.physmem.perBankRdBursts::15 123818 # Per bank write bursts +system.physmem.perBankWrBursts::0 61291 # Per bank write bursts +system.physmem.perBankWrBursts::1 61585 # Per bank write bursts +system.physmem.perBankWrBursts::2 60661 # Per bank write bursts +system.physmem.perBankWrBursts::3 61360 # Per bank write bursts +system.physmem.perBankWrBursts::4 61790 # Per bank write bursts +system.physmem.perBankWrBursts::5 63221 # Per bank write bursts +system.physmem.perBankWrBursts::6 64275 # Per bank write bursts +system.physmem.perBankWrBursts::7 65726 # Per bank write bursts +system.physmem.perBankWrBursts::8 65508 # Per bank write bursts +system.physmem.perBankWrBursts::9 65914 # Per bank write bursts +system.physmem.perBankWrBursts::10 65448 # Per bank write bursts +system.physmem.perBankWrBursts::11 65777 # Per bank write bursts +system.physmem.perBankWrBursts::12 64328 # Per bank write bursts +system.physmem.perBankWrBursts::13 64347 # Per bank write bursts +system.physmem.perBankWrBursts::14 64660 # Per bank write bursts +system.physmem.perBankWrBursts::15 64333 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 662030291500 # Total gap between requests +system.physmem.totGap 672881423000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1969157 # Read request sizes (log2) +system.physmem.readPktSize::6 1969171 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1020337 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1619145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 248303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 76115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1020253 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1621016 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 243733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 72507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 27497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 63086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 64803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 26054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 27728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 64414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -193,142 +193,143 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1776224 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.667141 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.863857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 136.742577 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1381396 77.77% 77.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 271071 15.26% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53950 3.04% 96.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21226 1.20% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12955 0.73% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6597 0.37% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5003 0.28% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3759 0.21% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20267 1.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1776224 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59925 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.795728 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 163.660245 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59887 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 9 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1777587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.583217 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.835342 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 136.553801 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1382839 77.79% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 271264 15.26% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53815 3.03% 96.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21128 1.19% 97.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12924 0.73% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6598 0.37% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5024 0.28% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3881 0.22% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20114 1.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1777587 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59878 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.821905 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.087941 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59840 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59925 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59925 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.026383 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.985304 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.212732 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 31950 53.32% 53.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1595 2.66% 55.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 20819 34.74% 90.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4577 7.64% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 750 1.25% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 154 0.26% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 27 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 19 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 7 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 59878 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59878 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.038378 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.996376 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.234472 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 31771 53.06% 53.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1453 2.43% 55.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 20992 35.06% 90.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4585 7.66% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 809 1.35% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 191 0.32% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 31 0.05% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 14 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 5 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::42 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59925 # Writes before turning the bus around for reads -system.physmem.totQLat 40790268000 # Total ticks spent queuing -system.physmem.totMemAccLat 77688280500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9839470000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20727.88 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::52 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59878 # Writes before turning the bus around for reads +system.physmem.totQLat 40967898000 # Total ticks spent queuing +system.physmem.totMemAccLat 77866023000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9839500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20818.08 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39477.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 190.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 98.64 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 190.36 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 98.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39568.08 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 187.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 97.04 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 187.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 97.04 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.26 # Data bus utilization in percentage -system.physmem.busUtilRead 1.49 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.77 # Data bus utilization in percentage for writes +system.physmem.busUtil 2.22 # Data bus utilization in percentage +system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.76 # Average write queue length when enqueuing -system.physmem.readRowHits 795786 # Number of row buffer hits during reads -system.physmem.writeRowHits 416180 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.79 # Row buffer hit rate for writes -system.physmem.avgGap 221452.29 # Average gap between requests -system.physmem.pageHitRate 40.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6511261680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3552771750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7409259000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3239617680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 43240314000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 299928124440 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 134120853750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 498002202300 # Total energy per rank (pJ) -system.physmem_0.averagePower 752.239455 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 221171423750 # Time in different power states -system.physmem_0.memoryStateTime::REF 22106500000 # Time in different power states +system.physmem.avgWrQLen 24.71 # Average write queue length when enqueuing +system.physmem.readRowHits 794560 # Number of row buffer hits during reads +system.physmem.writeRowHits 415972 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.77 # Row buffer hit rate for writes +system.physmem.avgGap 225087.32 # Average gap between requests +system.physmem.pageHitRate 40.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6515684280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3555184875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7409165400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3239410320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 43949246640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 305964835695 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 135337912500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 505971439710 # Total energy per rank (pJ) +system.physmem_0.averagePower 751.948773 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 223158478000 # Time in different power states +system.physmem_0.memoryStateTime::REF 22468940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 418748256250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 427253308500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6916946400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3774127500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7939518600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3371965200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 43240314000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 306633623535 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 128238837000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 500115332235 # Total energy per rank (pJ) -system.physmem_1.averagePower 755.431368 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 211341940750 # Time in different power states -system.physmem_1.memoryStateTime::REF 22106500000 # Time in different power states +system.physmem_1.actEnergy 6922850760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3777349125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7940244000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3371641200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 43949246640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 312976099035 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 129187681500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 508125112260 # Total energy per rank (pJ) +system.physmem_1.averagePower 755.149450 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 212887456750 # Time in different power states +system.physmem_1.memoryStateTime::REF 22468940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 428577885750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 437523815750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 410531758 # Number of BP lookups -system.cpu.branchPred.condPredicted 318847451 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16269165 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 283137932 # Number of BTB lookups -system.cpu.branchPred.BTBHits 279377578 # Number of BTB hits +system.cpu.branchPred.lookups 410709882 # Number of BP lookups +system.cpu.branchPred.condPredicted 318998342 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16277823 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 282986544 # Number of BTB lookups +system.cpu.branchPred.BTBHits 279468528 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.671900 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26373623 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 19 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.756826 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26379180 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 646133385 # DTB read hits -system.cpu.dtb.read_misses 12154937 # DTB read misses -system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 658288322 # DTB read accesses -system.cpu.dtb.write_hits 218173916 # DTB write hits -system.cpu.dtb.write_misses 7514058 # DTB write misses +system.cpu.dtb.read_hits 646309229 # DTB read hits +system.cpu.dtb.read_misses 12154225 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 658463454 # DTB read accesses +system.cpu.dtb.write_hits 218201258 # DTB write hits +system.cpu.dtb.write_misses 7510092 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225687974 # DTB write accesses -system.cpu.dtb.data_hits 864307301 # DTB hits -system.cpu.dtb.data_misses 19668995 # DTB misses -system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 883976296 # DTB accesses -system.cpu.itb.fetch_hits 422458110 # ITB hits -system.cpu.itb.fetch_misses 45 # ITB misses +system.cpu.dtb.write_accesses 225711350 # DTB write accesses +system.cpu.dtb.data_hits 864510487 # DTB hits +system.cpu.dtb.data_misses 19664317 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 884174804 # DTB accesses +system.cpu.itb.fetch_hits 422619736 # ITB hits +system.cpu.itb.fetch_misses 46 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 422458155 # ITB accesses +system.cpu.itb.fetch_accesses 422619782 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -342,238 +343,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1324060763 # number of cpu cycles simulated +system.cpu.numCycles 1345763040 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 433748906 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3419441963 # Number of instructions fetch has processed -system.cpu.fetch.Branches 410531758 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 305751201 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 867248304 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 45995858 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 88 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1804 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 422458110 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8422260 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1323997070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.582666 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.157790 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 433914332 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3420599858 # Number of instructions fetch has processed +system.cpu.fetch.Branches 410709882 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 305847708 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 888768265 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 46015780 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1748 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 422619736 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8427195 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1345692377 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.541888 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.149351 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 696991073 52.64% 52.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48002120 3.63% 56.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24407254 1.84% 58.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45263157 3.42% 61.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 142993214 10.80% 72.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 66222276 5.00% 77.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43788088 3.31% 80.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29616004 2.24% 82.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226713884 17.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 718495980 53.39% 53.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 48031633 3.57% 56.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24393578 1.81% 58.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45267643 3.36% 62.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 143041045 10.63% 72.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 66223895 4.92% 77.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43793513 3.25% 80.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29627313 2.20% 83.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226817777 16.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1323997070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310055 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.582542 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 355597650 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 384696746 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 525812607 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34892959 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 22997108 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62293389 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 869 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3264034948 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2192 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 22997108 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 373957968 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 205165673 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7731 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 538730067 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 183138523 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3181033284 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1755579 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18983042 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 140285341 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 27927823 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2377354751 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4126620289 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4126448707 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 171581 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1345692377 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305187 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.541755 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 355603714 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 406294583 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 525817435 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 34969591 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 23007054 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62310888 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 895 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3264812656 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2282 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 23007054 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 373973816 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 212778142 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7997 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 538797541 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 197127827 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3181847820 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1862600 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20249864 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 150635497 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 31416943 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2377870821 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4127617004 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4127447466 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 169537 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1001151788 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 192 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 191 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99207749 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 719206023 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272877739 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90880933 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 59162115 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2889782486 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 178 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2624016708 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1570062 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1139342915 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 505618557 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 149 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1323997070 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.981890 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.151111 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1001667858 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 209 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 206 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99280769 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 719325488 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272942348 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90808423 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 59047660 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2890368727 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 181 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2624396643 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1584497 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1140831193 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 506084435 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1345692377 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.950220 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.146970 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 519747645 39.26% 39.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 169377682 12.79% 52.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158338012 11.96% 64.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149173722 11.27% 75.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126185648 9.53% 84.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84437665 6.38% 91.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68199937 5.15% 96.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 33982775 2.57% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14553984 1.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 540762104 40.18% 40.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 169795677 12.62% 52.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158437148 11.77% 64.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149383051 11.10% 75.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126329288 9.39% 85.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84501883 6.28% 91.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68040537 5.06% 96.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34033784 2.53% 98.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14408905 1.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1323997070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1345692377 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13171575 35.70% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19111155 51.80% 87.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4612971 12.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13165371 35.79% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19036657 51.75% 87.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4585623 12.47% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1719329788 65.52% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 125 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1719509054 65.52% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 111 0.00% 65.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 895316 0.03% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 18 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 672939161 25.65% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230852080 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 896832 0.03% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 17 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 164 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 25 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 673114194 25.65% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230876222 8.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2624016708 # Type of FU issued -system.cpu.iq.rate 1.981795 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36895701 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014061 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6608517036 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4027973051 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2521923586 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1979213 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1297888 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 892539 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2659929620 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 982789 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69543206 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2624396643 # Type of FU issued +system.cpu.iq.rate 1.950118 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36787651 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014018 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6630876089 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4030049566 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2522176401 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1981722 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1296863 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 893189 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2660200136 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 984158 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69569005 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 274610360 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 379362 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 147727 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 112149237 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 274729825 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 379855 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 148630 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 112213846 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 353 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6023017 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 321 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6130129 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 22997108 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 147758887 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18474565 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3040988458 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6691344 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 719206023 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272877739 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 178 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 822290 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17921565 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 147727 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10901488 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8843129 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19744617 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2578330269 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 658288327 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45686439 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 23007054 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 150994559 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 20053347 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3041642230 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6687101 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 719325488 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272942348 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 181 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 819254 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 19491023 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 148630 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10888571 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8843177 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19731748 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2578706854 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 658463458 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45689789 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151205794 # number of nop insts executed -system.cpu.iew.exec_refs 883976375 # number of memory reference insts executed -system.cpu.iew.exec_branches 315983093 # Number of branches executed -system.cpu.iew.exec_stores 225688048 # Number of stores executed -system.cpu.iew.exec_rate 1.947290 # Inst execution rate -system.cpu.iew.wb_sent 2552817971 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2522816125 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1489246506 # num instructions producing a value -system.cpu.iew.wb_consumers 1920479792 # num instructions consuming a value +system.cpu.iew.exec_nop 151273322 # number of nop insts executed +system.cpu.iew.exec_refs 884174883 # number of memory reference insts executed +system.cpu.iew.exec_branches 315972780 # Number of branches executed +system.cpu.iew.exec_stores 225711425 # Number of stores executed +system.cpu.iew.exec_rate 1.916167 # Inst execution rate +system.cpu.iew.wb_sent 2553063246 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2523069590 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1489308587 # num instructions producing a value +system.cpu.iew.wb_consumers 1920703402 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.905363 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775455 # average fanout of values written-back +system.cpu.iew.wb_rate 1.874825 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775397 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1005136223 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1005912526 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16268344 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1185116972 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.535528 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.558449 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16276987 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1206693157 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.508072 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.543192 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 695949152 58.72% 58.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159874809 13.49% 72.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79784402 6.73% 78.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52116706 4.40% 83.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28440614 2.40% 85.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19407125 1.64% 87.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20027045 1.69% 89.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23110908 1.95% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106406211 8.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 717446911 59.46% 59.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159887401 13.25% 72.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79830197 6.62% 79.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52027392 4.31% 83.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28503242 2.36% 85.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19553290 1.62% 87.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20023421 1.66% 89.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23140213 1.92% 91.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106281090 8.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1185116972 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1206693157 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -619,339 +620,341 @@ system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106406211 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106281090 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3817847910 # The number of ROB reads -system.cpu.rob.rob_writes 5788846951 # The number of ROB writes -system.cpu.timesIdled 724 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 63693 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3840325519 # The number of ROB reads +system.cpu.rob.rob_writes 5790523687 # The number of ROB writes +system.cpu.timesIdled 690 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 70663 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.762689 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.762689 # CPI: Total CPI of All Threads -system.cpu.ipc 1.311151 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.311151 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3467581476 # number of integer regfile reads -system.cpu.int_regfile_writes 2022302956 # number of integer regfile writes -system.cpu.fp_regfile_reads 46080 # number of floating regfile reads -system.cpu.fp_regfile_writes 592 # number of floating regfile writes +system.cpu.cpi 0.775190 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.775190 # CPI: Total CPI of All Threads +system.cpu.ipc 1.290007 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.290007 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3468053564 # number of integer regfile reads +system.cpu.int_regfile_writes 2022530151 # number of integer regfile writes +system.cpu.fp_regfile_reads 45442 # number of floating regfile reads +system.cpu.fp_regfile_writes 563 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9209012 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.412521 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 713854428 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9213108 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 77.482477 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5099544250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.412521 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997903 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997903 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9208756 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.479772 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 713775439 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9212852 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.476056 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5132407000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.479772 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997920 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997920 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 751 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2935 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 697 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2970 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1472845170 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1472845170 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 558341279 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 558341279 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155513145 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155513145 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1472909430 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1472909430 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 558274718 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 558274718 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155500717 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155500717 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 713854424 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 713854424 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 713854424 # number of overall hits -system.cpu.dcache.overall_hits::total 713854424 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12746245 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12746245 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5215357 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5215357 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 713775435 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 713775435 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 713775435 # number of overall hits +system.cpu.dcache.overall_hits::total 713775435 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12845064 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12845064 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5227785 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5227785 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17961602 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17961602 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17961602 # number of overall misses -system.cpu.dcache.overall_misses::total 17961602 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 384451562750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 384451562750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 289305166008 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 289305166008 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 69500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 69500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 673756728758 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 673756728758 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 673756728758 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 673756728758 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 571087524 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 571087524 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 18072849 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 18072849 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 18072849 # number of overall misses +system.cpu.dcache.overall_misses::total 18072849 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 414536288750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 414536288750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 316664843212 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 316664843212 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 72500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 731201131962 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 731201131962 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 731201131962 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 731201131962 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 571119782 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 571119782 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 731816026 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 731816026 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 731816026 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 731816026 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022319 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022319 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032448 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032448 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 731848284 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 731848284 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 731848284 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 731848284 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022491 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022491 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032526 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032526 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024544 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024544 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024544 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024544 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30161.946734 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30161.946734 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55471.785730 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55471.785730 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37510.948564 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37510.948564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37510.948564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37510.948564 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14120110 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8634302 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1055091 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67341 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.382836 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 128.217609 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.024695 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024695 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024695 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024695 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32272.029844 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32272.029844 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60573.425114 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60573.425114 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40458.542644 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40458.542644 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40458.542644 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40458.542644 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15275634 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9588635 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1068737 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67992 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.293165 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 141.025930 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3742780 # number of writebacks -system.cpu.dcache.writebacks::total 3742780 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5412238 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5412238 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3336257 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3336257 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8748495 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8748495 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8748495 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8748495 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334007 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7334007 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879100 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879100 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3742849 # number of writebacks +system.cpu.dcache.writebacks::total 3742849 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5511228 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5511228 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3348770 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3348770 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8859998 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8859998 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8859998 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8859998 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333836 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7333836 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879015 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879015 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9213107 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9213107 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9213107 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9213107 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168659488250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 168659488250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77208966781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77208966781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 67500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 67500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245868455031 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 245868455031 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245868455031 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 245868455031 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9212851 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9212851 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9212851 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9212851 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180521790750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 180521790750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83364623703 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83364623703 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 71000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 71000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 263886414453 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 263886414453 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 263886414453 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 263886414453 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012841 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012841 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012589 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012589 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22996.908545 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22996.908545 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41088.269268 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41088.269268 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 67500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 67500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26686.812064 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26686.812064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26686.812064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26686.812064 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012588 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012588 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012588 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012588 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24614.920589 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24614.920589 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44366.129969 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44366.129969 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 71000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 71000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28643.295594 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28643.295594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28643.295594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28643.295594 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 770.158211 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 422456585 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 966 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 437325.657350 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 773.497223 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 422618194 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 975 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 433454.557949 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 770.158211 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.376054 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.376054 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 773.497223 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.377684 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.377684 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 974 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 899 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 844917184 # Number of tag accesses -system.cpu.icache.tags.data_accesses 844917184 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 422456585 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 422456585 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 422456585 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 422456585 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 422456585 # number of overall hits -system.cpu.icache.overall_hits::total 422456585 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1524 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1524 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1524 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1524 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1524 # number of overall misses -system.cpu.icache.overall_misses::total 1524 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 107000999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 107000999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 107000999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 107000999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 107000999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 107000999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 422458109 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 422458109 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 422458109 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 422458109 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 422458109 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 422458109 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.475586 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 845240447 # Number of tag accesses +system.cpu.icache.tags.data_accesses 845240447 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 422618194 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 422618194 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 422618194 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 422618194 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 422618194 # number of overall hits +system.cpu.icache.overall_hits::total 422618194 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1542 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1542 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1542 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1542 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1542 # number of overall misses +system.cpu.icache.overall_misses::total 1542 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 116278500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 116278500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 116278500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 116278500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 116278500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 116278500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 422619736 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 422619736 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 422619736 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 422619736 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 422619736 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 422619736 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70210.629265 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70210.629265 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70210.629265 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70210.629265 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70210.629265 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70210.629265 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 469 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75407.587549 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75407.587549 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75407.587549 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75407.587549 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75407.587549 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75407.587549 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 435 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 67 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62.142857 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 558 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 558 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 558 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 558 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 558 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 558 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 966 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 966 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72141249 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 72141249 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72141249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 72141249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72141249 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 72141249 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 567 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 567 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 567 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 567 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 567 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 567 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 975 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 975 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 975 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 975 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 975 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79199000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 79199000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79199000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 79199000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79199000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 79199000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74680.381988 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74680.381988 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74680.381988 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74680.381988 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74680.381988 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74680.381988 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81229.743590 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81229.743590 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81229.743590 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 81229.743590 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81229.743590 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 81229.743590 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1936441 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31406.538176 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9110982 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1966231 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.633729 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 27876136750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14557.398525 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.847630 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16822.292021 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.444257 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000819 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.513376 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.958451 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29790 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 970 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 611 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17653 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10389 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909119 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 107500175 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 107500175 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.data 6137091 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6137091 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3742780 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3742780 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1107826 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1107826 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7244917 # 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number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 162669041748 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 966 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7333996 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7334962 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3742780 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3742780 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1879112 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1879112 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 966 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9213108 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9214074 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 966 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9213108 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9214074 # number of overall (read+write) accesses +system.cpu.l2cache.tags.replacements 1936457 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31413.219008 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9110872 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1966244 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.633643 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 28158140750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14523.555801 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.886283 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16862.776924 # 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average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82612.853376 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82608.467353 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73672.101449 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82612.853376 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82608.467353 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.213636 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.213719 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80220.512821 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 90035.906632 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 90027.917310 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89856.827119 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89856.827119 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80220.512821 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89965.726737 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 89960.901567 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80220.512821 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89965.726737 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 89960.901567 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -960,105 +963,105 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1968191 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1969157 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58998750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 83895775000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83954773750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54083955498 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54083955498 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58998750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137979730498 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 138038729248 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58998750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137979730498 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 138038729248 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1020253 # number of writebacks +system.cpu.l2cache.writebacks::total 1020253 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 975 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1196875 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1197850 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 771321 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 771321 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 975 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1968196 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1969171 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 975 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1968196 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1969171 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66029500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 92659024750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 92725054250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59593481750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59593481750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66029500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 152252506500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 152318536000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66029500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 152252506500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 152318536000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163200 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163310 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410452 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410452 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163199 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163311 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410489 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410489 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213629 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.213712 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213636 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.213719 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213629 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.213712 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61075.310559 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70093.929761 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70086.656869 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70121.790747 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70121.790747 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61075.310559 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70104.847801 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70100.418224 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61075.310559 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70104.847801 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70100.418224 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213636 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.213719 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67722.564103 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77417.461932 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77409.570689 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77261.583374 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77261.583374 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67722.564103 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77356.374314 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77351.604305 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67722.564103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77356.374314 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77351.604305 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7334962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7334962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3742780 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879112 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879112 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1932 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22168996 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22170928 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829176832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 829238656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7334797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7334797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3742849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879030 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879030 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1950 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22168553 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22170503 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829164864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 829227264 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12957003 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12956676 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12957003 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12956676 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12957003 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10221354853 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12956676 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10221187000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1610750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1642000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14117356000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14136511250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1197871 # Transaction distribution -system.membus.trans_dist::ReadResp 1197871 # Transaction distribution -system.membus.trans_dist::Writeback 1020337 # Transaction distribution -system.membus.trans_dist::ReadExReq 771286 # Transaction distribution -system.membus.trans_dist::ReadExResp 771286 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4958651 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4958651 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191327616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 191327616 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1197850 # Transaction distribution +system.membus.trans_dist::ReadResp 1197850 # Transaction distribution +system.membus.trans_dist::Writeback 1020253 # Transaction distribution +system.membus.trans_dist::ReadExReq 771321 # Transaction distribution +system.membus.trans_dist::ReadExResp 771321 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4958595 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4958595 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191323136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191323136 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2989494 # Request fanout histogram +system.membus.snoop_fanout::samples 2989424 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2989494 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2989424 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2989494 # Request fanout histogram -system.membus.reqLayer0.occupancy 11823428000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 18423304250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.8 # Layer utilization (%) +system.membus.snoop_fanout::total 2989424 # Request fanout histogram +system.membus.reqLayer0.occupancy 7771933000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 10726595500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 2d7afdf8e..6346aa78f 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.623386 # Number of seconds simulated -sim_ticks 2623386226000 # Number of ticks simulated -final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.623365 # Number of seconds simulated +sim_ticks 2623365440500 # Number of ticks simulated +final_tick 2623365440500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1656263 # Simulator instruction rate (inst/s) -host_op_rate 1656263 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2387660297 # Simulator tick rate (ticks/s) -host_mem_usage 289632 # Number of bytes of host memory used -host_seconds 1098.73 # Real time elapsed on the host +host_inst_rate 1411989 # Simulator instruction rate (inst/s) +host_op_rate 1411989 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2035500124 # Simulator tick rate (ticks/s) +host_mem_usage 294160 # Number of bytes of host memory used +host_seconds 1288.81 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,40 +26,16 @@ system.physmem.num_reads::total 1959663 # Nu system.physmem.num_writes::writebacks 1018077 # Number of write requests responded to by this memory system.physmem.num_writes::total 1018077 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 19566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47788276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47807841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47788654 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47808220 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 19566 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 19566 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 24836956 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 24836956 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 24836956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 24837153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24837153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 24837153 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47788276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 72644797 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1178362 # Transaction distribution -system.membus.trans_dist::ReadResp 1178362 # Transaction distribution -system.membus.trans_dist::Writeback 1018077 # Transaction distribution -system.membus.trans_dist::ReadExReq 781301 # Transaction distribution -system.membus.trans_dist::ReadExResp 781301 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2977740 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2977740 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2977740 # Request fanout histogram -system.membus.reqLayer0.occupancy 11122356000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 17636967000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.physmem.bw_total::cpu.data 47788654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 72645373 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -94,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 5246772452 # number of cpu cycles simulated +system.cpu.numCycles 5246730881 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1819780127 # Number of instructions committed @@ -113,7 +89,7 @@ system.cpu.num_mem_refs 611922547 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5246772452 # Number of busy cycles +system.cpu.num_busy_cycles 5246730881 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 214632552 # Number of branches fetched @@ -152,13 +128,122 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction +system.cpu.dcache.tags.replacements 9107638 # number of replacements +system.cpu.dcache.tags.tagsinuse 4079.262739 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 40977437000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262739 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2584 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 200 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits +system.cpu.dcache.overall_hits::total 596212431 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses +system.cpu.dcache.overall_misses::total 9111734 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143355355000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143355355000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57375808000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57375808000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200731163000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200731163000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200731163000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200731163000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19848.675941 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19848.675941 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30368.496602 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30368.496602 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22029.963013 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22029.963013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22029.963013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22029.963013 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks +system.cpu.dcache.writebacks::total 3693497 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132521734000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 132521734000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54541828000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 54541828000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187063562000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 187063562000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187063562000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 187063562000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18348.675941 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18348.675941 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28868.496602 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28868.496602 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20529.963013 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20529.963013 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20529.963013 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20529.963013 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 612.458646 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 612.458786 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 612.458786 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id @@ -179,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44182000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44182000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44182000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44182000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44182000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44182000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44139500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44139500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44139500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44139500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44139500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44139500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses @@ -197,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55089.775561 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55089.775561 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55089.775561 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55089.775561 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55089.775561 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55089.775561 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55036.783042 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55036.783042 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55036.783042 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55036.783042 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55036.783042 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55036.783042 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -217,43 +302,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42578000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42578000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42578000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42578000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42578000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42578000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42936500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42936500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42936500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42936500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42936500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42936500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53089.775561 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53089.775561 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53536.783042 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53536.783042 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53536.783042 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53536.783042 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53536.783042 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53536.783042 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1926937 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30535.257456 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30535.253333 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8959453 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1956729 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.578791 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy +system.cpu.l2cache.tags.warmup_cycle 218167126000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15221.864156 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064589 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.324589 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.464534 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29792 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1059 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1060 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1253 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27303 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 106294313 # Number of tag accesses @@ -279,17 +364,17 @@ system.cpu.l2cache.demand_misses::total 1959663 # nu system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1958861 # number of overall misses system.cpu.l2cache.overall_misses::total 1959663 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41776000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61258944000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 61300720000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40629030000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 40629030000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 41776000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 101887974000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 101929750000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 41776000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 101887974000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 101929750000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42134500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61828353000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61870487500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41018308500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41018308500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 42134500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 102846661500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 102888796000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 42134500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102846661500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 102888796000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7222414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7223216 # number of ReadReq accesses(hits+misses) @@ -314,17 +399,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.215051 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214982 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.215051 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52089.775561 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52021.930093 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52021.976269 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.763725 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.763725 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52089.775561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52013.886641 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52013.917699 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52089.775561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52013.886641 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52013.917699 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52536.783042 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52505.479976 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52505.501281 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.007679 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.007679 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52536.783042 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52503.297324 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52503.311028 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52536.783042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52503.297324 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52503.311028 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -346,17 +431,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1959663 system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1958861 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1959663 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32152000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47128224000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47160376000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31253418000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31253418000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32152000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78381642000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 78413794000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32152000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78381642000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 78413794000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32510000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47697633000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47730143000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31642696500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31642696500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32510000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79340329500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 79372839500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32510000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79340329500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 79372839500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163042 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163135 # mshr miss rate for ReadReq accesses @@ -368,127 +453,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.215051 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214982 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.215051 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40089.775561 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.930093 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40021.976269 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.763725 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.763725 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40089.775561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40536.159601 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40505.479976 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40505.500856 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.007679 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.007679 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40536.159601 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40503.297324 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.310773 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40536.159601 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40503.297324 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.310773 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9107638 # number of replacements -system.cpu.dcache.tags.tagsinuse 4079.262869 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1238 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2584 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 200 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits -system.cpu.dcache.overall_hits::total 596212431 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses -system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143374726000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143374726000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57377180000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57377180000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200751906000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200751906000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200751906000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200751906000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19851.358009 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19851.358009 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30369.222789 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30369.222789 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22032.239528 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22032.239528 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks -system.cpu.dcache.writebacks::total 3693497 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128929898000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 128929898000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53598540000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53598540000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182528438000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 182528438000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182528438000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 182528438000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17851.358009 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17851.358009 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28369.222789 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28369.222789 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 7223216 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 3693497 # Transaction distribution @@ -518,5 +494,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 1203000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1178362 # Transaction distribution +system.membus.trans_dist::ReadResp 1178362 # Transaction distribution +system.membus.trans_dist::Writeback 1018077 # Transaction distribution +system.membus.trans_dist::ReadExReq 781301 # Transaction distribution +system.membus.trans_dist::ReadExResp 781301 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2977740 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2977740 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2977740 # Request fanout histogram +system.membus.reqLayer0.occupancy 7156873500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 9798315500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 1df40303a..0b1bb03bc 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.108725 # Number of seconds simulated -sim_ticks 1108725388000 # Number of ticks simulated -final_tick 1108725388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.121241 # Number of seconds simulated +sim_ticks 1121241432500 # Number of ticks simulated +final_tick 1121241432500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160331 # Simulator instruction rate (inst/s) -host_op_rate 172733 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115089854 # Simulator tick rate (ticks/s) -host_mem_usage 301444 # Number of bytes of host memory used -host_seconds 9633.56 # Real time elapsed on the host +host_inst_rate 243175 # Simulator instruction rate (inst/s) +host_op_rate 261985 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 176527853 # Simulator tick rate (ticks/s) +host_mem_usage 312356 # Number of bytes of host memory used +host_seconds 6351.64 # Real time elapsed on the host sim_insts 1544563087 # Number of instructions simulated sim_ops 1664032480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 50368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 131507968 # Number of bytes read from this memory -system.physmem.bytes_read::total 131558336 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66970688 # Number of bytes written to this memory -system.physmem.bytes_written::total 66970688 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 787 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2054812 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2055599 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1046417 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046417 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 45429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 118611849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 118657277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 45429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 45429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 60403314 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 60403314 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 60403314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 45429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 118611849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 179060592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2055599 # Number of read requests accepted -system.physmem.writeReqs 1046417 # Number of write requests accepted -system.physmem.readBursts 2055599 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1046417 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 131472320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 86016 # Total number of bytes read from write queue -system.physmem.bytesWritten 66969088 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131558336 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66970688 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1344 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 50560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 131525952 # Number of bytes read from this memory +system.physmem.bytes_read::total 131576512 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50560 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 66977984 # Number of bytes written to this memory +system.physmem.bytes_written::total 66977984 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 790 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2055093 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2055883 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046531 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046531 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 45093 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117303864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 117348956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 45093 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 45093 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 59735559 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 59735559 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 59735559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 45093 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117303864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 177084516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2055883 # Number of read requests accepted +system.physmem.writeReqs 1046531 # Number of write requests accepted +system.physmem.readBursts 2055883 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1046531 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 131490688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 85824 # Total number of bytes read from write queue +system.physmem.bytesWritten 66976384 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131576512 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66977984 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1341 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127971 # Per bank write bursts -system.physmem.perBankRdBursts::1 125115 # Per bank write bursts -system.physmem.perBankRdBursts::2 122192 # Per bank write bursts -system.physmem.perBankRdBursts::3 124223 # Per bank write bursts -system.physmem.perBankRdBursts::4 123351 # Per bank write bursts -system.physmem.perBankRdBursts::5 123340 # Per bank write bursts -system.physmem.perBankRdBursts::6 123758 # Per bank write bursts -system.physmem.perBankRdBursts::7 124120 # Per bank write bursts -system.physmem.perBankRdBursts::8 131994 # Per bank write bursts -system.physmem.perBankRdBursts::9 134060 # Per bank write bursts -system.physmem.perBankRdBursts::10 132574 # Per bank write bursts -system.physmem.perBankRdBursts::11 133683 # Per bank write bursts -system.physmem.perBankRdBursts::12 133864 # Per bank write bursts -system.physmem.perBankRdBursts::13 133891 # Per bank write bursts -system.physmem.perBankRdBursts::14 129793 # Per bank write bursts -system.physmem.perBankRdBursts::15 130326 # Per bank write bursts -system.physmem.perBankWrBursts::0 65785 # Per bank write bursts -system.physmem.perBankWrBursts::1 64106 # Per bank write bursts -system.physmem.perBankWrBursts::2 62369 # Per bank write bursts -system.physmem.perBankWrBursts::3 62872 # Per bank write bursts -system.physmem.perBankWrBursts::4 62855 # Per bank write bursts -system.physmem.perBankWrBursts::5 62943 # Per bank write bursts -system.physmem.perBankWrBursts::6 64256 # Per bank write bursts -system.physmem.perBankWrBursts::7 65177 # Per bank write bursts -system.physmem.perBankWrBursts::8 67064 # Per bank write bursts -system.physmem.perBankWrBursts::9 67603 # Per bank write bursts -system.physmem.perBankWrBursts::10 67361 # Per bank write bursts -system.physmem.perBankWrBursts::11 67637 # Per bank write bursts -system.physmem.perBankWrBursts::12 67067 # Per bank write bursts -system.physmem.perBankWrBursts::13 67487 # Per bank write bursts -system.physmem.perBankWrBursts::14 66154 # Per bank write bursts -system.physmem.perBankWrBursts::15 65656 # Per bank write bursts +system.physmem.perBankRdBursts::0 127988 # Per bank write bursts +system.physmem.perBankRdBursts::1 125250 # Per bank write bursts +system.physmem.perBankRdBursts::2 122092 # Per bank write bursts +system.physmem.perBankRdBursts::3 124158 # Per bank write bursts +system.physmem.perBankRdBursts::4 123330 # Per bank write bursts +system.physmem.perBankRdBursts::5 123315 # Per bank write bursts +system.physmem.perBankRdBursts::6 123951 # Per bank write bursts +system.physmem.perBankRdBursts::7 124319 # Per bank write bursts +system.physmem.perBankRdBursts::8 132052 # Per bank write bursts +system.physmem.perBankRdBursts::9 134015 # Per bank write bursts +system.physmem.perBankRdBursts::10 132327 # Per bank write bursts +system.physmem.perBankRdBursts::11 133706 # Per bank write bursts +system.physmem.perBankRdBursts::12 133817 # Per bank write bursts +system.physmem.perBankRdBursts::13 133969 # Per bank write bursts +system.physmem.perBankRdBursts::14 129938 # Per bank write bursts +system.physmem.perBankRdBursts::15 130315 # Per bank write bursts +system.physmem.perBankWrBursts::0 65788 # Per bank write bursts +system.physmem.perBankWrBursts::1 64148 # Per bank write bursts +system.physmem.perBankWrBursts::2 62323 # Per bank write bursts +system.physmem.perBankWrBursts::3 62858 # Per bank write bursts +system.physmem.perBankWrBursts::4 62842 # Per bank write bursts +system.physmem.perBankWrBursts::5 62926 # Per bank write bursts +system.physmem.perBankWrBursts::6 64344 # Per bank write bursts +system.physmem.perBankWrBursts::7 65270 # Per bank write bursts +system.physmem.perBankWrBursts::8 67114 # Per bank write bursts +system.physmem.perBankWrBursts::9 67597 # Per bank write bursts +system.physmem.perBankWrBursts::10 67253 # Per bank write bursts +system.physmem.perBankWrBursts::11 67655 # Per bank write bursts +system.physmem.perBankWrBursts::12 67032 # Per bank write bursts +system.physmem.perBankWrBursts::13 67505 # Per bank write bursts +system.physmem.perBankWrBursts::14 66189 # Per bank write bursts +system.physmem.perBankWrBursts::15 65662 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1108725299500 # Total gap between requests +system.physmem.totGap 1121241338000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2055599 # Read request sizes (log2) +system.physmem.readPktSize::6 2055883 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1046417 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1922438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 131799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1046531 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1926751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -193,104 +193,105 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1917383 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.495400 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.766538 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.134212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1491936 77.81% 77.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 306042 15.96% 93.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52771 2.75% 96.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21239 1.11% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13137 0.69% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7295 0.38% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5316 0.28% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4195 0.22% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15452 0.81% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1917383 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60970 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.645219 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 157.122880 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60927 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1919691 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.383938 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.729389 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 124.654868 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1494811 77.87% 77.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305161 15.90% 93.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53151 2.77% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21323 1.11% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13050 0.68% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7398 0.39% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5428 0.28% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5020 0.26% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14349 0.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1919691 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60985 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.641650 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 160.664141 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60945 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 9 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60970 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60970 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.162408 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.127431 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.097398 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27276 44.74% 44.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1165 1.91% 46.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28420 46.61% 93.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3653 5.99% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 385 0.63% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 61 0.10% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 7 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60970 # Writes before turning the bus around for reads -system.physmem.totQLat 38268969000 # Total ticks spent queuing -system.physmem.totMemAccLat 76786250250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10271275000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18629.12 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 60985 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60985 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.160056 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.125150 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.096252 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27287 44.74% 44.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1323 2.17% 46.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28176 46.20% 93.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3806 6.24% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 330 0.54% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 51 0.08% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 9 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60985 # Writes before turning the bus around for reads +system.physmem.totQLat 38434565750 # Total ticks spent queuing +system.physmem.totMemAccLat 76957228250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10272710000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18707.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37379.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 118.58 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 60.40 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 118.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 60.40 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37457.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 117.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 59.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 117.35 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 59.74 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.40 # Data bus utilization in percentage -system.physmem.busUtilRead 0.93 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.38 # Data bus utilization in percentage +system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.62 # Average write queue length when enqueuing -system.physmem.readRowHits 776845 # Number of row buffer hits during reads -system.physmem.writeRowHits 406412 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.84 # Row buffer hit rate for writes -system.physmem.avgGap 357420.88 # Average gap between requests -system.physmem.pageHitRate 38.16 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7070973840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3858170250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7753512000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3307152240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 72416401200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 416204777970 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 300142086750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 810753074250 # Total energy per rank (pJ) -system.physmem_0.averagePower 731.249224 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 496624730250 # Time in different power states -system.physmem_0.memoryStateTime::REF 37022700000 # Time in different power states +system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing +system.physmem.readRowHits 774810 # Number of row buffer hits during reads +system.physmem.writeRowHits 406537 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.85 # Row buffer hit rate for writes +system.physmem.avgGap 361409.32 # Average gap between requests +system.physmem.pageHitRate 38.09 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7080832080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3863549250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7756031400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3308033520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 73233657120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 422818284195 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 301848259500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 819908647065 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.254419 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 499427924250 # Time in different power states +system.physmem_0.memoryStateTime::REF 37440520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 575075912250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 584369735750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7424434080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4051030500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8269419600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3473467920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 72416401200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 425140731810 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 292303530750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 813079015860 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.347080 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 483537101750 # Time in different power states -system.physmem_1.memoryStateTime::REF 37022700000 # Time in different power states +system.physmem_1.actEnergy 7432016760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4055167875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8269029600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3473325360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 73233657120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 431345081205 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 294368613000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 822176890920 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.277404 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 486933261750 # Time in different power states +system.physmem_1.memoryStateTime::REF 37440520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 588165429250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 596864300250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 240158127 # Number of BP lookups -system.cpu.branchPred.condPredicted 186758642 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14604059 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 133657061 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122306338 # Number of BTB hits +system.cpu.branchPred.lookups 240141363 # Number of BP lookups +system.cpu.branchPred.condPredicted 186745178 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14595264 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132286201 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122283419 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.507577 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15659556 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.438530 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15659523 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -410,90 +411,90 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2217450776 # number of cpu cycles simulated +system.cpu.numCycles 2242482865 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563087 # Number of instructions committed system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed -system.cpu.discardedOps 40093383 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 40063389 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.435649 # CPI: cycles per instruction -system.cpu.ipc 0.696549 # IPC: instructions per cycle -system.cpu.tickCycles 1838812013 # Number of cycles that the object actually ticked -system.cpu.idleCycles 378638763 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9223724 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.606596 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624087400 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9227820 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.631076 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 9776044000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.606596 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997463 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997463 # Average percentage of cache occupancy +system.cpu.cpi 1.451856 # CPI: cycles per instruction +system.cpu.ipc 0.688774 # IPC: instructions per cycle +system.cpu.tickCycles 1838984641 # Number of cycles that the object actually ticked +system.cpu.idleCycles 403498224 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9223361 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.642530 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624067003 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9227457 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.631527 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9813070000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.642530 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997471 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997471 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1296 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2482 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1217 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276555670 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276555670 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 453740634 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453740634 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170346644 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170346644 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1276544027 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276544027 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 453735354 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453735354 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170331527 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170331527 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624087278 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624087278 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624087278 # number of overall hits -system.cpu.dcache.overall_hits::total 624087278 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7337122 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7337122 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2239403 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2239403 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9576525 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9576525 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9576525 # number of overall misses -system.cpu.dcache.overall_misses::total 9576525 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 183400270746 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 183400270746 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 101399706750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 101399706750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 284799977496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 284799977496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 284799977496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 284799977496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461077756 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461077756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 624066881 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624066881 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624066881 # number of overall hits +system.cpu.dcache.overall_hits::total 624066881 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7336762 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7336762 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2254520 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2254520 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9591282 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9591282 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9591282 # number of overall misses +system.cpu.dcache.overall_misses::total 9591282 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 192442349996 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 192442349996 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 109711138250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 109711138250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 302153488246 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 302153488246 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 302153488246 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 302153488246 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461072116 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461072116 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 633663803 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633663803 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 633663803 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633663803 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015913 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012976 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012976 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015113 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015113 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015113 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015113 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24996.213876 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24996.213876 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45279.794101 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45279.794101 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29739.386416 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29739.386416 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29739.386416 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29739.386416 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 633658163 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633658163 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633658163 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633658163 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015912 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015912 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013063 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013063 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015136 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015136 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015136 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015136 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26229.874977 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26229.874977 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48662.747835 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48662.747835 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31502.930291 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31502.930291 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31502.930291 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31502.930291 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,101 +503,101 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3701129 # number of writebacks -system.cpu.dcache.writebacks::total 3701129 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 221 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 348484 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 348484 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 348705 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 348705 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 348705 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 348705 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336901 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7336901 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890919 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890919 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9227820 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9227820 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9227820 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9227820 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168309061254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 168309061254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77322111500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77322111500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245631172754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 245631172754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245631172754 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 245631172754 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015913 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 3701040 # number of writebacks +system.cpu.dcache.writebacks::total 3701040 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 208 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 363617 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 363617 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 363825 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 363825 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 363825 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 363825 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336554 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7336554 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890903 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890903 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9227457 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9227457 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9227457 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9227457 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 181020888504 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 181020888504 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83976849000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83976849000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264997737504 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 264997737504 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264997737504 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 264997737504 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015912 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015912 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014563 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014563 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22940.075279 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22940.075279 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40891.286988 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40891.286988 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26618.548341 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26618.548341 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24673.830317 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24673.830317 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44410.976660 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44410.976660 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28718.393107 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28718.393107 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28718.393107 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28718.393107 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.tagsinuse 661.153981 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466170177 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 568500.215854 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 32 # number of replacements +system.cpu.icache.tags.tagsinuse 661.433391 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466139352 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 566390.464156 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 661.153981 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322829 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322829 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 661.433391 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322966 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322966 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932342814 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932342814 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 466170177 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961118 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.222715 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.222781 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961118 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.222715 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.222781 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77102.402023 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87510.692856 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 87504.136601 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88193.858129 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88193.858129 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77102.402023 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87776.681587 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87772.574673 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77102.402023 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87776.681587 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87772.574673 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -730,8 +731,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1046417 # number of writebacks -system.cpu.l2cache.writebacks::total 1046417 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1046531 # number of writebacks +system.cpu.l2cache.writebacks::total 1046531 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits @@ -741,107 +742,105 @@ system.cpu.l2cache.demand_mshr_hits::total 5 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 787 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1254716 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1255503 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 800096 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 800096 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2054812 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2055599 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2054812 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2055599 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 45360250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 84287306750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84332667000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54391877500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54391877500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 45360250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 138679184250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 138724544500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 45360250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 138679184250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 138724544500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171014 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171103 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222676 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.222741 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222676 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.222741 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57636.912325 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67176.402270 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67170.422532 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67981.689072 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67981.689072 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57636.912325 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67489.962220 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57636.912325 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67489.962220 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 790 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1254946 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1255736 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 800147 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 800147 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 790 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2055093 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2055883 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 790 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2055093 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2055883 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51087500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 93955002000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94006089500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60459125500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60459125500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51087500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154414127500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 154465215000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51087500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154414127500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 154465215000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171054 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171142 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423156 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423156 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222715 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.222781 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222715 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.222781 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64667.721519 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74867.764828 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74861.347847 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75560.022721 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75560.022721 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64667.721519 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75137.294273 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75133.271203 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64667.721519 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75137.294273 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75133.271203 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7337721 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7337721 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3701129 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890919 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890919 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22156769 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22158409 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827452736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 827505216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7337377 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7337377 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3701040 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890903 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890903 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1646 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22155954 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22157600 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827423808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 827476480 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12929769 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12929320 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 12929769 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 12929320 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12929769 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10166013500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12929320 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10165700000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1389749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1400999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14186681246 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14190167496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1255503 # Transaction distribution -system.membus.trans_dist::ReadResp 1255503 # Transaction distribution -system.membus.trans_dist::Writeback 1046417 # Transaction distribution -system.membus.trans_dist::ReadExReq 800096 # Transaction distribution -system.membus.trans_dist::ReadExResp 800096 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157615 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5157615 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198529024 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198529024 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1255736 # Transaction distribution +system.membus.trans_dist::ReadResp 1255736 # Transaction distribution +system.membus.trans_dist::Writeback 1046531 # Transaction distribution +system.membus.trans_dist::ReadExReq 800147 # Transaction distribution +system.membus.trans_dist::ReadExResp 800147 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5158297 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5158297 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198554496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198554496 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3102016 # Request fanout histogram +system.membus.snoop_fanout::samples 3102414 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3102016 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3102414 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3102016 # Request fanout histogram -system.membus.reqLayer0.occupancy 12126859000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 19430032500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.8 # Layer utilization (%) +system.membus.snoop_fanout::total 3102414 # Request fanout histogram +system.membus.reqLayer0.occupancy 7944829000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 11243795500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 2039a5a26..d3007a8e0 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.756343 # Number of seconds simulated -sim_ticks 756342731500 # Number of ticks simulated -final_tick 756342731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.771783 # Number of seconds simulated +sim_ticks 771782683000 # Number of ticks simulated +final_tick 771782683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137786 # Simulator instruction rate (inst/s) -host_op_rate 148444 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67471289 # Simulator tick rate (ticks/s) -host_mem_usage 311496 # Number of bytes of host memory used -host_seconds 11209.85 # Real time elapsed on the host +host_inst_rate 141348 # Simulator instruction rate (inst/s) +host_op_rate 152281 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 70628369 # Simulator tick rate (ticks/s) +host_mem_usage 310548 # Number of bytes of host memory used +host_seconds 10927.38 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1664032415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 66304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 238887296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63148480 # Number of bytes read from this memory -system.physmem.bytes_read::total 302102080 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 66304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 66304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104863424 # Number of bytes written to this memory -system.physmem.bytes_written::total 104863424 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1036 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3732614 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 986695 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4720345 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1638491 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1638491 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 87664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 315845299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 83491885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 399424847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 87664 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 87664 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 138645378 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 138645378 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 138645378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 87664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 315845299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 83491885 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 538070225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4720345 # Number of read requests accepted -system.physmem.writeReqs 1638491 # Number of write requests accepted -system.physmem.readBursts 4720345 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1638491 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 301644480 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 457600 # Total number of bytes read from write queue -system.physmem.bytesWritten 104860480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 302102080 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104863424 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7150 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 20 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 66112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 238756480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63336128 # Number of bytes read from this memory +system.physmem.bytes_read::total 302158720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 66112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 66112 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104900608 # Number of bytes written to this memory +system.physmem.bytes_written::total 104900608 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1033 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3730570 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 989627 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4721230 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1639072 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1639072 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 85661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309357135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82064718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 391507515 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 85661 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 85661 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 135919878 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 135919878 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 135919878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 85661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309357135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82064718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 527427392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4721230 # Number of read requests accepted +system.physmem.writeReqs 1639072 # Number of write requests accepted +system.physmem.readBursts 4721230 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1639072 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 301708544 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 450176 # Total number of bytes read from write queue +system.physmem.bytesWritten 104898432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 302158720 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104900608 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7034 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 296862 # Per bank write bursts -system.physmem.perBankRdBursts::1 294626 # Per bank write bursts -system.physmem.perBankRdBursts::2 288270 # Per bank write bursts -system.physmem.perBankRdBursts::3 292812 # Per bank write bursts -system.physmem.perBankRdBursts::4 290199 # Per bank write bursts -system.physmem.perBankRdBursts::5 289793 # Per bank write bursts -system.physmem.perBankRdBursts::6 284872 # Per bank write bursts -system.physmem.perBankRdBursts::7 281493 # Per bank write bursts -system.physmem.perBankRdBursts::8 297311 # Per bank write bursts -system.physmem.perBankRdBursts::9 303290 # Per bank write bursts -system.physmem.perBankRdBursts::10 295469 # Per bank write bursts -system.physmem.perBankRdBursts::11 301855 # Per bank write bursts -system.physmem.perBankRdBursts::12 303298 # Per bank write bursts -system.physmem.perBankRdBursts::13 302373 # Per bank write bursts -system.physmem.perBankRdBursts::14 297652 # Per bank write bursts -system.physmem.perBankRdBursts::15 293020 # Per bank write bursts -system.physmem.perBankWrBursts::0 104131 # Per bank write bursts -system.physmem.perBankWrBursts::1 101826 # Per bank write bursts -system.physmem.perBankWrBursts::2 99098 # Per bank write bursts -system.physmem.perBankWrBursts::3 99979 # Per bank write bursts -system.physmem.perBankWrBursts::4 99438 # Per bank write bursts -system.physmem.perBankWrBursts::5 99115 # Per bank write bursts -system.physmem.perBankWrBursts::6 102674 # Per bank write bursts -system.physmem.perBankWrBursts::7 104427 # Per bank write bursts -system.physmem.perBankWrBursts::8 105209 # Per bank write bursts -system.physmem.perBankWrBursts::9 104570 # Per bank write bursts -system.physmem.perBankWrBursts::10 102342 # Per bank write bursts -system.physmem.perBankWrBursts::11 102683 # Per bank write bursts -system.physmem.perBankWrBursts::12 102787 # Per bank write bursts -system.physmem.perBankWrBursts::13 102808 # Per bank write bursts -system.physmem.perBankWrBursts::14 104630 # Per bank write bursts -system.physmem.perBankWrBursts::15 102728 # Per bank write bursts +system.physmem.perBankRdBursts::0 296496 # Per bank write bursts +system.physmem.perBankRdBursts::1 294922 # Per bank write bursts +system.physmem.perBankRdBursts::2 288553 # Per bank write bursts +system.physmem.perBankRdBursts::3 293200 # Per bank write bursts +system.physmem.perBankRdBursts::4 290519 # Per bank write bursts +system.physmem.perBankRdBursts::5 289057 # Per bank write bursts +system.physmem.perBankRdBursts::6 284695 # Per bank write bursts +system.physmem.perBankRdBursts::7 280747 # Per bank write bursts +system.physmem.perBankRdBursts::8 297891 # Per bank write bursts +system.physmem.perBankRdBursts::9 303659 # Per bank write bursts +system.physmem.perBankRdBursts::10 295750 # Per bank write bursts +system.physmem.perBankRdBursts::11 302488 # Per bank write bursts +system.physmem.perBankRdBursts::12 303486 # Per bank write bursts +system.physmem.perBankRdBursts::13 302338 # Per bank write bursts +system.physmem.perBankRdBursts::14 297681 # Per bank write bursts +system.physmem.perBankRdBursts::15 292714 # Per bank write bursts +system.physmem.perBankWrBursts::0 104090 # Per bank write bursts +system.physmem.perBankWrBursts::1 102136 # Per bank write bursts +system.physmem.perBankWrBursts::2 99204 # Per bank write bursts +system.physmem.perBankWrBursts::3 100079 # Per bank write bursts +system.physmem.perBankWrBursts::4 99319 # Per bank write bursts +system.physmem.perBankWrBursts::5 99058 # Per bank write bursts +system.physmem.perBankWrBursts::6 102867 # Per bank write bursts +system.physmem.perBankWrBursts::7 104266 # Per bank write bursts +system.physmem.perBankWrBursts::8 105488 # Per bank write bursts +system.physmem.perBankWrBursts::9 104503 # Per bank write bursts +system.physmem.perBankWrBursts::10 102301 # Per bank write bursts +system.physmem.perBankWrBursts::11 102956 # Per bank write bursts +system.physmem.perBankWrBursts::12 103260 # Per bank write bursts +system.physmem.perBankWrBursts::13 102520 # Per bank write bursts +system.physmem.perBankWrBursts::14 104484 # Per bank write bursts +system.physmem.perBankWrBursts::15 102507 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 756342591500 # Total gap between requests +system.physmem.totGap 771782536000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4720345 # Read request sizes (log2) +system.physmem.readPktSize::6 4721230 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1638491 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2764600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1036830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 329452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 239558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 162691 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 91104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 40419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 17706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1653 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1639072 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2775597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1044443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 331745 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 234202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 153941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 85295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 39428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23872 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 434 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,38 +148,38 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 59650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 74848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 84172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 91913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 98459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 106253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 107840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 108834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 109988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 110978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 113431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 107071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 104798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 103128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 22873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 60114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 75847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 99435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 106485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 107133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 110847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 113228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 106323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 103422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -197,123 +197,121 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4285614 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.853108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.948636 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 101.693693 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3410667 79.58% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 676414 15.78% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 97051 2.26% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35005 0.82% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22710 0.53% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12276 0.29% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7200 0.17% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5155 0.12% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19136 0.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4285614 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 98802 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.703225 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 32.303831 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 97.301104 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-127 94981 96.13% 96.13% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-255 1362 1.38% 97.51% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-383 759 0.77% 98.28% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::384-511 434 0.44% 98.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-639 380 0.38% 99.10% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::640-767 348 0.35% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-895 273 0.28% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::896-1023 148 0.15% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1151 67 0.07% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1152-1279 20 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1407 9 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1408-1535 8 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1663 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 4289012 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.801701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.923105 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 101.558340 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3414847 79.62% 79.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 675748 15.76% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 96615 2.25% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35482 0.83% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22807 0.53% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12154 0.28% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7173 0.17% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5164 0.12% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19022 0.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4289012 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 98837 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.696531 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 32.309771 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 98.301255 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-127 95044 96.16% 96.16% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-255 1344 1.36% 97.52% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-383 770 0.78% 98.30% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::384-511 419 0.42% 98.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-639 374 0.38% 99.10% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::640-767 356 0.36% 99.46% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-895 254 0.26% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::896-1023 146 0.15% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1151 62 0.06% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1152-1279 41 0.04% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1407 8 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1408-1535 7 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1663 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-1919 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1920-2047 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2176-2303 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2432-2559 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2687 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2688-2815 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2816-2943 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 98802 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 98802 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.583116 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.550078 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.089696 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 73349 74.24% 74.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1793 1.81% 76.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18295 18.52% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3696 3.74% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 920 0.93% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 398 0.40% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 161 0.16% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 94 0.10% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 50 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 24 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 14 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 98802 # Writes before turning the bus around for reads -system.physmem.totQLat 132475907765 # Total ticks spent queuing -system.physmem.totMemAccLat 220848314015 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23565975000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28107.45 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::2304-2431 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2687 3 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2944-3071 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3200-3327 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-3711 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 98837 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 98837 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.583243 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.550199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.089458 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 73410 74.27% 74.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1674 1.69% 75.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18461 18.68% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3603 3.65% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 928 0.94% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 388 0.39% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 174 0.18% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 100 0.10% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 61 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 27 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 7 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 98837 # Writes before turning the bus around for reads +system.physmem.totQLat 132409571838 # Total ticks spent queuing +system.physmem.totMemAccLat 220800746838 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23570980000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28087.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46857.45 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 398.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 138.64 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 399.42 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 138.65 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46837.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 390.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 135.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 391.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 135.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.20 # Data bus utilization in percentage -system.physmem.busUtilRead 3.12 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.08 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing -system.physmem.readRowHits 1712938 # Number of row buffer hits during reads -system.physmem.writeRowHits 353078 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.55 # Row buffer hit rate for writes -system.physmem.avgGap 118943.56 # Average gap between requests -system.physmem.pageHitRate 32.53 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 16066436400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8766408750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18087404400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5253193440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 49400501280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 400853320515 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 102178887750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 600606152535 # Total energy per rank (pJ) -system.physmem_0.averagePower 794.094387 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 167492103071 # Time in different power states -system.physmem_0.memoryStateTime::REF 25255880000 # Time in different power states +system.physmem.busUtil 4.12 # Data bus utilization in percentage +system.physmem.busUtilRead 3.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing +system.physmem.readRowHits 1710867 # Number of row buffer hits during reads +system.physmem.writeRowHits 353347 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 21.56 # Row buffer hit rate for writes +system.physmem.avgGap 121343.69 # Average gap between requests +system.physmem.pageHitRate 32.49 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 16078381200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8772926250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18081671400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5255351280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50408975760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 410988240855 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 102552687000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 612138233745 # Total energy per rank (pJ) +system.physmem_0.averagePower 793.150023 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 168058001250 # Time in different power states +system.physmem_0.memoryStateTime::REF 25771460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 563593117929 # Time in different power states +system.physmem_0.memoryStateTime::ACT 577951698750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16332729840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8911707750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18675259200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5363826480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 49400501280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 402415744095 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 100808340750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 601908109395 # Total energy per rank (pJ) -system.physmem_1.averagePower 795.815775 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 165215512876 # Time in different power states -system.physmem_1.memoryStateTime::REF 25255880000 # Time in different power states +system.physmem_1.actEnergy 16346489040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8919215250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18688846800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5365504800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50408975760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 412404849315 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 101310048000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 613443928965 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.841817 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 165993972457 # Time in different power states +system.physmem_1.memoryStateTime::REF 25771460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 565869633374 # Time in different power states +system.physmem_1.memoryStateTime::ACT 580015821043 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 286251205 # Number of BP lookups -system.cpu.branchPred.condPredicted 223383370 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14630986 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158738952 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150334108 # Number of BTB hits +system.cpu.branchPred.lookups 286268512 # Number of BP lookups +system.cpu.branchPred.condPredicted 223399208 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14631885 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157652290 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150341382 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.705242 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16640646 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.362638 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16641174 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 65 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -432,233 +430,233 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1512685464 # number of cpu cycles simulated +system.cpu.numCycles 1543565367 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13925295 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067334861 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286251205 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166974754 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1484044715 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29286501 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 170 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 1090 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656878260 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 961 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1512614520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.464203 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.224459 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13925779 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067423618 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286268512 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166982556 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1514915602 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29288421 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 919 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656914213 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 942 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1543486763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.434983 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229356 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 430302331 28.45% 28.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465370544 30.77% 59.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101420857 6.71% 65.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515520788 34.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 461116597 29.87% 29.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465422138 30.15% 60.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101389056 6.57% 66.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515558972 33.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1512614520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.189234 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.366665 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74740374 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 515177494 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849893259 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58160845 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14642548 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42195150 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 750 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2036986769 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52385989 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14642548 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139815435 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 436624028 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12701 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837804287 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 83715521 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976173031 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26689335 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45146280 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 125414 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1394915 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 22818803 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985649062 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9127137269 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432583454 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 143 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1543486763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185459 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.339382 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74615169 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 546131714 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 850052649 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58043724 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14643507 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42202613 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 760 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037139109 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52472329 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14643507 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139680975 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 464946049 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14177 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837873228 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 86328827 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976320354 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26732336 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45128593 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 125639 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1500891 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25518898 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985788047 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9127865226 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432787425 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 124 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310750117 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 155 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 146 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111721700 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542489680 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199288909 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26826914 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28715919 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947778041 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 214 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857580897 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13541153 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 279193675 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 645796508 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1512614520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.228060 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150014 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 310889102 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 151 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 141 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111344488 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542536301 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199301557 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26908887 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29198248 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947883742 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 210 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857409514 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13500100 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 279518916 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 646881302 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1543486763 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.203385 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.151093 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 560160519 37.03% 37.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 325201183 21.50% 58.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378431439 25.02% 83.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219774852 14.53% 98.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29040355 1.92% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6172 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 590762659 38.27% 38.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 325764931 21.11% 59.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378272466 24.51% 83.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219653351 14.23% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29027182 1.88% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6174 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1512614520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1543486763 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166509117 41.02% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1974 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191277328 47.12% 88.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 48123931 11.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166053840 40.99% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1992 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191416352 47.25% 88.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47630536 11.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138363415 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 801029 0.04% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532094788 28.64% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186321614 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138248479 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 801009 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 26 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532044411 28.64% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186315567 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857580897 # Type of FU issued -system.cpu.iq.rate 1.228002 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405912350 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218517 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5647229580 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2226984572 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805831958 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2263493115 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 132 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17832338 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857409514 # Type of FU issued +system.cpu.iq.rate 1.203324 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405102720 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218101 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5676908390 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2227415601 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805707256 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 208 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262512110 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 124 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17814082 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84183346 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66238 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13114 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24441864 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84229967 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66402 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13168 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24454512 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4579390 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4849629 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4520775 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4802645 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14642548 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25281228 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1183865 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947778336 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14643507 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25316113 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1330365 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947884031 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542489680 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199288909 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 152 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 158613 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1024253 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13114 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7709445 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8723908 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16433353 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827918594 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516926976 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29662303 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542536301 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199301557 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 148 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 158933 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1170467 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13168 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7700956 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8705023 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16405979 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827745758 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516865735 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29663756 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 81 # number of nop insts executed -system.cpu.iew.exec_refs 698686621 # number of memory reference insts executed -system.cpu.iew.exec_branches 229598858 # Number of branches executed -system.cpu.iew.exec_stores 181759645 # Number of stores executed -system.cpu.iew.exec_rate 1.208393 # Inst execution rate -system.cpu.iew.wb_sent 1808851456 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805832027 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169265268 # num instructions producing a value -system.cpu.iew.wb_consumers 1689455879 # num instructions consuming a value +system.cpu.iew.exec_nop 79 # number of nop insts executed +system.cpu.iew.exec_refs 698617938 # number of memory reference insts executed +system.cpu.iew.exec_branches 229554698 # Number of branches executed +system.cpu.iew.exec_stores 181752203 # Number of stores executed +system.cpu.iew.exec_rate 1.184106 # Inst execution rate +system.cpu.iew.wb_sent 1808737138 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805707322 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169287953 # num instructions producing a value +system.cpu.iew.wb_consumers 1689671414 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.193792 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692096 # average fanout of values written-back +system.cpu.iew.wb_rate 1.169829 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692021 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 257820227 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 257958644 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14630284 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1473146552 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.129577 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.040655 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14631182 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1504006174 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.106400 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.024308 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 893288218 60.64% 60.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250810214 17.03% 77.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 109558722 7.44% 85.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55058301 3.74% 88.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29206870 1.98% 90.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 33934631 2.30% 93.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24884814 1.69% 94.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18117903 1.23% 96.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58286879 3.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 923727407 61.42% 61.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250637926 16.66% 78.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110048306 7.32% 85.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55269063 3.67% 89.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29308073 1.95% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34102690 2.27% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24713726 1.64% 94.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18129256 1.21% 96.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58069727 3.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1473146552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1504006174 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -704,77 +702,77 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction -system.cpu.commit.bw_lim_events 58286879 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 58069727 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3336711734 # The number of ROB reads -system.cpu.rob.rob_writes 3883178493 # The number of ROB writes -system.cpu.timesIdled 871 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 70944 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3367926925 # The number of ROB reads +system.cpu.rob.rob_writes 3883468057 # The number of ROB writes +system.cpu.timesIdled 846 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 78604 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.979361 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.979361 # CPI: Total CPI of All Threads -system.cpu.ipc 1.021073 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.021073 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175874054 # number of integer regfile reads -system.cpu.int_regfile_writes 1261590215 # number of integer regfile writes +system.cpu.cpi 0.999354 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.999354 # CPI: Total CPI of All Threads +system.cpu.ipc 1.000646 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.000646 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175695472 # number of integer regfile reads +system.cpu.int_regfile_writes 1261559121 # number of integer regfile writes system.cpu.fp_regfile_reads 38 # number of floating regfile reads -system.cpu.fp_regfile_writes 51 # number of floating regfile writes -system.cpu.cc_regfile_reads 6966029517 # number of cc regfile reads -system.cpu.cc_regfile_writes 551971474 # number of cc regfile writes -system.cpu.misc_regfile_reads 675853074 # number of misc regfile reads +system.cpu.fp_regfile_writes 48 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965502930 # number of cc regfile reads +system.cpu.cc_regfile_writes 551873305 # number of cc regfile writes +system.cpu.misc_regfile_reads 675842878 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.replacements 17007297 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.963762 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638259274 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17007809 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.527425 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 79888000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.963762 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999929 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999929 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 17005493 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964646 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638183172 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17006005 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.526931 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 79063000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964646 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 405 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 392 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335624835 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335624835 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469463783 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469463783 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168795373 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168795373 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335677307 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335677307 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469397613 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469397613 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168785441 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168785441 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638259156 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638259156 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638259156 # number of overall hits -system.cpu.dcache.overall_hits::total 638259156 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17258559 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17258559 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3790674 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3790674 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638183054 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638183054 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638183054 # number of overall hits +system.cpu.dcache.overall_hits::total 638183054 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17351867 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17351867 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3800606 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3800606 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21049233 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21049233 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21049235 # number of overall misses -system.cpu.dcache.overall_misses::total 21049235 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 392276819281 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 392276819281 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 143202458834 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 143202458834 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 535479278115 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 535479278115 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 535479278115 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 535479278115 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486722342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486722342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21152473 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21152473 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21152475 # number of overall misses +system.cpu.dcache.overall_misses::total 21152475 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 417182903209 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 417182903209 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 149917932873 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 149917932873 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 358750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 358750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 567100836082 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 567100836082 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 567100836082 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 567100836082 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486749480 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486749480 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -783,421 +781,419 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659308389 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659308389 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659308391 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659308391 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035459 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035459 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.021964 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.021964 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659335527 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659335527 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659335529 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659335529 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035648 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035648 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022022 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022022 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.031926 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.031926 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.031926 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.031926 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22729.407437 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22729.407437 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37777.571702 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37777.571702 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25439.372452 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25439.372452 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25439.370035 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25439.370035 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 19976216 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2938205 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1014245 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 66761 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.695651 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 44.010800 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.032082 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032082 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032082 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032082 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24042.536933 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24042.536933 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39445.797032 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39445.797032 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 89687.500000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 89687.500000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26810.143480 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26810.143480 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26810.140945 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26810.140945 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20723795 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3315809 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 944207 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67033 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.948360 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49.465323 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 4837992 # number of writebacks -system.cpu.dcache.writebacks::total 4837992 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2988204 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2988204 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1053221 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1053221 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 4835251 # number of writebacks +system.cpu.dcache.writebacks::total 4835251 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3083373 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3083373 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1063096 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1063096 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4041425 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4041425 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4041425 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4041425 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14270355 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14270355 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737453 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737453 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4146469 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4146469 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4146469 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4146469 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14268494 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14268494 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737510 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737510 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17007808 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17007808 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17007809 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17007809 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 303479537034 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 303479537034 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 110174073244 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 110174073244 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 413653610278 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 413653610278 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 413653672278 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 413653672278 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029319 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029319 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015861 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015861 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 17006004 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17006004 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17006005 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17006005 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 329072767985 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 329072767985 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115107857313 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 115107857313 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 67750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 67750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 444180625298 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 444180625298 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 444180693048 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 444180693048 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029314 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029314 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025796 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025796 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025796 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025796 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21266.432197 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21266.432197 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40246.927799 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40246.927799 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24321.394637 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24321.394637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24321.396852 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24321.396852 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025793 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025793 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23062.894233 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23062.894233 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42048.378750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42048.378750 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67750 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67750 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26119.047443 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26119.047443 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26119.049891 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26119.049891 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 591 # number of replacements -system.cpu.icache.tags.tagsinuse 445.749905 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656876635 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1079 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 608782.794254 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 588 # number of replacements +system.cpu.icache.tags.tagsinuse 446.068543 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656912599 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1076 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 610513.567844 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 445.749905 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.870605 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.870605 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 446.068543 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.871228 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.871228 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313757597 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313757597 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656876635 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656876635 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656876635 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656876635 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656876635 # number of overall hits -system.cpu.icache.overall_hits::total 656876635 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1624 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1624 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1624 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1624 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1624 # number of overall misses -system.cpu.icache.overall_misses::total 1624 # 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number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1612 # number of overall misses +system.cpu.icache.overall_misses::total 1612 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 102924516 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 102924516 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 102924516 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 102924516 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 102924516 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 102924516 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656914211 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656914211 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656914211 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656914211 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656914211 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656914211 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58610.060345 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 58610.060345 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 58610.060345 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 58610.060345 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 58610.060345 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 58610.060345 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 15932 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 279 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 193 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 82.549223 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 39.857143 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63848.955335 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63848.955335 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63848.955335 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63848.955335 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63848.955335 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63848.955335 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 17306 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 307 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 186 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 93.043011 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 38.375000 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 280997772654 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 68540364307 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 349598106711 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192628 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192686 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.writebacks::writebacks 1639072 # number of writebacks +system.cpu.l2cache.writebacks::total 1639072 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 36084 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 36084 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3647 # 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number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 71046693133 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 91372170669 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 91372170669 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66585771 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 304219086258 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 304285672029 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66585771 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 304219086258 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 71046693133 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 375332365162 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192606 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192664 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358524 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358524 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219330 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.219377 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219330 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358628 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358628 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219332 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.219379 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219332 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.277771 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57885.859073 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70417.702439 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70412.981182 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69007.892781 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69007.892781 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89081.022602 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89081.022602 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57885.859073 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75328.061039 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75323.218263 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57885.859073 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75328.061039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69007.892781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73995.579018 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.277809 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64458.636012 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77449.685390 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77444.804111 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71495.470199 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 71495.470199 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93069.478753 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93069.478753 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64458.636012 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81560.973259 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81556.238134 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64458.636012 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81560.973259 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71495.470199 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79440.212830 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 14271401 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 14271401 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4837992 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1352607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737487 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737487 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2158 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38853610 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 38855768 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1398131264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1398200320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1352607 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 23199492 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.058303 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.234316 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 14269530 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 14269530 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4835251 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1300143 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737551 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737551 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38847261 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 38849413 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397840384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1397909248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1300143 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 23142477 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.056180 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.230269 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 21846885 94.17% 94.17% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 1352607 5.83% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 21842334 94.38% 94.38% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 1300143 5.62% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23199492 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15761436995 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1798250 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 23142477 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15756418748 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1812271 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 26002804288 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 26100835834 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3738412 # Transaction distribution -system.membus.trans_dist::ReadResp 3738412 # Transaction distribution -system.membus.trans_dist::Writeback 1638491 # Transaction distribution -system.membus.trans_dist::ReadExReq 981933 # Transaction distribution -system.membus.trans_dist::ReadExResp 981933 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11079181 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11079181 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406965504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 406965504 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 3739202 # Transaction distribution +system.membus.trans_dist::ReadResp 3739202 # Transaction distribution +system.membus.trans_dist::Writeback 1639072 # Transaction distribution +system.membus.trans_dist::ReadExReq 982028 # Transaction distribution +system.membus.trans_dist::ReadExResp 982028 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11081532 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11081532 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 407059328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 407059328 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6358836 # Request fanout histogram +system.membus.snoop_fanout::samples 6360302 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6358836 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 6360302 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6358836 # Request fanout histogram -system.membus.reqLayer0.occupancy 20942586092 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 44003891862 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 5.8 # Layer utilization (%) +system.membus.snoop_fanout::total 6360302 # Request fanout histogram +system.membus.reqLayer0.occupancy 14493239223 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 25671846860 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index c26ad4c6d..a5246083c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490000 # Number of ticks simulated final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1680600 # Simulator instruction rate (inst/s) -host_op_rate 1810592 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 905297170 # Simulator tick rate (ticks/s) -host_mem_usage 301428 # Number of bytes of host memory used -host_seconds 919.05 # Real time elapsed on the host +host_inst_rate 1937211 # Simulator instruction rate (inst/s) +host_op_rate 2087051 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1043527090 # Simulator tick rate (ticks/s) +host_mem_usage 301332 # Number of bytes of host memory used +host_seconds 797.31 # Real time elapsed on the host sim_insts 1544563041 # Number of instructions simulated sim_ops 1664032433 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 system.membus.pkt_size::total 8383808419 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 2172060894 # Request fanout histogram -system.membus.snoop_fanout::mean 4.711106 # Request fanout histogram +system.membus.snoop_fanout::mean 2.711106 # Request fanout histogram system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 627495305 28.89% 28.89% # Request fanout histogram -system.membus.snoop_fanout::5 1544565589 71.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 627495305 28.89% 28.89% # Request fanout histogram +system.membus.snoop_fanout::3 1544565589 71.11% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 2172060894 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 89012dc1c..893b8aa6f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.363671 # Number of seconds simulated -sim_ticks 2363670998000 # Number of ticks simulated -final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.363663 # Number of seconds simulated +sim_ticks 2363662966500 # Number of ticks simulated +final_tick 2363662966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1113267 # Simulator instruction rate (inst/s) -host_op_rate 1199701 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1710076181 # Simulator tick rate (ticks/s) -host_mem_usage 309628 # Number of bytes of host memory used -host_seconds 1382.20 # Real time elapsed on the host +host_inst_rate 1021163 # Simulator instruction rate (inst/s) +host_op_rate 1100446 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1568591191 # Simulator tick rate (ticks/s) +host_mem_usage 309800 # Number of bytes of host memory used +host_seconds 1506.87 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1658228914 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,16 +26,16 @@ system.physmem.num_reads::total 1958774 # Nu system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 16679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53020117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53036796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53020297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53036976 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 16679 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 16679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27542188 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27542188 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27542188 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 27542282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27542282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27542282 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53020297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80579258 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4727341996 # number of cpu cycles simulated +system.cpu.numCycles 4727325933 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759601 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 633153380 # nu system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 4727341995.998000 # Number of busy cycles +system.cpu.num_busy_cycles 4727325932.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 213462426 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032480 # Class of executed instruction system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4083.733675 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 25164658000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733675 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -254,14 +254,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115235 # n system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143400508500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143400508500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57355969000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57355969000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200756477500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200756477500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200756477500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200756477500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) @@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19844.838340 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19844.838340 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30360.743912 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30360.743912 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22024.278858 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22024.278858 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22024.276442 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22024.276442 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132561379500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 132561379500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54522245500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 54522245500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187083625000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 187083625000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187083678500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 187083678500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18344.838340 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18344.838340 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28860.743912 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28860.743912 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20524.278858 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20524.278858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20524.282476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20524.282476 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 515.012767 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 515.012865 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 515.012767 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.251471 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id @@ -373,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34244500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34244500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34244500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34244500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34244500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34244500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34207000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34207000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34207000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34207000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34207000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34207000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses @@ -391,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53674.764890 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53674.764890 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53674.764890 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53674.764890 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53615.987461 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53615.987461 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53615.987461 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53615.987461 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53615.987461 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53615.987461 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -411,37 +411,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32968500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32968500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32968500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32968500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32968500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32968500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33250000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33250000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33250000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33250000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33250000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 33250000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51674.764890 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51674.764890 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52115.987461 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52115.987461 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52115.987461 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52115.987461 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52115.987461 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52115.987461 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1926075 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31008.537310 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31008.535045 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 150067859000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15658.172881 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876038 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.488392 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.477850 # Average percentage of cache occupancy +system.cpu.l2cache.tags.warmup_cycle 150067842000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15658.160488 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876098 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.498459 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.477849 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000729 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.467727 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.467728 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.946305 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id @@ -476,17 +476,17 @@ system.cpu.l2cache.demand_misses::total 1958774 # nu system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32110500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61239144500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 61271255000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608894000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 40608894000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 32110500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 101848038500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 101880149000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 32110500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 101848038500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 101880149000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32381000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61822893500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61855274500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40996230000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 40996230000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 32381000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 102819123500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 102851504500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 32381000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102819123500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 102851504500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) @@ -511,17 +511,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.214875 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52127.435065 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52017.396427 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52017.453973 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.279809 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.279809 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52012.202020 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52012.202020 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52566.558442 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52513.241093 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52513.268976 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.307347 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.307347 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52566.558442 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.083362 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52508.101751 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52566.558442 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.083362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52508.101751 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -543,17 +543,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1958774 system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24708000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098189000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122897000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24708000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336506000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 78361214000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24708000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336506000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 78361214000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24978000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47681937000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47706915000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31625653000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31625653000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24978000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79307590000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 79332568000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24978000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79307590000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 79332568000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses @@ -565,17 +565,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.389610 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.868602 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.923263 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40548.701299 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40501.712419 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40501.736993 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.224107 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.224107 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40548.701299 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40501.118909 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.133873 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40548.701299 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40501.118909 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.133873 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution @@ -590,19 +590,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 12813292 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 12813292 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) @@ -630,9 +628,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 2975972 # Request fanout histogram -system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 7175472500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 9807518500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 310a8da1f..9a9ddb0f1 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.882581 # Number of seconds simulated -sim_ticks 5882580526000 # Number of ticks simulated -final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.882580 # Number of seconds simulated +sim_ticks 5882580398500 # Number of ticks simulated +final_tick 5882580398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 912016 # Simulator instruction rate (inst/s) -host_op_rate 1421004 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1783532526 # Simulator tick rate (ticks/s) -host_mem_usage 308940 # Number of bytes of host memory used -host_seconds 3298.27 # Real time elapsed on the host +host_inst_rate 733187 # Simulator instruction rate (inst/s) +host_op_rate 1142372 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1433815394 # Simulator tick rate (ticks/s) +host_mem_usage 313792 # Number of bytes of host memory used +host_seconds 4102.75 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -27,7 +27,7 @@ system.physmem.num_writes::writebacks 1018421 # Nu system.physmem.num_writes::total 1018421 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 21304762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 21312105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 21312106 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s) @@ -35,37 +35,11 @@ system.physmem.bw_write::total 11079992 # Wr system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1177614 # Transaction distribution -system.membus.trans_dist::ReadResp 1177614 # Transaction distribution -system.membus.trans_dist::Writeback 1018421 # Transaction distribution -system.membus.trans_dist::ReadExReq 781295 # Transaction distribution -system.membus.trans_dist::ReadExResp 781295 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2977330 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2977330 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2977330 # Request fanout histogram -system.membus.reqLayer0.occupancy 11124698000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) +system.physmem.bw_total::total 32392098 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 11765161052 # number of cpu cycles simulated +system.cpu.numCycles 11765160797 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed @@ -86,7 +60,7 @@ system.cpu.num_mem_refs 1677713084 # nu system.cpu.num_load_insts 1239184746 # Number of load instructions system.cpu.num_store_insts 438528338 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 11765161051.998001 # Number of busy cycles +system.cpu.num_busy_cycles 11765160796.998001 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 248500691 # Number of branches fetched @@ -125,6 +99,115 @@ system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction +system.cpu.dcache.tags.replacements 9108581 # number of replacements +system.cpu.dcache.tags.tagsinuse 4084.587033 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 58853917000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587033 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2744 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits +system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses +system.cpu.dcache.overall_misses::total 9112677 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328499000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143328499000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382147000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57382147000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200710646000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200710646000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200710646000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200710646000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.759596 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.759596 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.703662 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.703662 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.431824 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22025.431824 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.431824 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22025.431824 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3697956 # number of writebacks +system.cpu.dcache.writebacks::total 3697956 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132494224000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 132494224000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54547406500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 54547406500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187041630500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 187041630500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187041630500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 187041630500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18343.759596 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18343.759596 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28863.703662 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28863.703662 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20525.431824 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20525.431824 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20525.431824 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20525.431824 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10 # number of replacements system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. @@ -152,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst 675 # n system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses system.cpu.icache.overall_misses::total 675 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 37156000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 37156000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 37156000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 37156000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 37156000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 37156000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37138500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37138500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37138500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37138500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37138500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37138500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses @@ -170,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55045.925926 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55045.925926 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55045.925926 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55045.925926 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55020 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55020 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55020 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55020 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55020 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55020 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -190,34 +273,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 675 system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35806000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 35806000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35806000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 35806000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35806000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 35806000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36126000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36126000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36126000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36126000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36126000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36126000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53045.925926 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53045.925926 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53520 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53520 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53520 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53520 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53520 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53520 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1926197 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31136.249379 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31136.249311 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 340768621000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795346 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812949 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy @@ -252,17 +335,17 @@ system.cpu.l2cache.demand_misses::total 1958909 # nu system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1958234 # number of overall misses system.cpu.l2cache.overall_misses::total 1958909 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35131000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61200881000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 61236012000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40627414000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 40627414000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 35131000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 101828295000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 101863426000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 35131000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 101828295000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 101863426000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35451000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61789308500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61824759500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41017993500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41017993500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 35451000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 102807302000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 102842753000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 35451000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102807302000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 102842753000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses) @@ -287,17 +370,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.214949 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214891 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.214949 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52045.925926 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.045032 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.071331 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.094715 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.094715 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.080657 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.080657 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52520 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500.009346 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.020805 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.007680 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.007680 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52520 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.008681 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.015570 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52520 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.008681 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.015570 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -319,17 +402,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1958909 system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1958234 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1958909 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27031000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47077613000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47104644000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31251874000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31251874000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27031000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78329487000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 78356518000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27031000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78329487000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 78356518000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27350500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47666040500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47693391000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31642453500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31642453500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27350500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79308494000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 79335844500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27350500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79308494000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 79335844500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162947 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163025 # mshr miss rate for ReadReq accesses @@ -341,127 +424,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.214949 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.214949 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.925926 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.045032 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.071331 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.094715 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.094715 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40519.259259 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500.009346 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.020380 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.007680 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.007680 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40519.259259 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.008681 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.015315 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40519.259259 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.008681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.015315 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2744 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1668600407 # 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number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200710756000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.765411 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.765411 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.739644 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.739644 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22025.443895 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22025.443895 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3697956 # number of writebacks -system.cpu.dcache.writebacks::total 3697956 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128882841000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 128882841000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53602561000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53602561000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182485402000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 182485402000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182485402000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 182485402000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.765411 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.765411 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution @@ -493,5 +467,31 @@ system.cpu.toL2Bus.respLayer0.occupancy 1012500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1177614 # Transaction distribution +system.membus.trans_dist::ReadResp 1177614 # Transaction distribution +system.membus.trans_dist::Writeback 1018421 # Transaction distribution +system.membus.trans_dist::ReadExReq 781295 # Transaction distribution +system.membus.trans_dist::ReadExResp 781295 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2977330 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2977330 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2977330 # Request fanout histogram +system.membus.reqLayer0.occupancy 7158077000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 9794545500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index ae03186ae..e483ad3f0 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.052167 # Number of seconds simulated -sim_ticks 52167245000 # Number of ticks simulated -final_tick 52167245000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.052202 # Number of seconds simulated +sim_ticks 52201532500 # Number of ticks simulated +final_tick 52201532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 211928 # Simulator instruction rate (inst/s) -host_op_rate 211928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 120297341 # Simulator tick rate (ticks/s) -host_mem_usage 286252 # Number of bytes of host memory used -host_seconds 433.65 # Real time elapsed on the host +host_inst_rate 357575 # Simulator instruction rate (inst/s) +host_op_rate 357575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 203104604 # Simulator tick rate (ticks/s) +host_mem_usage 300132 # Number of bytes of host memory used +host_seconds 257.02 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 202688 # Nu system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory system.physmem.num_reads::total 5318 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3885350 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2638897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6524247 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3885350 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3885350 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3885350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2638897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6524247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3882798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2637164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6519962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3882798 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3882798 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3882798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2637164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6519962 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5318 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5318 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 52167163500 # Total gap between requests +system.physmem.totGap 52201444000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 386 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 972 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.971193 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 211.834828 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.374999 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 320 32.92% 32.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 191 19.65% 52.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96 9.88% 62.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 99 10.19% 72.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 63 6.48% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 36 3.70% 82.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24 2.47% 85.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 26 2.67% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 117 12.04% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 972 # Bytes accessed per row activation -system.physmem.totQLat 32099750 # Total ticks spent queuing -system.physmem.totMemAccLat 131812250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 983 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 345.912513 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 209.979760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.521018 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 325 33.06% 33.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 203 20.65% 53.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 90 9.16% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 89 9.05% 71.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 77 7.83% 79.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 32 3.26% 83.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 28 2.85% 85.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 23 2.34% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 116 11.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 983 # Bytes accessed per row activation +system.physmem.totQLat 33415750 # Total ticks spent queuing +system.physmem.totMemAccLat 133128250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26590000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6036.06 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6283.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24786.06 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25033.52 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.52 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4338 # Number of row buffer hits during reads +system.physmem.readRowHits 4331 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9809545.60 # Average gap between requests -system.physmem.pageHitRate 81.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3530520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1926375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19827600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 9815991.73 # Average gap between requests +system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3500280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1909875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19975800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3406843440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1740830445 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29769165000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34942123380 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.898193 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49520504500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1741740000 # Time in different power states +system.physmem_0.refreshEnergy 3409386240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1770933285 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29766117750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34971823230 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.967540 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49515286750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1743040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 898118000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 940967000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3772440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2058375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3908520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2132625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21301800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3406843440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1807143390 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29710995750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34952029395 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.088108 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49425818250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1741740000 # Time in different power states +system.physmem_1.refreshEnergy 3409386240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1804216725 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29736921750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34977867660 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.083336 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49466733750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1743040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 995309750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 989849750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 11476348 # Number of BP lookups -system.cpu.branchPred.condPredicted 8235349 # Number of conditional branches predicted +system.cpu.branchPred.lookups 11476351 # Number of BP lookups +system.cpu.branchPred.condPredicted 8235351 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 785844 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6672654 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5371509 # Number of BTB hits +system.cpu.branchPred.BTBLookups 6672655 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5371510 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.500338 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1176737 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 80.500341 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1176738 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 26977004 # DT system.cpu.dtb.data_misses 47407 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 27024411 # DTB accesses -system.cpu.itb.fetch_hits 23068130 # ITB hits +system.cpu.itb.fetch_hits 23068140 # ITB hits system.cpu.itb.fetch_misses 88 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 23068218 # ITB accesses +system.cpu.itb.fetch_accesses 23068228 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,26 +293,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 104334490 # number of cpu cycles simulated +system.cpu.numCycles 104403065 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed system.cpu.discardedOps 2153944 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.135266 # CPI: cycles per instruction -system.cpu.ipc 0.880851 # IPC: instructions per cycle -system.cpu.tickCycles 102681434 # Number of cycles that the object actually ticked -system.cpu.idleCycles 1653056 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.136013 # CPI: cycles per instruction +system.cpu.ipc 0.880272 # IPC: instructions per cycle +system.cpu.tickCycles 102681380 # Number of cycles that the object actually ticked +system.cpu.idleCycles 1721685 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.700214 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26568138 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1448.443915 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26568135 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11913.963229 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11913.961883 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1448.700214 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353687 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353687 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1448.443915 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353624 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353624 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id @@ -320,16 +320,16 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53145366 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53145366 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20069946 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20069946 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 53145360 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53145360 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20069943 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20069943 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6498192 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6498192 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26568138 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26568138 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26568138 # number of overall hits -system.cpu.dcache.overall_hits::total 26568138 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 26568135 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26568135 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26568135 # number of overall hits +system.cpu.dcache.overall_hits::total 26568135 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 519 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 519 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2911 # number of WriteReq misses @@ -338,22 +338,22 @@ system.cpu.dcache.demand_misses::cpu.data 3430 # n system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 3430 # number of overall misses system.cpu.dcache.overall_misses::total 3430 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37684500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37684500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 195045500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 195045500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 232730000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 232730000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 232730000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 232730000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20070465 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20070465 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40365000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40365000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 216719250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 216719250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 257084250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 257084250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 257084250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 257084250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20070462 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20070462 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26571568 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26571568 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26571568 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26571568 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26571565 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26571565 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26571565 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26571565 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000448 # miss rate for WriteReq accesses @@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72609.826590 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72609.826590 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67002.919959 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67002.919959 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67851.311953 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67851.311953 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67851.311953 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67851.311953 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77774.566474 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77774.566474 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74448.385435 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74448.385435 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74951.676385 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74951.676385 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74951.676385 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74951.676385 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2230 system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34103500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34103500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 117640500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 117640500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151744000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 151744000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151744000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151744000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37010250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37010250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 130741250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 130741250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167751500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 167751500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 167751500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 167751500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -412,24 +412,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70316.494845 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70316.494845 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67415.759312 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67415.759312 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68046.636771 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68046.636771 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76309.793814 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76309.793814 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74923.352436 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74923.352436 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75224.887892 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75224.887892 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75224.887892 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75224.887892 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13871 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.665289 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23052294 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1640.396029 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23052304 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15835 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1455.781118 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1455.781749 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.665289 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801106 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801106 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.396029 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.800975 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.800975 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id @@ -437,44 +437,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 669 system.cpu.icache.tags.age_task_id_blocks_1024::3 148 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 948 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 46152095 # Number of tag accesses -system.cpu.icache.tags.data_accesses 46152095 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23052294 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23052294 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23052294 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23052294 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23052294 # number of overall hits -system.cpu.icache.overall_hits::total 23052294 # number of overall hits +system.cpu.icache.tags.tag_accesses 46152115 # Number of tag accesses +system.cpu.icache.tags.data_accesses 46152115 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23052304 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23052304 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23052304 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23052304 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23052304 # number of overall hits +system.cpu.icache.overall_hits::total 23052304 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15836 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15836 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15836 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15836 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15836 # number of overall misses system.cpu.icache.overall_misses::total 15836 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 386327750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 386327750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 386327750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 386327750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 386327750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 386327750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 23068130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 23068130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 23068130 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 23068130 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 23068130 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 23068130 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 409644000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 409644000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 409644000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 409644000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 409644000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 409644000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 23068140 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 23068140 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 23068140 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 23068140 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 23068140 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 23068140 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000686 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000686 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000686 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000686 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000686 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000686 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24395.538646 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24395.538646 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24395.538646 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24395.538646 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24395.538646 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24395.538646 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25867.895933 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25867.895933 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25867.895933 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25867.895933 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25867.895933 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25867.895933 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -489,38 +489,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15836 system.cpu.icache.demand_mshr_misses::total 15836 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15836 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15836 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353292250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 353292250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353292250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 353292250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353292250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 353292250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 384517500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 384517500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 384517500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 384517500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 384517500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 384517500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000686 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000686 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22309.437358 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22309.437358 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22309.437358 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22309.437358 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22309.437358 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22309.437358 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24281.226320 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24281.226320 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24281.226320 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24281.226320 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24281.226320 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24281.226320 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2479.833240 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2479.394298 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 12735 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3665 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 3.474761 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.780071 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.017125 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 361.036043 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.779390 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2100.640552 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 360.974356 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064118 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011018 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.075679 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064106 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011016 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.075665 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3665 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id @@ -554,17 +554,17 @@ system.cpu.l2cache.demand_misses::total 5318 # nu system.cpu.l2cache.overall_misses::cpu.inst 3167 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2151 # number of overall misses system.cpu.l2cache.overall_misses::total 5318 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210776750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 33082500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 243859250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115635000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 115635000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 210776750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 148717500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 359494250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 210776750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 148717500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 359494250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 235668000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35962750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 271630750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128723250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 128723250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 235668000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 164686000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 400354000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 235668000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 164686000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 400354000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 15835 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 485 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 16320 # number of ReadReq accesses(hits+misses) @@ -589,17 +589,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.294381 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200000 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.294381 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66554.073255 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76579.861111 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67757.502084 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67268.760908 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67268.760908 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66554.073255 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69138.772664 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67599.520496 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66554.073255 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69138.772664 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67599.520496 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74413.640669 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83247.106481 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75473.951098 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74882.635253 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74882.635253 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74413.640669 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76562.529056 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75282.813088 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74413.640669 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76562.529056 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75282.813088 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -619,17 +619,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5318 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3167 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5318 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 170928750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27694500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198623250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93817500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93817500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 170928750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 121512000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 292440750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 170928750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 121512000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 292440750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 196043000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30551250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 226594250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 107188750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 107188750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 196043000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137740000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 333783000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 196043000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137740000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 333783000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.220527 # mshr miss rate for ReadReq accesses @@ -641,17 +641,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.294381 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294381 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53971.818756 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64107.638889 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55188.455126 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54576.788831 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54576.788831 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53971.818756 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56490.934449 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53971.818756 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56490.934449 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61901.799811 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70720.486111 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62960.336205 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62355.293775 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62355.293775 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61901.799811 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64035.332404 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62764.761188 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61901.799811 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64035.332404 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62764.761188 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 16320 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 16320 # Transaction distribution @@ -678,9 +678,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 18172 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 9193000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24435250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24439500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3734000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3770500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 3599 # Transaction distribution system.membus.trans_dist::ReadResp 3599 # Transaction distribution @@ -701,9 +701,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5318 # Request fanout histogram -system.membus.reqLayer0.occupancy 6478000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6453000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50027750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28232500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index fbd001a0c..9c86c55d6 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022159 # Number of seconds simulated -sim_ticks 22159411000 # Number of ticks simulated -final_tick 22159411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022229 # Number of seconds simulated +sim_ticks 22228749500 # Number of ticks simulated +final_tick 22228749500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210811 # Simulator instruction rate (inst/s) -host_op_rate 210811 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55493646 # Simulator tick rate (ticks/s) -host_mem_usage 299980 # Number of bytes of host memory used -host_seconds 399.31 # Real time elapsed on the host +host_inst_rate 212613 # Simulator instruction rate (inst/s) +host_op_rate 212613 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56143360 # Simulator tick rate (ticks/s) +host_mem_usage 300388 # Number of bytes of host memory used +host_seconds 395.93 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 196160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138688 # Number of bytes read from this memory -system.physmem.bytes_read::total 334848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 196160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 196160 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2167 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5232 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8852221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6258650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15110871 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8852221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8852221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8852221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6258650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15110871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5232 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 196032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory +system.physmem.bytes_read::total 334592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 196032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 196032 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3063 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8818850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6233369 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15052219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8818850 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8818850 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8818850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6233369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15052219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5228 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5232 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5228 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334848 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334592 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334848 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334592 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 471 # Per bank write bursts -system.physmem.perBankRdBursts::1 289 # Per bank write bursts +system.physmem.perBankRdBursts::0 472 # Per bank write bursts +system.physmem.perBankRdBursts::1 290 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts -system.physmem.perBankRdBursts::3 527 # Per bank write bursts -system.physmem.perBankRdBursts::4 218 # Per bank write bursts +system.physmem.perBankRdBursts::3 525 # Per bank write bursts +system.physmem.perBankRdBursts::4 219 # Per bank write bursts system.physmem.perBankRdBursts::5 224 # Per bank write bursts -system.physmem.perBankRdBursts::6 217 # Per bank write bursts -system.physmem.perBankRdBursts::7 287 # Per bank write bursts -system.physmem.perBankRdBursts::8 239 # Per bank write bursts -system.physmem.perBankRdBursts::9 281 # Per bank write bursts -system.physmem.perBankRdBursts::10 249 # Per bank write bursts -system.physmem.perBankRdBursts::11 253 # Per bank write bursts -system.physmem.perBankRdBursts::12 396 # Per bank write bursts +system.physmem.perBankRdBursts::6 218 # Per bank write bursts +system.physmem.perBankRdBursts::7 285 # Per bank write bursts +system.physmem.perBankRdBursts::8 238 # Per bank write bursts +system.physmem.perBankRdBursts::9 279 # Per bank write bursts +system.physmem.perBankRdBursts::10 248 # Per bank write bursts +system.physmem.perBankRdBursts::11 252 # Per bank write bursts +system.physmem.perBankRdBursts::12 398 # Per bank write bursts system.physmem.perBankRdBursts::13 338 # Per bank write bursts -system.physmem.perBankRdBursts::14 493 # Per bank write bursts -system.physmem.perBankRdBursts::15 448 # Per bank write bursts +system.physmem.perBankRdBursts::14 491 # Per bank write bursts +system.physmem.perBankRdBursts::15 449 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22159321500 # Total gap between requests +system.physmem.totGap 22228653000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5232 # Read request sizes (log2) +system.physmem.readPktSize::6 5228 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -188,27 +188,27 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 866 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 383.630485 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 228.084782 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.284844 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 269 31.06% 31.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 171 19.75% 50.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 88 10.16% 60.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 63 7.27% 68.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 38 4.39% 72.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 33 3.81% 76.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 35 4.04% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 46 5.31% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 123 14.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 225.895164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 361.482180 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 274 31.64% 31.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 174 20.09% 51.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 79 9.12% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 66 7.62% 68.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 29 3.35% 71.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 4.27% 76.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 36 4.16% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 45 5.20% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 126 14.55% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 866 # Bytes accessed per row activation -system.physmem.totQLat 41292000 # Total ticks spent queuing -system.physmem.totMemAccLat 139392000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7892.20 # Average queueing delay per DRAM burst +system.physmem.totQLat 39875750 # Total ticks spent queuing +system.physmem.totMemAccLat 137900750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7627.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26642.20 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.11 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26377.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.05 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.11 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.05 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.12 # Data bus utilization in percentage @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.12 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4354 # Number of row buffer hits during reads +system.physmem.readRowHits 4353 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.22 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.26 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4235344.32 # Average gap between requests -system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined +system.physmem.avgGap 4251846.40 # Average gap between requests +system.physmem.pageHitRate 83.26 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 3137400 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 1711875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19453200 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 19476600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1446853200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 894020490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 12507056250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14872232415 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.367713 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 20804380500 # Time in different power states -system.physmem_0.memoryStateTime::REF 739700000 # Time in different power states +system.physmem_0.refreshEnergy 1451430240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 894518100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12548665500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14918939715 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.352430 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20873521000 # Time in different power states +system.physmem_0.memoryStateTime::REF 742040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 608242500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 606815000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20802600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3349080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1827375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20794800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1446853200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 920005650 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12484262250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14877088470 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.586927 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 20766250250 # Time in different power states -system.physmem_1.memoryStateTime::REF 739700000 # Time in different power states +system.physmem_1.refreshEnergy 1451430240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 919030095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12527163750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14923595340 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.561933 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20841181500 # Time in different power states +system.physmem_1.memoryStateTime::REF 742040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 646430250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 642887000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16298030 # Number of BP lookups -system.cpu.branchPred.condPredicted 11843884 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 974423 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8872850 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7618799 # Number of BTB hits +system.cpu.branchPred.lookups 16323961 # Number of BP lookups +system.cpu.branchPred.condPredicted 11865379 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 978310 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9045215 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7641567 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 85.866424 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1608574 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 439 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 84.481872 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1608650 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 453 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24142171 # DTB read hits -system.cpu.dtb.read_misses 235539 # DTB read misses +system.cpu.dtb.read_hits 24152698 # DTB read hits +system.cpu.dtb.read_misses 236585 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 24377710 # DTB read accesses -system.cpu.dtb.write_hits 7161357 # DTB write hits -system.cpu.dtb.write_misses 1208 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 7162565 # DTB write accesses -system.cpu.dtb.data_hits 31303528 # DTB hits -system.cpu.dtb.data_misses 236747 # DTB misses -system.cpu.dtb.data_acv 3 # DTB access violations -system.cpu.dtb.data_accesses 31540275 # DTB accesses -system.cpu.itb.fetch_hits 16127186 # ITB hits -system.cpu.itb.fetch_misses 86 # ITB misses +system.cpu.dtb.read_accesses 24389283 # DTB read accesses +system.cpu.dtb.write_hits 7160578 # DTB write hits +system.cpu.dtb.write_misses 1214 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 7161792 # DTB write accesses +system.cpu.dtb.data_hits 31313276 # DTB hits +system.cpu.dtb.data_misses 237799 # DTB misses +system.cpu.dtb.data_acv 2 # DTB access violations +system.cpu.dtb.data_accesses 31551075 # DTB accesses +system.cpu.itb.fetch_hits 16159751 # ITB hits +system.cpu.itb.fetch_misses 85 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 16127272 # ITB accesses +system.cpu.itb.fetch_accesses 16159836 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,139 +293,140 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 44318823 # number of cpu cycles simulated +system.cpu.numCycles 44457500 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16859439 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 139373095 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16298030 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9227373 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 26218422 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2029202 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2359 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 16127186 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 380559 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44094963 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.160749 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.432020 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 16896881 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 139613933 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16323961 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9250217 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 26293708 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2036816 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 2 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 203 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2338 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 16159751 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 382144 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44211553 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.157861 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.431266 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19653198 44.57% 44.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2660337 6.03% 50.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1339868 3.04% 53.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1948475 4.42% 58.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3047157 6.91% 64.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1303414 2.96% 67.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1381873 3.13% 71.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 894467 2.03% 73.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11866174 26.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19722112 44.61% 44.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2663068 6.02% 50.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1345508 3.04% 53.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1957580 4.43% 58.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3052640 6.90% 65.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1306785 2.96% 67.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1385791 3.13% 71.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 896674 2.03% 73.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11881395 26.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44094963 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367745 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.144783 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13063435 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8246931 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19674377 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2107337 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1002883 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2678530 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12053 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 133445502 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 49010 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1002883 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 14206625 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4728440 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8922 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20521133 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3626960 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 129917938 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 71936 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1987853 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1348485 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 46206 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 95420653 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 168813407 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 161260201 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7553205 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44211553 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367181 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.140391 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13076592 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8324763 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19681975 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2121490 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1006733 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2681054 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12065 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 133596496 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 48387 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1006733 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 14226924 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4752424 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9184 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20532599 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3683689 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 130038627 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 69797 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2001155 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1372929 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 55394 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 95511389 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 168978901 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 161414982 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7563918 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 26993292 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 764 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 773 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8204907 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 27105677 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8747640 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3541499 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1618929 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 112639456 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1940 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 100102500 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 120259 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27967887 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21886191 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1551 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44094963 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.270157 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.096378 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27084028 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 772 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 782 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8280120 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 27136625 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8757663 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3565364 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1670156 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 112744524 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2237 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 100145020 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 122649 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 28075682 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21979359 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1848 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44211553 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.265132 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.094303 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11535006 26.16% 26.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7754470 17.59% 43.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7555421 17.13% 60.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5737104 13.01% 73.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4489384 10.18% 84.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2977388 6.75% 90.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2013844 4.57% 95.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1160432 2.63% 98.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 871914 1.98% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11585483 26.20% 26.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7800031 17.64% 43.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7580714 17.15% 60.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5746471 13.00% 73.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4482670 10.14% 84.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2978699 6.74% 90.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2013201 4.55% 95.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1153505 2.61% 98.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 870779 1.97% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44094963 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44211553 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 479018 20.14% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 443 0.02% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 33638 1.41% 21.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 11723 0.49% 22.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1006429 42.32% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 686405 28.86% 93.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 160330 6.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 481856 20.25% 20.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 20.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 20.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 350 0.01% 20.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34531 1.45% 21.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 11644 0.49% 22.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1006485 42.29% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 687304 28.88% 93.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 157568 6.62% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60895268 60.83% 60.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 491428 0.49% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60921013 60.83% 60.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 491088 0.49% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2836761 2.83% 64.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115534 0.12% 64.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2437739 2.44% 66.71% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 313998 0.31% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 765483 0.76% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2841000 2.84% 64.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115643 0.12% 64.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2440640 2.44% 66.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 314095 0.31% 67.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 766051 0.76% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued @@ -447,84 +448,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.79% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24980978 24.96% 92.74% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7264985 7.26% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24991126 24.95% 92.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7264038 7.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 100102500 # Type of FU issued -system.cpu.iq.rate 2.258690 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2377986 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023756 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 231175586 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 131029945 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 90008848 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15622622 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9621224 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7166740 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 94135370 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8345109 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1908744 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 100145020 # Type of FU issued +system.cpu.iq.rate 2.252601 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2379738 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023763 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 231363005 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 131215529 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 90039702 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15640975 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9648680 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7175345 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 94170320 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8354431 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1902679 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7109479 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 10719 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 42241 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2246537 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7140427 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11100 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 42139 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2256560 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42761 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2468 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42760 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1687 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1002883 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3707612 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 461807 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 123638491 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 278104 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 27105677 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8747640 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1940 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 39979 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 414885 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 42241 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 554445 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 525545 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1079990 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98729735 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24378234 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1372765 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1006733 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3731793 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 447885 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 123749930 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 277756 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 27136625 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8757663 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2237 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 43684 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 396903 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 42139 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 560048 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 524506 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1084554 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98770041 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24389817 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1374979 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10997095 # number of nop insts executed -system.cpu.iew.exec_refs 31540837 # number of memory reference insts executed -system.cpu.iew.exec_branches 12532490 # Number of branches executed -system.cpu.iew.exec_stores 7162603 # Number of stores executed -system.cpu.iew.exec_rate 2.227716 # Inst execution rate -system.cpu.iew.wb_sent 97918369 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 97175588 # cumulative count of insts written-back -system.cpu.iew.wb_producers 67088120 # num instructions producing a value -system.cpu.iew.wb_consumers 95122376 # num instructions consuming a value +system.cpu.iew.exec_nop 11003169 # number of nop insts executed +system.cpu.iew.exec_refs 31551638 # number of memory reference insts executed +system.cpu.iew.exec_branches 12536484 # Number of branches executed +system.cpu.iew.exec_stores 7161821 # Number of stores executed +system.cpu.iew.exec_rate 2.221673 # Inst execution rate +system.cpu.iew.wb_sent 97959187 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 97215047 # cumulative count of insts written-back +system.cpu.iew.wb_producers 67118954 # num instructions producing a value +system.cpu.iew.wb_consumers 95176065 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.192648 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705282 # average fanout of values written-back +system.cpu.iew.wb_rate 2.186696 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705208 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 31736961 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 31848480 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 962705 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39466887 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.328612 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.908948 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 966635 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39567002 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.322720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.905630 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14969500 37.93% 37.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8597582 21.78% 59.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3898491 9.88% 69.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1956472 4.96% 74.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1378246 3.49% 78.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1028775 2.61% 80.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 694003 1.76% 82.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 732346 1.86% 84.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6211472 15.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15032687 37.99% 37.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8622118 21.79% 59.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3917590 9.90% 69.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1951695 4.93% 74.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1384336 3.50% 78.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1033619 2.61% 80.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 694183 1.75% 82.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 726057 1.84% 84.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6204717 15.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39466887 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39567002 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -570,345 +571,345 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6211472 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6204717 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 156894391 # The number of ROB reads -system.cpu.rob.rob_writes 251967276 # The number of ROB writes -system.cpu.timesIdled 4539 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 223860 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 157112780 # The number of ROB reads +system.cpu.rob.rob_writes 252206838 # The number of ROB writes +system.cpu.timesIdled 4633 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 245947 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.526479 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.526479 # CPI: Total CPI of All Threads -system.cpu.ipc 1.899412 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.899412 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 133358103 # number of integer regfile reads -system.cpu.int_regfile_writes 73122882 # number of integer regfile writes -system.cpu.fp_regfile_reads 6250590 # number of floating regfile reads -system.cpu.fp_regfile_writes 6153622 # number of floating regfile writes -system.cpu.misc_regfile_reads 718773 # number of misc regfile reads +system.cpu.cpi 0.528126 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.528126 # CPI: Total CPI of All Threads +system.cpu.ipc 1.893487 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.893487 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 133407543 # number of integer regfile reads +system.cpu.int_regfile_writes 73150911 # number of integer regfile writes +system.cpu.fp_regfile_reads 6256040 # number of floating regfile reads +system.cpu.fp_regfile_writes 6161921 # number of floating regfile writes +system.cpu.misc_regfile_reads 718993 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 160 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.564933 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28680753 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2248 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12758.342082 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 159 # number of replacements +system.cpu.dcache.tags.tagsinuse 1458.668074 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28697534 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2246 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12777.174533 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.564933 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355851 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355851 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1458.668074 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.356120 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.356120 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2087 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57382576 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57382576 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22187756 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22187756 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492735 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492735 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 262 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 262 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28680491 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28680491 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28680491 # number of overall hits -system.cpu.dcache.overall_hits::total 28680491 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1042 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1042 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8368 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8368 # number of WriteReq misses +system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 57416312 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57416312 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22204643 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22204643 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492628 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492628 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 263 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 263 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28697271 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28697271 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28697271 # number of overall hits +system.cpu.dcache.overall_hits::total 28697271 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1023 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1023 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8475 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8475 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9410 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9410 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9410 # number of overall misses -system.cpu.dcache.overall_misses::total 9410 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65475750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65475750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 523849968 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 523849968 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 589325718 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 589325718 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 589325718 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 589325718 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22188798 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22188798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9498 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9498 # number of overall misses +system.cpu.dcache.overall_misses::total 9498 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 69711000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 69711000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 550954965 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 550954965 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 85000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 620665965 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 620665965 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 620665965 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 620665965 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22205666 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22205666 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 263 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 263 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28689901 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28689901 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28689901 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28689901 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001287 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001287 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003802 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003802 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62836.612284 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62836.612284 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62601.573614 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62601.573614 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62627.600213 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62627.600213 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62627.600213 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62627.600213 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29227 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 416 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 894 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.692394 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 208 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 264 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 264 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28706769 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28706769 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28706769 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28706769 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001304 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001304 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003788 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003788 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000331 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000331 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000331 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000331 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68143.695015 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68143.695015 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65009.435398 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65009.435398 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65347.016740 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65347.016740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65347.016740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65347.016740 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33287 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 426 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.138498 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 110 # number of writebacks -system.cpu.dcache.writebacks::total 110 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 529 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 529 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7163 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7163 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7163 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7163 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 109 # number of writebacks +system.cpu.dcache.writebacks::total 109 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 512 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 512 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6741 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6741 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7253 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7253 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7253 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7253 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 511 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 511 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2247 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2247 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2247 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2247 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36153000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36153000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125731745 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 125731745 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161884745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161884745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161884745 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161884745 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2245 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2245 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2245 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2245 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38736500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 38736500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 136484495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 136484495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 83500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 83500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 175220995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 175220995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 175220995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 175220995 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003802 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003802 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003788 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003788 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70473.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70473.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72509.656863 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72509.656863 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72044.835336 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72044.835336 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72044.835336 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72044.835336 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75805.283757 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75805.283757 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78710.781430 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78710.781430 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 83500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 83500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78049.440980 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78049.440980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78049.440980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78049.440980 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 9583 # number of replacements -system.cpu.icache.tags.tagsinuse 1600.631053 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 16112652 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11519 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1398.789131 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9845 # number of replacements +system.cpu.icache.tags.tagsinuse 1600.510636 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 16144798 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11783 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1370.177204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1600.631053 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.781558 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.781558 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 763 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 930 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 32265889 # Number of tag accesses -system.cpu.icache.tags.data_accesses 32265889 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 16112652 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 16112652 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 16112652 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 16112652 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 16112652 # number of overall hits -system.cpu.icache.overall_hits::total 16112652 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14533 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14533 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14533 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14533 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14533 # number of overall misses -system.cpu.icache.overall_misses::total 14533 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 419570250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 419570250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 419570250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 419570250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 419570250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 419570250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 16127185 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 16127185 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 16127185 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 16127185 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 16127185 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 16127185 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000901 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000901 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000901 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000901 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000901 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000901 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28870.174775 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28870.174775 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28870.174775 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28870.174775 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28870.174775 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28870.174775 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1600.510636 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781499 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781499 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 760 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 936 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 32331281 # Number of tag accesses +system.cpu.icache.tags.data_accesses 32331281 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 16144798 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 16144798 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 16144798 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 16144798 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 16144798 # number of overall hits +system.cpu.icache.overall_hits::total 16144798 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14951 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14951 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14951 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14951 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14951 # number of overall misses +system.cpu.icache.overall_misses::total 14951 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 446766000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 446766000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 446766000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 446766000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 446766000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 446766000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 16159749 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 16159749 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 16159749 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 16159749 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 16159749 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 16159749 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000925 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000925 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000925 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000925 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000925 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000925 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29882.014581 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29882.014581 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29882.014581 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29882.014581 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29882.014581 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29882.014581 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 39.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55.777778 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3014 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3014 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3014 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3014 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3014 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3014 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11519 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11519 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11519 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11519 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11519 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11519 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306551250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 306551250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306551250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 306551250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306551250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 306551250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000714 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000714 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000714 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26612.661689 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26612.661689 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26612.661689 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26612.661689 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26612.661689 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26612.661689 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3168 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3168 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3168 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3168 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3168 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3168 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11783 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11783 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11783 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11783 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11783 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11783 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 332403750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 332403750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 332403750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 332403750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 332403750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 332403750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000729 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000729 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000729 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000729 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000729 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000729 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28210.451498 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28210.451498 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28210.451498 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28210.451498 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28210.451498 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28210.451498 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 376.940444 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.698797 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2011.289043 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 378.344128 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061259 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011503 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.073303 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3591 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # 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number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3063 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5228 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3063 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 190854250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 31997500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222851750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 113271750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 113271750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 190854250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145269250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 336123500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 190854250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145269250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 336123500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.259951 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892578 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.286295 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.259951 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.372657 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.259951 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.372657 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62309.582109 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70016.411379 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63310.156250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66318.354801 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66318.354801 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62309.582109 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67098.960739 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64292.941852 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62309.582109 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67098.960739 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64292.941852 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 12032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 12032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 110 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1735 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1735 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23038 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27644 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 888128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 12295 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12295 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1734 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1734 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23566 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4601 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 28167 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 754112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 904832 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 13877 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 14138 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 13877 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 14138 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13877 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 14138 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7178000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17856250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 18279750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3547750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3635750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3523 # Transaction distribution -system.membus.trans_dist::ReadResp 3523 # Transaction distribution -system.membus.trans_dist::ReadExReq 1709 # Transaction distribution -system.membus.trans_dist::ReadExResp 1709 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 3520 # Transaction distribution +system.membus.trans_dist::ReadResp 3520 # Transaction distribution +system.membus.trans_dist::ReadExReq 1708 # Transaction distribution +system.membus.trans_dist::ReadExResp 1708 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10456 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10456 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5232 # Request fanout histogram +system.membus.snoop_fanout::samples 5228 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5232 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5228 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5232 # Request fanout histogram -system.membus.reqLayer0.occupancy 6529000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5228 # Request fanout histogram +system.membus.reqLayer0.occupancy 6467500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 48920250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 27502000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 4e099442b..85445221a 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.118729 # Number of seconds simulated -sim_ticks 118729316000 # Number of ticks simulated -final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 118729316500 # Number of ticks simulated +final_tick 118729316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1660785 # Simulator instruction rate (inst/s) -host_op_rate 1660785 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2145562848 # Simulator tick rate (ticks/s) -host_mem_usage 293264 # Number of bytes of host memory used -host_seconds 55.34 # Real time elapsed on the host +host_inst_rate 1507080 # Simulator instruction rate (inst/s) +host_op_rate 1507080 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1946992285 # Simulator tick rate (ticks/s) +host_mem_usage 297820 # Number of bytes of host memory used +host_seconds 60.98 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,29 +29,6 @@ system.physmem.bw_inst_read::total 1412827 # In system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 3043 # Transaction distribution -system.membus.trans_dist::ReadResp 3043 # Transaction distribution -system.membus.trans_dist::ReadExReq 1722 # Transaction distribution -system.membus.trans_dist::ReadExResp 1722 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4765 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4765 # Request fanout histogram -system.membus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 42885000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 237458632 # number of cpu cycles simulated +system.cpu.numCycles 237458633 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903056 # Number of instructions committed @@ -105,7 +82,7 @@ system.cpu.num_mem_refs 26497334 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_store_insts 6501126 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 237458632 # Number of busy cycles +system.cpu.num_busy_cycles 237458633 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 10240685 # Number of branches fetched @@ -144,13 +121,122 @@ system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91903089 # Class of executed instruction +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1442.043377 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043377 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 487 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits +system.cpu.dcache.overall_hits::total 26495078 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses +system.cpu.dcache.overall_misses::total 2223 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92426000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92426000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115612500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 115612500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115612500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 115612500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48813.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48813.684211 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52875.286041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52875.286041 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52007.422402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52007.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52007.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52007.422402 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 6681 # number of replacements -system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1418.052759 # Cycle average of tags in use system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052759 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id @@ -174,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst 8510 # n system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses system.cpu.icache.overall_misses::total 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 220712000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 220712000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 220712000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 220712000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 220712000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 220712500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 220712500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 220712500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 220712500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 220712500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses @@ -192,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.605170 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25935.605170 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25935.605170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25935.605170 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.663925 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25935.663925 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25935.663925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25935.663925 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,34 +298,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 8510 system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 207947500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 207947500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 207947500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 207947500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 207947500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 207947500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24435.663925 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24435.663925 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24435.663925 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24435.663925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24435.663925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24435.663925 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2074.070560 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2074.070538 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 5956 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.915729 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.795177 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.017985 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257376 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy @@ -277,17 +363,17 @@ system.cpu.l2cache.demand_misses::total 4765 # nu system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4765 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 136292000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21944000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 158236000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 89544000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 89544000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 136292000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 111488000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 247780000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 136292000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 111488000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 247780000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137603000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22155000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 159758000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90405000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 90405000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 137603000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112560000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 250163000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137603000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112560000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 250163000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 8510 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 8985 # number of ReadReq accesses(hits+misses) @@ -312,17 +398,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.443958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.190767 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.164312 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.104932 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.104932 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -342,17 +428,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4765 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104840000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 121720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85760000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 190600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104840000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85760000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 190600000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106150500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17091000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 123241500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69741000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69741000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106150500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86832000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 192982500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106150500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86832000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 192982500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.338676 # mshr miss rate for ReadReq accesses @@ -364,127 +450,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1442.043392 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 487 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits -system.cpu.dcache.overall_hits::total 26495078 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses -system.cpu.dcache.overall_misses::total 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107 # number of writebacks -system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution @@ -514,5 +491,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 12765000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3043 # Transaction distribution +system.membus.trans_dist::ReadResp 3043 # Transaction distribution +system.membus.trans_dist::ReadExReq 1722 # Transaction distribution +system.membus.trans_dist::ReadExResp 1722 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 4765 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 4765 # Request fanout histogram +system.membus.reqLayer0.occupancy 4765500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 23825500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index c2d632546..f13570e98 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.131746 # Number of seconds simulated -sim_ticks 131745950000 # Number of ticks simulated -final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.131756 # Number of seconds simulated +sim_ticks 131756455500 # Number of ticks simulated +final_tick 131756455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165378 # Simulator instruction rate (inst/s) -host_op_rate 174335 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 126440065 # Simulator tick rate (ticks/s) -host_mem_usage 304748 # Number of bytes of host memory used -host_seconds 1041.96 # Real time elapsed on the host +host_inst_rate 249754 # Simulator instruction rate (inst/s) +host_op_rate 263281 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 190965456 # Simulator tick rate (ticks/s) +host_mem_usage 316672 # Number of bytes of host memory used +host_seconds 689.95 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated sim_ops 181650742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 138176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory -system.physmem.bytes_read::total 247488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 138176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 138176 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2159 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 247616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3867 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1048806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 829718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1878525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1048806 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1048806 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1048806 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 829718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1878525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3867 # Number of read requests accepted +system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1049694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 829652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1879346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1049694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1049694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1049694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 829652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1879346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3869 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3867 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 247488 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 247488 # Total read bytes from the system interface side +system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -45,18 +45,18 @@ system.physmem.perBankRdBursts::0 305 # Pe system.physmem.perBankRdBursts::1 217 # Per bank write bursts system.physmem.perBankRdBursts::2 135 # Per bank write bursts system.physmem.perBankRdBursts::3 313 # Per bank write bursts -system.physmem.perBankRdBursts::4 308 # Per bank write bursts +system.physmem.perBankRdBursts::4 307 # Per bank write bursts system.physmem.perBankRdBursts::5 305 # Per bank write bursts system.physmem.perBankRdBursts::6 273 # Per bank write bursts system.physmem.perBankRdBursts::7 222 # Per bank write bursts system.physmem.perBankRdBursts::8 249 # Per bank write bursts system.physmem.perBankRdBursts::9 218 # Per bank write bursts system.physmem.perBankRdBursts::10 295 # Per bank write bursts -system.physmem.perBankRdBursts::11 199 # Per bank write bursts +system.physmem.perBankRdBursts::11 201 # Per bank write bursts system.physmem.perBankRdBursts::12 183 # Per bank write bursts system.physmem.perBankRdBursts::13 218 # Per bank write bursts system.physmem.perBankRdBursts::14 224 # Per bank write bursts -system.physmem.perBankRdBursts::15 203 # Per bank write bursts +system.physmem.perBankRdBursts::15 204 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 131745861500 # Total gap between requests +system.physmem.totGap 131756361000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3867 # Read request sizes (log2) +system.physmem.readPktSize::6 3869 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,7 +90,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 912 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 269.543860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.691365 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 273.658023 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 266 29.17% 29.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 353 38.71% 67.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 82 8.99% 76.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 61 6.69% 83.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 33 3.62% 87.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 27 2.96% 90.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 14 1.54% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation -system.physmem.totQLat 28130750 # Total ticks spent queuing -system.physmem.totMemAccLat 100637000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7274.57 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 895 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 274.663687 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.028895 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 274.690311 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 245 27.37% 27.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 357 39.89% 67.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 81 9.05% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51 5.70% 82.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 43 4.80% 86.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 26 2.91% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 22 2.46% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 1.79% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 54 6.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 895 # Bytes accessed per row activation +system.physmem.totQLat 26801000 # Total ticks spent queuing +system.physmem.totMemAccLat 99344750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6927.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26024.57 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25677.11 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2950 # Number of row buffer hits during reads +system.physmem.readRowHits 2968 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34069268.55 # Average gap between requests -system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3092040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1687125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 34054370.90 # Average gap between requests +system.physmem.pageHitRate 76.71 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3069360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1674750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3575900700 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75909402750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88111095015 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.807422 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126280313250 # Time in different power states -system.physmem_0.memoryStateTime::REF 4399200000 # Time in different power states +system.physmem_0.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3539588850 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75945927000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88111773120 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.773044 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126343733250 # Time in different power states +system.physmem_0.memoryStateTime::REF 4399460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1064296750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1010942750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3787560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2066625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3681720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2008875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13774800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3595739265 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75892008750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 88112204400 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.815773 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126251429250 # Time in different power states -system.physmem_1.memoryStateTime::REF 4399200000 # Time in different power states +system.physmem_1.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3587668065 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75903760500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88116237720 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.806861 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126271447000 # Time in different power states +system.physmem_1.memoryStateTime::REF 4399460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1093059250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1080937500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 49935043 # Number of BP lookups -system.cpu.branchPred.condPredicted 39664695 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5744224 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24405530 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23309445 # Number of BTB hits +system.cpu.branchPred.lookups 49934480 # Number of BP lookups +system.cpu.branchPred.condPredicted 39666708 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5743450 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24374232 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23299942 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.508866 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1908457 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 95.592518 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1908561 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,75 +377,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 263491900 # number of cpu cycles simulated +system.cpu.numCycles 263512911 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317809 # Number of instructions committed system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11758002 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11759003 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.529104 # CPI: cycles per instruction -system.cpu.ipc 0.653978 # IPC: instructions per cycle -system.cpu.tickCycles 257145198 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6346702 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.529226 # CPI: cycles per instruction +system.cpu.ipc 0.653925 # IPC: instructions per cycle +system.cpu.tickCycles 257129924 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6382987 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.772724 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40762987 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1377.698544 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40765677 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22522.473481 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.772724 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336370 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698544 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81532656 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81532656 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28355530 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28355530 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12362643 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 81538036 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81538036 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28358222 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28358222 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40718173 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40718173 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40718173 # number of overall hits -system.cpu.dcache.overall_hits::total 40718173 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 792 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 792 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1644 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 40720863 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40720863 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40720863 # number of overall hits +system.cpu.dcache.overall_hits::total 40720863 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 790 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 790 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 2436 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 2436 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2436 # number of overall misses system.cpu.dcache.overall_misses::total 2436 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 54011984 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 54011984 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 115610250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 115610250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 169622234 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 169622234 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 169622234 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 169622234 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28356322 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28356322 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57599734 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57599734 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 127302750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 127302750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184902484 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184902484 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184902484 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184902484 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28359012 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28359012 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40720609 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40720609 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40720609 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40720609 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40723299 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40723299 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40723299 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40723299 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses @@ -454,14 +454,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68196.949495 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70322.536496 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70322.536496 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69631.458949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69631.458949 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72911.055696 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72911.055696 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77340.674362 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77340.674362 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75904.139573 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75904.139573 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,10 +472,10 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 546 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 546 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 626 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 626 # number of overall MSHR hits @@ -488,14 +488,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810 system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47293264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 47293264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76508500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 76508500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123801764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 123801764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 123801764 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 123801764 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51193764 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51193764 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85249250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85249250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136443014 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 136443014 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136443014 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 136443014 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -504,69 +504,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66423.123596 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66423.123596 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69679.872495 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69679.872495 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71901.353933 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71901.353933 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77640.482696 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77640.482696 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2909 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.880841 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71614329 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4705 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15220.898831 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2891 # number of replacements +system.cpu.icache.tags.tagsinuse 1424.909254 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 71597357 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4688 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15272.473763 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.880841 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695743 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695743 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909254 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695756 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695756 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 492 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 143242775 # Number of tag accesses -system.cpu.icache.tags.data_accesses 143242775 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71614329 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71614329 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71614329 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71614329 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71614329 # number of overall hits -system.cpu.icache.overall_hits::total 71614329 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4706 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4706 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4706 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4706 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4706 # number of overall misses -system.cpu.icache.overall_misses::total 4706 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 186377497 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 186377497 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 186377497 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 186377497 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 186377497 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 186377497 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71619035 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71619035 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71619035 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71619035 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71619035 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71619035 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39604.228007 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39604.228007 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39604.228007 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39604.228007 # average overall miss latency +system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 129 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1067 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 143208780 # Number of tag accesses +system.cpu.icache.tags.data_accesses 143208780 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 71597357 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 71597357 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 71597357 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 71597357 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 71597357 # number of overall hits +system.cpu.icache.overall_hits::total 71597357 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4689 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4689 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4689 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4689 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4689 # number of overall misses +system.cpu.icache.overall_misses::total 4689 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 200362248 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 200362248 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 200362248 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 200362248 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 200362248 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 200362248 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 71602046 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 71602046 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 71602046 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 71602046 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 71602046 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 71602046 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42730.272553 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42730.272553 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42730.272553 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42730.272553 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -575,123 +575,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4706 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4706 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4706 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4706 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4706 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4706 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176047503 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 176047503 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176047503 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 176047503 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176047503 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 176047503 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37409.159159 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37409.159159 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4689 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4689 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4689 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4689 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4689 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4689 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192401752 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 192401752 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192401752 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 192401752 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192401752 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 192401752 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41032.576669 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41032.576669 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2001.520471 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2624 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.942190 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2001.520500 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2606 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.935056 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.029184 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.649056 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 490.842232 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 3.029170 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.676368 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814962 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046010 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.014978 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.061082 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 522 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 153 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 56139 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 56139 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2543 # 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number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 712 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5418 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5401 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4706 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 4689 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1810 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6516 # 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miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992714 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.459626 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461506 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.596225 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.459626 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.597938 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461506 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.596225 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67456.079519 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72431.566456 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68581.127013 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69109.174312 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69109.174312 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67456.079519 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70328.542393 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68729.279279 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67456.079519 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70328.542393 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68729.279279 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.597938 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74492.259704 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78539.952532 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75407.188841 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77124.541284 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77124.541284 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75888.896037 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75888.896037 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -700,115 +700,113 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 14 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2160 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2162 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 618 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2778 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2780 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2160 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2162 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3868 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2160 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2162 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3868 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 118562000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 37228000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155790000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61501500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61501500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 118562000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 98729500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 217291500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 118562000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 98729500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 217291500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134008500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40696500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 174705000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70436750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70436750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134008500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111133250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 245141750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134008500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111133250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 245141750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.512735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514719 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.595476 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54889.814815 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60239.482201 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56079.913607 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56423.394495 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56423.394495 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.595476 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61983.580019 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65851.941748 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62843.525180 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64620.871560 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64620.871560 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 5401 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5400 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9411 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9377 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 13047 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 301120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 13013 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300032 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 417984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 416896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6532 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6515 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 6532 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 6515 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6532 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3282000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6515 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3273500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7517497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7496248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2996736 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3020486 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 2777 # Transaction distribution -system.membus.trans_dist::ReadResp 2777 # Transaction distribution +system.membus.trans_dist::ReadReq 2779 # Transaction distribution +system.membus.trans_dist::ReadResp 2779 # Transaction distribution system.membus.trans_dist::ReadExReq 1090 # Transaction distribution system.membus.trans_dist::ReadExResp 1090 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7734 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7734 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 247488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3867 # Request fanout histogram +system.membus.snoop_fanout::samples 3869 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3867 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3867 # Request fanout histogram -system.membus.reqLayer0.occupancy 4723500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3869 # Request fanout histogram +system.membus.reqLayer0.occupancy 4526500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 36361000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20559250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 30df36f38..bc1d643b6 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085008 # Number of seconds simulated -sim_ticks 85008313500 # Number of ticks simulated -final_tick 85008313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085027 # Number of seconds simulated +sim_ticks 85027009000 # Number of ticks simulated +final_tick 85027009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130085 # Simulator instruction rate (inst/s) -host_op_rate 137131 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64179279 # Simulator tick rate (ticks/s) -host_mem_usage 313784 # Number of bytes of host memory used -host_seconds 1324.54 # Real time elapsed on the host +host_inst_rate 134467 # Simulator instruction rate (inst/s) +host_op_rate 141751 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66356016 # Simulator tick rate (ticks/s) +host_mem_usage 312828 # Number of bytes of host memory used +host_seconds 1281.38 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 181635953 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 127168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 48000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71360 # Number of bytes read from this memory -system.physmem.bytes_read::total 246528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 127168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 127168 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1987 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3852 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1495948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 564651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 839447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2900046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1495948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1495948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1495948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 564651 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 839447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2900046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3852 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 127040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71040 # Number of bytes read from this memory +system.physmem.bytes_read::total 245760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 127040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 127040 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1985 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 745 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1110 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3840 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1494113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 560763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 835499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2890376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1494113 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1494113 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1494113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 560763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 835499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2890376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3840 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3852 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3840 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 246528 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 245760 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 246528 # Total read bytes from the system interface side +system.physmem.bytesReadSys 245760 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 309 # Per bank write bursts -system.physmem.perBankRdBursts::1 223 # Per bank write bursts +system.physmem.perBankRdBursts::1 220 # Per bank write bursts system.physmem.perBankRdBursts::2 142 # Per bank write bursts -system.physmem.perBankRdBursts::3 310 # Per bank write bursts +system.physmem.perBankRdBursts::3 304 # Per bank write bursts system.physmem.perBankRdBursts::4 300 # Per bank write bursts system.physmem.perBankRdBursts::5 302 # Per bank write bursts system.physmem.perBankRdBursts::6 262 # Per bank write bursts system.physmem.perBankRdBursts::7 237 # Per bank write bursts system.physmem.perBankRdBursts::8 252 # Per bank write bursts -system.physmem.perBankRdBursts::9 218 # Per bank write bursts -system.physmem.perBankRdBursts::10 293 # Per bank write bursts +system.physmem.perBankRdBursts::9 219 # Per bank write bursts +system.physmem.perBankRdBursts::10 292 # Per bank write bursts system.physmem.perBankRdBursts::11 194 # Per bank write bursts -system.physmem.perBankRdBursts::12 193 # Per bank write bursts -system.physmem.perBankRdBursts::13 212 # Per bank write bursts +system.physmem.perBankRdBursts::12 191 # Per bank write bursts +system.physmem.perBankRdBursts::13 211 # Per bank write bursts system.physmem.perBankRdBursts::14 211 # Per bank write bursts system.physmem.perBankRdBursts::15 194 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85008170000 # Total gap between requests +system.physmem.totGap 85026865500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3852 # Read request sizes (log2) +system.physmem.readPktSize::6 3840 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,17 +94,17 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 895 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 851 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.936842 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 203.366462 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 304.047629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 237 31.18% 31.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 182 23.95% 55.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 69 9.08% 64.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 96 12.63% 76.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 4.61% 81.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 45 5.92% 87.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 18 2.37% 89.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 14 1.84% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 64 8.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 760 # Bytes accessed per row activation -system.physmem.totQLat 36289181 # Total ticks spent queuing -system.physmem.totMemAccLat 108514181 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19260000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9420.87 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 319.332464 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 200.822648 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.559029 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 236 30.77% 30.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 188 24.51% 55.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 81 10.56% 65.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 90 11.73% 77.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 32 4.17% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 41 5.35% 87.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 12 1.56% 88.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 2.09% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 71 9.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 767 # Bytes accessed per row activation +system.physmem.totQLat 42919435 # Total ticks spent queuing +system.physmem.totMemAccLat 114919435 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11176.94 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28170.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29926.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.89 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.89 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 3.02 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3085 # Number of row buffer hits during reads +system.physmem.readRowHits 3071 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.09 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.97 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 22068579.96 # Average gap between requests -system.physmem.pageHitRate 80.09 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2721600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1485000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16239600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 22142412.89 # Average gap between requests +system.physmem.pageHitRate 79.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2691360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1468500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16192800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5551949520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2339255205 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 48949672500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 56861323425 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.935094 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81434793722 # Time in different power states -system.physmem_0.memoryStateTime::REF 2838420000 # Time in different power states +system.physmem_0.refreshEnergy 5553475200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2327866605 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48973677750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 56875372215 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.916551 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81470624236 # Time in different power states +system.physmem_0.memoryStateTime::REF 2839200000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 733662278 # Time in different power states +system.physmem_0.memoryStateTime::ACT 716299514 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3001320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1637625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13540800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3107160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1695375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13657800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5551949520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2301878880 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 48982450500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 56854458645 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.854443 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 81486384408 # Time in different power states -system.physmem_1.memoryStateTime::REF 2838420000 # Time in different power states +system.physmem_1.refreshEnergy 5553475200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2285718525 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 49010649750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56868303810 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.833418 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 81532427147 # Time in different power states +system.physmem_1.memoryStateTime::REF 2839200000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 678791592 # Time in different power states +system.physmem_1.memoryStateTime::ACT 654496603 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 85929478 # Number of BP lookups -system.cpu.branchPred.condPredicted 68409655 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6016514 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40103730 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39019729 # Number of BTB hits +system.cpu.branchPred.lookups 85926168 # Number of BP lookups +system.cpu.branchPred.condPredicted 68405800 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6016539 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 40105937 # Number of BTB lookups +system.cpu.branchPred.BTBHits 39014203 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.297007 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3701200 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81899 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.277874 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3700977 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81896 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,96 +381,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 170016628 # number of cpu cycles simulated +system.cpu.numCycles 170054019 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5612512 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349284796 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85929478 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42720929 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158258026 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12046973 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1522 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5612946 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349281739 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85926168 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42715180 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158272644 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12047045 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1757 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 2068 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78953849 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 17938 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169897637 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.150791 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.046975 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 2232 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78951619 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 17953 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169913124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.150597 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.047113 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17345965 10.21% 10.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30201314 17.78% 27.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31838054 18.74% 46.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90512304 53.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17360928 10.22% 10.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30199989 17.77% 27.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31841897 18.74% 46.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90510310 53.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169897637 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.505418 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.054416 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17565023 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17095500 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122663721 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6724834 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5848559 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11136257 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 190151 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306621954 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27645544 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5848559 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37752791 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8406678 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 578098 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108929543 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8381968 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278665579 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13416120 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3045260 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 842372 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2187359 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 31268 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 80203 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483123422 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1196973277 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297590130 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3005585 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169913124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.505287 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.053946 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17565564 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17109843 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 122664763 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6724358 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5848596 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11135936 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 189930 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 306620744 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27649027 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5848596 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37751386 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8466295 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 579465 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108929053 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8338329 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 278664885 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13415182 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3050613 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 842331 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2187361 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 37352 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 26454 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 483122463 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1196977553 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 297589838 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3006277 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190146493 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23524 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23418 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13341047 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34139788 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14476953 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2546690 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1793951 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 264825375 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45850 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214906973 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5192109 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82644277 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219958197 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 634 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169897637 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.264920 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017502 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 190145534 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23528 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23432 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13338171 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 34140942 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14477069 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2549253 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1790153 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 264824262 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45858 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214907174 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5191222 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82643318 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 219950944 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 642 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169913124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.264806 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017451 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52826553 31.09% 31.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36096362 21.25% 52.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65782146 38.72% 91.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13572889 7.99% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1571303 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47864 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 520 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52840350 31.10% 31.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36091754 21.24% 52.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65793999 38.72% 91.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13568282 7.99% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1571301 0.92% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47256 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 182 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169897637 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169913124 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35601312 66.11% 66.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 152935 0.28% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35600908 66.11% 66.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 152918 0.28% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.39% # attempts to use FU when none available @@ -489,22 +489,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.39% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1069 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1064 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35738 0.07% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 318 0.00% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35736 0.07% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 241 0.00% 66.46% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 812 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34382 0.06% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 216 0.00% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 1033 0.00% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34370 0.06% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14078938 26.14% 92.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3947834 7.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14078817 26.14% 92.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3947857 7.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167350726 77.87% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918985 0.43% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167349433 77.87% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 918954 0.43% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued @@ -523,93 +523,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33019 0.02% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33017 0.02% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165190 0.08% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245718 0.11% 78.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165198 0.08% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245711 0.11% 78.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460475 0.21% 78.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460497 0.21% 78.75% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 206696 0.10% 78.85% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32004909 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13373295 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32005154 14.89% 93.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13374554 6.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214906973 # Type of FU issued -system.cpu.iq.rate 1.264035 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53853755 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.250591 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654805304 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 345511813 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204602678 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3952143 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2010627 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806422 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266627552 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2133176 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1600193 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214907174 # Type of FU issued +system.cpu.iq.rate 1.263758 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53853149 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.250588 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654819591 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 345508564 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204603377 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3952252 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2011834 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806382 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266627232 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2133091 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1600790 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6243644 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7556 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7106 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1832319 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6244798 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7531 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7120 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1832435 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25875 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 661 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25844 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 768 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5848559 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5681569 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 36478 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 264887188 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5848596 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5681557 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 36821 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 264886087 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34139788 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14476953 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23442 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3814 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29479 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7106 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3233640 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3247282 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6480922 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207527385 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30721175 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7379588 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 34140942 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14477069 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23450 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3913 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29719 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7120 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3233413 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3247375 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6480788 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207526427 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30720305 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7380747 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15963 # number of nop insts executed -system.cpu.iew.exec_refs 43860513 # number of memory reference insts executed -system.cpu.iew.exec_branches 44937173 # Number of branches executed -system.cpu.iew.exec_stores 13139338 # Number of stores executed -system.cpu.iew.exec_rate 1.220630 # Inst execution rate -system.cpu.iew.wb_sent 206744227 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206409100 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129466460 # num instructions producing a value -system.cpu.iew.wb_consumers 221676348 # num instructions consuming a value +system.cpu.iew.exec_nop 15967 # number of nop insts executed +system.cpu.iew.exec_refs 43860812 # number of memory reference insts executed +system.cpu.iew.exec_branches 44937004 # Number of branches executed +system.cpu.iew.exec_stores 13140507 # Number of stores executed +system.cpu.iew.exec_rate 1.220356 # Inst execution rate +system.cpu.iew.wb_sent 206744573 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206409759 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129475490 # num instructions producing a value +system.cpu.iew.wb_consumers 221697589 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.214052 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584034 # average fanout of values written-back +system.cpu.iew.wb_rate 1.213789 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.584018 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69543087 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69541306 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5841587 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158455572 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.146380 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.646562 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5841613 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158471260 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146267 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.646384 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73674398 46.50% 46.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41276379 26.05% 72.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22551197 14.23% 86.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9630660 6.08% 92.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3550983 2.24% 95.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2150131 1.36% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1280461 0.81% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 988669 0.62% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3352694 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73683520 46.50% 46.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41279039 26.05% 72.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22557642 14.23% 86.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9629639 6.08% 92.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3553008 2.24% 95.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2147976 1.36% 96.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1280790 0.81% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 986719 0.62% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3352927 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158455572 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158471260 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 181650341 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,186 +655,186 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction -system.cpu.commit.bw_lim_events 3352694 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3352927 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 406291105 # The number of ROB reads -system.cpu.rob.rob_writes 513842853 # The number of ROB writes -system.cpu.timesIdled 3394 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 118991 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 406304779 # The number of ROB reads +system.cpu.rob.rob_writes 513839131 # The number of ROB writes +system.cpu.timesIdled 3408 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 140895 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 181635953 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.986730 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.986730 # CPI: Total CPI of All Threads -system.cpu.ipc 1.013448 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.013448 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218960053 # number of integer regfile reads -system.cpu.int_regfile_writes 114514072 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904445 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441481 # number of floating regfile writes -system.cpu.cc_regfile_reads 709585079 # number of cc regfile reads -system.cpu.cc_regfile_writes 229544416 # number of cc regfile writes -system.cpu.misc_regfile_reads 59313443 # number of misc regfile reads +system.cpu.cpi 0.986947 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.986947 # CPI: Total CPI of All Threads +system.cpu.ipc 1.013225 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.013225 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218958782 # number of integer regfile reads +system.cpu.int_regfile_writes 114515411 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904346 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441525 # number of floating regfile writes +system.cpu.cc_regfile_reads 709584302 # number of cc regfile reads +system.cpu.cc_regfile_writes 229541480 # number of cc regfile writes +system.cpu.misc_regfile_reads 59315386 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.replacements 72897 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.439547 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41117509 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73409 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.115367 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 497141250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.439547 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998905 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998905 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 72889 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.417696 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41115745 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73401 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 560.152382 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 506067250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.417696 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998863 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 222 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82532283 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82532283 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28730746 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28730746 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341850 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341850 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82529901 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82529901 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28729389 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28729389 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341441 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341441 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22145 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22145 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41072596 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41072596 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41072957 # number of overall hits -system.cpu.dcache.overall_hits::total 41072957 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89111 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89111 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22437 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22437 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 262 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 262 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 111548 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 111548 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 111666 # number of overall misses -system.cpu.dcache.overall_misses::total 111666 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 835319240 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 835319240 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 222952999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 222952999 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2325000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2325000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1058272239 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1058272239 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1058272239 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1058272239 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28819857 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28819857 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 41070830 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41070830 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41071191 # number of overall hits +system.cpu.dcache.overall_hits::total 41071191 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89283 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89283 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22846 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22846 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 112129 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112129 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112245 # number of overall misses +system.cpu.dcache.overall_misses::total 112245 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 853218237 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 853218237 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 244809935 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 244809935 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2319500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2319500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1098028172 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1098028172 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1098028172 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1098028172 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28818672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28818672 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 477 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 477 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41184144 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41184144 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41184623 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41184623 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003092 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003092 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001815 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001815 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011693 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011693 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002709 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002709 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002711 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002711 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9373.918371 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9373.918371 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9936.845345 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9936.845345 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8874.045802 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8874.045802 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9487.146690 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9487.146690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9477.121407 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9477.121407 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 122 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7730 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41182959 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41182959 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41183436 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41183436 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003098 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003098 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001848 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001848 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.243187 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.243187 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011604 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002723 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002723 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002725 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002725 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9556.334767 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9556.334767 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10715.658540 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10715.658540 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8921.153846 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8921.153846 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9792.544052 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9792.544052 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9782.423912 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9782.423912 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 167 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10490 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 532 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 61 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 14.530075 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 844 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 12.428910 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 64874 # number of writebacks -system.cpu.dcache.writebacks::total 64874 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24383 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24383 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 13871 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 13871 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 262 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 262 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38254 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38254 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38254 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38254 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64728 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64728 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8566 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8566 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 115 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 115 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 73294 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 73294 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73409 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73409 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 491417758 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 491417758 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 74043249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 74043249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 982500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 982500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 565461007 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 565461007 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 566443507 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 566443507 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 64871 # number of writebacks +system.cpu.dcache.writebacks::total 64871 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24560 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24560 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14281 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14281 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 38841 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 38841 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 38841 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 38841 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64723 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64723 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8565 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8565 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 73288 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 73288 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73401 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73401 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 526941010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 526941010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81775757 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 81775757 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 905500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 905500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 608716767 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 608716767 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 609622267 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 609622267 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002246 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002246 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.240084 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.240084 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.236897 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.236897 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001780 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001782 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7592.042980 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7592.042980 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8643.853491 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8643.853491 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8543.478261 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8543.478261 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7714.969943 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7714.969943 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7716.267855 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7716.267855 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8141.479999 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8141.479999 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9547.665733 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9547.665733 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8013.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8013.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8305.817692 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8305.817692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8305.367325 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8305.367325 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 54440 # number of replacements -system.cpu.icache.tags.tagsinuse 510.617911 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78896507 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54952 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1435.734951 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 84258685250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.617911 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997301 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997301 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 54441 # number of replacements +system.cpu.icache.tags.tagsinuse 510.602621 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78893897 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54953 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1435.661329 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84271974250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.602621 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997271 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997271 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id @@ -842,188 +842,188 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 272 system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157962600 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157962600 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78896507 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78896507 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78896507 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78896507 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78896507 # number of overall hits -system.cpu.icache.overall_hits::total 78896507 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57317 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57317 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57317 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57317 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57317 # number of overall misses -system.cpu.icache.overall_misses::total 57317 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 586515679 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 586515679 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 586515679 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 586515679 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 586515679 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 586515679 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78953824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78953824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78953824 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78953824 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78953824 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78953824 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000726 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000726 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000726 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000726 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000726 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000726 # 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number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 120193759 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33127750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 153321509 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 68601184 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 68601184 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16505250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16505250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 120193759 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 49633000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 169826759 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 120193759 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 49633000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 68601184 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 238427943 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.036122 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.007828 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.020816 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027209 # 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mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036122 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.035470 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52440.613991 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58060.679612 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53597.422062 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34908.254405 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34908.254405 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56717.021277 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65340.729783 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61525.485152 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37943.132743 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37943.132743 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69349.789916 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69349.789916 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60551.012091 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66621.476510 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62207.604029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60551.012091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66621.476510 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37943.132743 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52540.313574 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 119724 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 119724 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 64874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8637 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8637 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109904 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 321596 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8850112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 12367040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2213 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 195448 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.011323 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105804 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 119718 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 119718 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 64871 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2155 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8636 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8636 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109906 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211673 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 321579 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8849408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12366400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2155 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 195380 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011030 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.104442 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 193235 98.87% 98.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 2213 1.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 193225 98.90% 98.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 2155 1.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 195448 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 161491500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 195380 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 161483500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82814471 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 82836732 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110208992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 110205232 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3617 # Transaction distribution -system.membus.trans_dist::ReadResp 3617 # Transaction distribution -system.membus.trans_dist::ReadExReq 235 # Transaction distribution -system.membus.trans_dist::ReadExResp 235 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7704 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7704 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 246528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 246528 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 3602 # Transaction distribution +system.membus.trans_dist::ReadResp 3602 # Transaction distribution +system.membus.trans_dist::ReadExReq 238 # Transaction distribution +system.membus.trans_dist::ReadExResp 238 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7680 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7680 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 245760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 245760 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3852 # Request fanout histogram +system.membus.snoop_fanout::samples 3840 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3852 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3840 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3852 # Request fanout histogram -system.membus.reqLayer0.occupancy 5007645 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3840 # Request fanout histogram +system.membus.reqLayer0.occupancy 4975502 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 36124927 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20238053 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 7ececc2b6..e6a9622eb 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.099596 # Nu sim_ticks 99596491000 # Number of ticks simulated final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1699536 # Simulator instruction rate (inst/s) -host_op_rate 1791584 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 982302061 # Simulator tick rate (ticks/s) -host_mem_usage 304728 # Number of bytes of host memory used -host_seconds 101.39 # Real time elapsed on the host +host_inst_rate 1940320 # Simulator instruction rate (inst/s) +host_op_rate 2045410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1121471108 # Simulator tick rate (ticks/s) +host_mem_usage 304628 # Number of bytes of host memory used +host_seconds 88.81 # Real time elapsed on the host sim_insts 172317409 # Number of instructions simulated sim_ops 181650341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 230024466 # Request fanout histogram -system.membus.snoop_fanout::mean 4.825391 # Request fanout histogram +system.membus.snoop_fanout::mean 2.825391 # Request fanout histogram system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 40164415 17.46% 17.46% # Request fanout histogram -system.membus.snoop_fanout::5 189860051 82.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 40164415 17.46% 17.46% # Request fanout histogram +system.membus.snoop_fanout::3 189860051 82.54% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 230024466 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 62a10ca2c..6ce1a7f0e 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.230173 # Number of seconds simulated -sim_ticks 230173357000 # Number of ticks simulated -final_tick 230173357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 230173357500 # Number of ticks simulated +final_tick 230173357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1229194 # Simulator instruction rate (inst/s) -host_op_rate 1295881 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1646435898 # Simulator tick rate (ticks/s) -host_mem_usage 312932 # Number of bytes of host memory used -host_seconds 139.80 # Real time elapsed on the host +host_inst_rate 1098511 # Simulator instruction rate (inst/s) +host_op_rate 1158108 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1471393960 # Simulator tick rate (ticks/s) +host_mem_usage 313104 # Number of bytes of host memory used +host_seconds 156.43 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 181165370 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 460346714 # number of cpu cycles simulated +system.cpu.numCycles 460346715 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 171842483 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 40540779 # nu system.cpu.num_load_insts 27896144 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 460346713.998000 # Number of busy cycles +system.cpu.num_busy_cycles 460346714.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 40300311 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650742 # Class of executed instruction system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.619284 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1363.619277 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619284 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619277 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id @@ -309,16 +309,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1788 system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34093000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34093000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57994500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 57994500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 92087500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92140500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 92140500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34437000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34437000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58544500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 58544500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92981500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 92981500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93035000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 93035000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -329,24 +329,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50053.779070 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50053.779070 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53222.272727 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53222.272727 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52003.076063 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52003.076063 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52003.912800 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52003.912800 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1506 # number of replacements -system.cpu.icache.tags.tagsinuse 1147.992604 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1147.992598 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992604 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992598 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id @@ -370,12 +370,12 @@ system.cpu.icache.demand_misses::cpu.inst 3051 # n system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses system.cpu.icache.overall_misses::total 3051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 112370500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 112370500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 112370500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 112370500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 112370500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 112370500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 112371000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 112371000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 112371000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 112371000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 112371000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 112371000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses @@ -388,12 +388,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.711242 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36830.711242 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.711242 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36830.711242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.711242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36830.711242 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.875123 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36830.875123 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36830.875123 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36830.875123 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,34 +408,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3051 system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106268500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 106268500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106268500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 106268500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106268500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 106268500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 107794500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 107794500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 107794500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 107794500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 107794500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 107794500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34830.711242 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34830.711242 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34830.711242 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34830.711242 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34830.711242 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34830.711242 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35330.875123 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35330.875123 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35330.875123 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35330.875123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1675.663358 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 1675.663349 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036759 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588821 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036753 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588818 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy @@ -473,17 +473,17 @@ system.cpu.l2cache.demand_misses::total 3453 # nu system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses system.cpu.l2cache.overall_misses::total 3453 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 89997500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32887000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 122884500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56814500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 56814500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 89997500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 89701500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 179699000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 89997500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 89701500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 179699000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 90862500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 33203000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 124065500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57360500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 57360500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 90862500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 90563500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 181426000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 90862500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 90563500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 181426000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3051 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 689 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses) @@ -508,17 +508,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.713430 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52051.764025 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52036.392405 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52047.649301 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52027.930403 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52027.930403 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52051.764025 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52031.032483 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52041.413264 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52051.764025 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52031.032483 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52041.413264 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52552.053210 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52536.392405 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52547.861076 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52527.930403 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52527.930403 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52541.558065 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52541.558065 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,17 +538,17 @@ system.cpu.l2cache.demand_mshr_misses::total 3453 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94440000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 138120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 138120000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70024500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25596000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 95620500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44226000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44226000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70024500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 69822000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 139846500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70024500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 69822000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 139846500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.631283 # mshr miss rate for ReadReq accesses @@ -560,17 +560,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution @@ -585,19 +585,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 4856 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4856 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) @@ -624,9 +622,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3453 # Request fanout histogram -system.membus.reqLayer0.occupancy 3596000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3596500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 31220000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 17408500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 66a194e38..e9f2af2a4 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.270563 # Number of seconds simulated -sim_ticks 270563082000 # Number of ticks simulated -final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 270563082500 # Number of ticks simulated +final_tick 270563082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1449498 # Simulator instruction rate (inst/s) -host_op_rate 1449499 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2027353723 # Simulator tick rate (ticks/s) -host_mem_usage 294428 # Number of bytes of host memory used -host_seconds 133.46 # Real time elapsed on the host +host_inst_rate 1283602 # Simulator instruction rate (inst/s) +host_op_rate 1283603 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1795321724 # Simulator tick rate (ticks/s) +host_mem_usage 297332 # Number of bytes of host memory used +host_seconds 150.70 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,32 +29,9 @@ system.physmem.bw_inst_read::total 850848 # In system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 4095 # Transaction distribution -system.membus.trans_dist::ReadResp 4095 # Transaction distribution -system.membus.trans_dist::ReadExReq 1078 # Transaction distribution -system.membus.trans_dist::ReadExResp 1078 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5173 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5173 # Request fanout histogram -system.membus.reqLayer0.occupancy 5173000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 46557000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 401 # Number of system calls -system.cpu.numCycles 541126164 # number of cpu cycles simulated +system.cpu.numCycles 541126165 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 193444518 # Number of instructions committed @@ -73,7 +50,7 @@ system.cpu.num_mem_refs 76733958 # nu system.cpu.num_load_insts 57735091 # Number of load instructions system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 541126163.998000 # Number of busy cycles +system.cpu.num_busy_cycles 541126164.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 15132745 # Number of branches fetched @@ -112,13 +89,142 @@ system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 193445773 # Class of executed instruction +system.cpu.dcache.tags.replacements 2 # number of replacements +system.cpu.dcache.tags.tagsinuse 1237.203936 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203936 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits +system.cpu.dcache.overall_hits::total 76709932 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses +system.cpu.dcache.overall_misses::total 1575 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2 # number of writebacks +system.cpu.dcache.writebacks::total 2 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26643000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26643000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57619500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 57619500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 53500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84262500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 84262500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84262500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 84262500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53500 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10362 # number of replacements -system.cpu.icache.tags.tagsinuse 1591.579171 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1591.579164 # Cycle average of tags in use system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579164 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id @@ -142,12 +248,12 @@ system.cpu.icache.demand_misses::cpu.inst 12288 # n system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses system.cpu.icache.overall_misses::total 12288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 310818000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 310818000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 310818000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 310818000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 310818000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 310818500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 310818500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 310818500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 310818500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 310818500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses @@ -160,12 +266,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.433594 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25294.433594 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25294.433594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25294.433594 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.474284 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25294.474284 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25294.474284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25294.474284 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -180,34 +286,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 12288 system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 286242000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 286242000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 286242000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 286242000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 286242000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 286242000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292386500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 292386500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292386500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 292386500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292386500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 292386500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23294.433594 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23294.433594 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23794.474284 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23794.474284 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23794.474284 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23794.474284 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23794.474284 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23794.474284 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2678.340865 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2678.340853 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282913 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057487 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy @@ -240,17 +346,17 @@ system.cpu.l2cache.demand_misses::total 5173 # nu system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses system.cpu.l2cache.overall_misses::total 5173 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 187044000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25896000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 212940000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56056000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 56056000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 187044000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 81952000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 268996000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 187044000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 81952000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 268996000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 188843000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 26145000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 214988000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56595000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 56595000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 188843000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 82740000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 271583000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 188843000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 82740000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 271583000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 12288 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 498 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 12786 # number of ReadReq accesses(hits+misses) @@ -275,17 +381,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.373125 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.139005 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.122100 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.096656 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.096656 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -305,17 +411,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5173 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63040000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 206920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63040000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 206920000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145678500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20169000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 165847500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43659000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43659000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145678500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63828000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 209506500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145678500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63828000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 209506500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320272 # mshr miss rate for ReadReq accesses @@ -327,147 +433,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # 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Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits -system.cpu.dcache.overall_hits::total 76709932 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 1 # 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number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83475000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 83475000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83475000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 83475000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 12786 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution @@ -497,5 +474,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 18432000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 4095 # Transaction distribution +system.membus.trans_dist::ReadResp 4095 # Transaction distribution +system.membus.trans_dist::ReadExReq 1078 # Transaction distribution +system.membus.trans_dist::ReadExResp 1078 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5173 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5173 # Request fanout histogram +system.membus.reqLayer0.occupancy 5173500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 25865500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 85460c89a..e5c937252 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.148652 # Number of seconds simulated -sim_ticks 148652306000 # Number of ticks simulated -final_tick 148652306000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.148669 # Number of seconds simulated +sim_ticks 148668850500 # Number of ticks simulated +final_tick 148668850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 83185 # Simulator instruction rate (inst/s) -host_op_rate 139426 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 93628996 # Simulator tick rate (ticks/s) -host_mem_usage 346568 # Number of bytes of host memory used -host_seconds 1587.67 # Real time elapsed on the host +host_inst_rate 82634 # Simulator instruction rate (inst/s) +host_op_rate 138502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 93018548 # Simulator tick rate (ticks/s) +host_mem_usage 346916 # Number of bytes of host memory used +host_seconds 1598.27 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 224768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125696 # Number of bytes read from this memory -system.physmem.bytes_read::total 350464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 224768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 224768 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3512 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1964 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5476 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1512038 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 845570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2357609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1512038 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1512038 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1512038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 845570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2357609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5476 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 225344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125504 # Number of bytes read from this memory +system.physmem.bytes_read::total 350848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 225344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 225344 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3521 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1961 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5482 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1515745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 844185 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2359929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1515745 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1515745 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1515745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 844185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2359929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5482 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5476 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5482 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 350464 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 350848 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 350464 # Total read bytes from the system interface side +system.physmem.bytesReadSys 350848 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 324 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 295 # Per bank write bursts -system.physmem.perBankRdBursts::1 363 # Per bank write bursts -system.physmem.perBankRdBursts::2 461 # Per bank write bursts -system.physmem.perBankRdBursts::3 370 # Per bank write bursts -system.physmem.perBankRdBursts::4 335 # Per bank write bursts -system.physmem.perBankRdBursts::5 334 # Per bank write bursts -system.physmem.perBankRdBursts::6 400 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 345 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 294 # Per bank write bursts +system.physmem.perBankRdBursts::1 364 # Per bank write bursts +system.physmem.perBankRdBursts::2 457 # Per bank write bursts +system.physmem.perBankRdBursts::3 371 # Per bank write bursts +system.physmem.perBankRdBursts::4 339 # Per bank write bursts +system.physmem.perBankRdBursts::5 333 # Per bank write bursts +system.physmem.perBankRdBursts::6 398 # Per bank write bursts system.physmem.perBankRdBursts::7 383 # Per bank write bursts -system.physmem.perBankRdBursts::8 340 # Per bank write bursts -system.physmem.perBankRdBursts::9 286 # Per bank write bursts -system.physmem.perBankRdBursts::10 236 # Per bank write bursts -system.physmem.perBankRdBursts::11 261 # Per bank write bursts -system.physmem.perBankRdBursts::12 219 # Per bank write bursts -system.physmem.perBankRdBursts::13 509 # Per bank write bursts -system.physmem.perBankRdBursts::14 392 # Per bank write bursts -system.physmem.perBankRdBursts::15 292 # Per bank write bursts +system.physmem.perBankRdBursts::8 344 # Per bank write bursts +system.physmem.perBankRdBursts::9 280 # Per bank write bursts +system.physmem.perBankRdBursts::10 239 # Per bank write bursts +system.physmem.perBankRdBursts::11 268 # Per bank write bursts +system.physmem.perBankRdBursts::12 225 # Per bank write bursts +system.physmem.perBankRdBursts::13 502 # Per bank write bursts +system.physmem.perBankRdBursts::14 395 # Per bank write bursts +system.physmem.perBankRdBursts::15 290 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 148652208500 # Total gap between requests +system.physmem.totGap 148668756000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5476 # Read request sizes (log2) +system.physmem.readPktSize::6 5482 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 909 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 304.265039 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.960981 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.625541 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 464 40.45% 40.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 245 21.36% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 104 9.07% 70.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 57 4.97% 75.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 54 4.71% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 57 4.97% 85.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24 2.09% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 15 1.31% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 127 11.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1147 # Bytes accessed per row activation -system.physmem.totQLat 37377750 # Total ticks spent queuing -system.physmem.totMemAccLat 140052750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 27380000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6825.74 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1140 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 306.470175 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.641766 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.557853 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 448 39.30% 39.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 255 22.37% 61.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 105 9.21% 70.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 70 6.14% 77.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 38 3.33% 80.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 59 5.18% 85.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 19 1.67% 87.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 18 1.58% 88.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 128 11.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1140 # Bytes accessed per row activation +system.physmem.totQLat 40930250 # Total ticks spent queuing +system.physmem.totMemAccLat 143717750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 27410000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7466.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25575.74 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26216.30 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.36 # Average system read bandwidth in MiByte/s @@ -214,286 +214,285 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4321 # Number of row buffer hits during reads +system.physmem.readRowHits 4334 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.91 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.06 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 27146130.11 # Average gap between requests -system.physmem.pageHitRate 78.91 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5072760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2767875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 22791600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 27119437.43 # Average gap between requests +system.physmem.pageHitRate 79.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 22776000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 9708918960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4015280925 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 85666359000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 99421191120 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.838371 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 142511183750 # Time in different power states -system.physmem_0.memoryStateTime::REF 4963660000 # Time in different power states +system.physmem_0.refreshEnergy 9709936080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4021675470 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 85670093250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 99432251325 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.842708 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 142518159000 # Time in different power states +system.physmem_0.memoryStateTime::REF 4964180000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1172773250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1181750000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3575880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1951125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19585800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3568320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1947000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19648200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 9708918960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3861811845 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 85800972750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 99396816360 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.674456 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 142739163750 # Time in different power states -system.physmem_1.memoryStateTime::REF 4963660000 # Time in different power states +system.physmem_1.refreshEnergy 9709936080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3821631120 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 85845562500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 99402293220 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.641253 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 142814554750 # Time in different power states +system.physmem_1.memoryStateTime::REF 4964180000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 947728750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 888260750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 22375930 # Number of BP lookups -system.cpu.branchPred.condPredicted 22375930 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1550820 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 14142904 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13245564 # Number of BTB hits +system.cpu.branchPred.lookups 22385702 # Number of BP lookups +system.cpu.branchPred.condPredicted 22385702 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1554139 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 14132286 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13246709 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.655193 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1524021 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21798 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.733661 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1526841 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 22095 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 297304620 # number of cpu cycles simulated +system.cpu.numCycles 297337717 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27866919 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 248846814 # Number of instructions fetch has processed -system.cpu.fetch.Branches 22375930 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 14769585 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 267364531 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3698749 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 56 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 42690 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 27888104 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 249064218 # Number of instructions fetch has processed +system.cpu.fetch.Branches 22385702 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 14773550 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 267343346 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3703385 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 34 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 48972 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 111 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 26638460 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 257102 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 297128244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.381645 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.790124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 83 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 26656558 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 259176 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 297137957 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.382061 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.790607 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 229068376 77.09% 77.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5099613 1.72% 78.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4127262 1.39% 80.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4784384 1.61% 81.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4893969 1.65% 83.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5110538 1.72% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5334476 1.80% 86.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3994023 1.34% 88.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34715603 11.68% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 229077480 77.09% 77.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5080600 1.71% 78.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4128062 1.39% 80.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4791015 1.61% 81.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4884919 1.64% 83.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5103681 1.72% 85.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5337561 1.80% 86.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4007445 1.35% 88.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34727194 11.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 297128244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075263 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.837010 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16329336 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 230975824 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 26113582 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21860128 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1849374 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 359242894 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1849374 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24118008 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 162656356 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 38273 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 38263619 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 70202614 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 350538626 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 41453 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 61947521 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7945702 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 153558 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 405817730 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 972424276 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 641996744 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4657501 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 297137957 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075287 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.837648 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16350382 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 230944995 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 26142980 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21847908 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1851692 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 359376016 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1851692 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24144395 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 162574126 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 34810 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 38280834 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70252100 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 350628030 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 42505 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 62013521 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7956456 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 170486 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 405834886 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 972854229 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 642281329 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4678301 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 146388280 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2397 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2322 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 128546417 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89512895 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 32023027 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 63891013 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21581901 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 341300793 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5145 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 266928835 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 76764 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 119543073 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 250225997 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3900 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 297128244 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.898362 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.364631 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 146405436 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2386 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2313 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 128573116 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89639956 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 32032649 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 63973866 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21576036 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 341334735 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4899 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 266857181 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 74594 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 119571219 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 250511173 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3654 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 297137957 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.898092 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.364162 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 171384973 57.68% 57.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 54250707 18.26% 75.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33605057 11.31% 87.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19187938 6.46% 93.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10808168 3.64% 97.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4369052 1.47% 98.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2227260 0.75% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 898004 0.30% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 397085 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 171399069 57.68% 57.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54278133 18.27% 75.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33575860 11.30% 87.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19165859 6.45% 93.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10861721 3.66% 97.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4344660 1.46% 98.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2227090 0.75% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 887493 0.30% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 398072 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 297128244 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 297137957 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 240256 7.42% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2591676 80.04% 87.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 406020 12.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 235011 7.30% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2578157 80.11% 87.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 405217 12.59% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211341 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167360520 62.70% 63.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 793230 0.30% 63.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7036198 2.64% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1213739 0.45% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 66512723 24.92% 91.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22801084 8.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211344 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167292419 62.69% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 790150 0.30% 63.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035672 2.64% 66.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1215098 0.46% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 66512451 24.92% 91.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22800047 8.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 266928835 # Type of FU issued -system.cpu.iq.rate 0.897829 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3237952 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012130 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 829304993 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 456859927 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 261005005 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4995637 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4315017 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2397122 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266441955 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2513491 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18899538 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 266857181 # Type of FU issued +system.cpu.iq.rate 0.897488 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3218385 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012060 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 829150425 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 456900250 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 260922611 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4994873 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4333463 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2397328 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266351243 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2512979 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18909810 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 32863308 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14004 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 331776 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11507310 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 32990369 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14136 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 328607 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11516932 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 52520 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 52167 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1849374 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 126083228 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5521965 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 341305938 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 113234 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89512895 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 32023027 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2291 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2224383 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 364956 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 331776 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 682604 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 926974 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1609578 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 264820941 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 65644877 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2107894 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1851692 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 126137646 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5532810 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 341339634 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 112602 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89639956 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 32032649 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2212 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2223479 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 382778 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 328607 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 684628 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 928175 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1612803 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 264737771 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 65643847 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2119410 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 88243318 # number of memory reference insts executed -system.cpu.iew.exec_branches 14594562 # Number of branches executed -system.cpu.iew.exec_stores 22598441 # Number of stores executed -system.cpu.iew.exec_rate 0.890739 # Inst execution rate -system.cpu.iew.wb_sent 264116022 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 263402127 # cumulative count of insts written-back -system.cpu.iew.wb_producers 208929627 # num instructions producing a value -system.cpu.iew.wb_consumers 376950815 # num instructions consuming a value +system.cpu.iew.exec_refs 88241442 # number of memory reference insts executed +system.cpu.iew.exec_branches 14589088 # Number of branches executed +system.cpu.iew.exec_stores 22597595 # Number of stores executed +system.cpu.iew.exec_rate 0.890361 # Inst execution rate +system.cpu.iew.wb_sent 264036391 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 263319939 # cumulative count of insts written-back +system.cpu.iew.wb_producers 208896510 # num instructions producing a value +system.cpu.iew.wb_consumers 376872402 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.885967 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.554262 # average fanout of values written-back +system.cpu.iew.wb_rate 0.885592 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.554290 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119991036 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 120026923 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1555160 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 280815934 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.788286 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.594389 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1559493 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 280830334 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.788246 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.594394 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 180962849 64.44% 64.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57749972 20.57% 85.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14199777 5.06% 90.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11927311 4.25% 94.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4203723 1.50% 95.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2893126 1.03% 96.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 916943 0.33% 97.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1048119 0.37% 97.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6914114 2.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 180946233 64.43% 64.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57795535 20.58% 85.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14201408 5.06% 90.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11929876 4.25% 94.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4188274 1.49% 95.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2885386 1.03% 96.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 910038 0.32% 97.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1053521 0.38% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6920063 2.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 280815934 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 280830334 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -539,336 +538,336 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6914114 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6920063 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 615256240 # The number of ROB reads -system.cpu.rob.rob_writes 699066092 # The number of ROB writes -system.cpu.timesIdled 3079 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 176376 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 615300578 # The number of ROB reads +system.cpu.rob.rob_writes 699132843 # The number of ROB writes +system.cpu.timesIdled 3156 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 199760 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.251094 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.251094 # CPI: Total CPI of All Threads -system.cpu.ipc 0.444229 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.444229 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 456513966 # number of integer regfile reads -system.cpu.int_regfile_writes 239334814 # number of integer regfile writes -system.cpu.fp_regfile_reads 3274089 # number of floating regfile reads -system.cpu.fp_regfile_writes 2057271 # number of floating regfile writes -system.cpu.cc_regfile_reads 102998380 # number of cc regfile reads -system.cpu.cc_regfile_writes 60202762 # number of cc regfile writes -system.cpu.misc_regfile_reads 136901121 # number of misc regfile reads +system.cpu.cpi 2.251344 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.251344 # CPI: Total CPI of All Threads +system.cpu.ipc 0.444179 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.444179 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 456486870 # number of integer regfile reads +system.cpu.int_regfile_writes 239256029 # number of integer regfile writes +system.cpu.fp_regfile_reads 3277423 # number of floating regfile reads +system.cpu.fp_regfile_writes 2057707 # number of floating regfile writes +system.cpu.cc_regfile_reads 102994410 # number of cc regfile reads +system.cpu.cc_regfile_writes 60201710 # number of cc regfile writes +system.cpu.misc_regfile_reads 136869897 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.replacements 52 # number of replacements -system.cpu.dcache.tags.tagsinuse 1443.647680 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 67095165 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2013 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33330.931446 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 51 # number of replacements +system.cpu.dcache.tags.tagsinuse 1444.566400 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 67084714 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2000 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33542.357000 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1443.647680 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.352453 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.352453 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1961 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 441 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1444.566400 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352677 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352677 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1949 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1405 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.478760 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 134197329 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 134197329 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 46580786 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 46580786 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513865 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513865 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 67094651 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 67094651 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 67094651 # number of overall hits -system.cpu.dcache.overall_hits::total 67094651 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1141 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1141 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1866 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1866 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3007 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3007 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3007 # number of overall misses -system.cpu.dcache.overall_misses::total 3007 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 64283437 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 64283437 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 116004574 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 116004574 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 180288011 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 180288011 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 180288011 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 180288011 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 46581927 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 46581927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_task_id_percent::1024 0.475830 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 134176300 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 134176300 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 46570369 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 46570369 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513845 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513845 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 67084214 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 67084214 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 67084214 # number of overall hits +system.cpu.dcache.overall_hits::total 67084214 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1050 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1050 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1886 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1886 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2936 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2936 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2936 # number of overall misses +system.cpu.dcache.overall_misses::total 2936 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 66068903 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 66068903 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 130813345 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 130813345 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 196882248 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 196882248 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 196882248 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 196882248 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 46571419 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 46571419 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 67097658 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 67097658 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 67097658 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 67097658 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000091 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000091 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56339.559159 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56339.559159 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62167.510182 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62167.510182 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59956.106086 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59956.106086 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59956.106086 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59956.106086 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 248 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 50 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 67087150 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 67087150 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 67087150 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 67087150 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000092 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000092 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000044 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000044 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000044 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000044 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62922.764762 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62922.764762 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69360.204136 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69360.204136 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67057.986376 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67057.986376 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67057.986376 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67057.986376 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 241 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 39 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.600000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 10 # number of writebacks system.cpu.dcache.writebacks::total 10 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 666 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 666 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 588 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 588 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 667 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 667 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 667 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 667 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1865 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1865 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2340 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2340 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2340 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2340 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33671000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33671000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111589176 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 111589176 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145260176 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 145260176 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 145260176 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 145260176 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 589 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 589 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 589 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 589 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 462 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 462 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1885 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1885 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2347 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2347 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2347 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36319250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36319250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127241905 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 127241905 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163561155 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 163561155 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163561155 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 163561155 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000091 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000091 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000092 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000092 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70886.315789 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70886.315789 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59833.338338 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59833.338338 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62076.998291 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62076.998291 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62076.998291 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62076.998291 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78613.095238 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78613.095238 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67502.336870 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67502.336870 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69689.456753 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 69689.456753 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69689.456753 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 69689.456753 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5851 # number of replacements -system.cpu.icache.tags.tagsinuse 1641.461746 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 26627917 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 7830 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3400.755683 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5861 # number of replacements +system.cpu.icache.tags.tagsinuse 1662.434995 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 26645946 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 7838 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3399.584843 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1641.461746 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801495 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801495 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1979 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 813 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 767 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.966309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 53285074 # Number of tag accesses -system.cpu.icache.tags.data_accesses 53285074 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 26627919 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 26627919 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 26627919 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 26627919 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 26627919 # number of overall hits -system.cpu.icache.overall_hits::total 26627919 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 10540 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 10540 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 10540 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 10540 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 10540 # number of overall misses -system.cpu.icache.overall_misses::total 10540 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 391405749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 391405749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 391405749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 391405749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 391405749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 391405749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 26638459 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 26638459 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 26638459 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 26638459 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 26638459 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 26638459 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000396 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000396 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000396 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000396 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000396 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000396 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37135.270304 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37135.270304 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37135.270304 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37135.270304 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37135.270304 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37135.270304 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1286 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1662.434995 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.811736 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.811736 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1977 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 756 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 135 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 777 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.965332 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 53321296 # Number of tag accesses +system.cpu.icache.tags.data_accesses 53321296 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 26645946 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 26645946 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 26645946 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 26645946 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 26645946 # number of overall hits +system.cpu.icache.overall_hits::total 26645946 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 10610 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 10610 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 10610 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 10610 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 10610 # number of overall misses +system.cpu.icache.overall_misses::total 10610 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 431026999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 431026999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 431026999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 431026999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 431026999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 431026999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 26656556 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 26656556 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 26656556 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 26656556 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 26656556 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40624.599340 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40624.599340 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1664 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 27 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 49.461538 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 61.629630 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292444251 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 292444251 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292444251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 292444251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292444251 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 292444251 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000306 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000306 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000306 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000306 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323320999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 323320999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323320999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 323320999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000307 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000307 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000307 # 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Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.107252 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2641.798011 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4354 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3951 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.101999 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1.637738 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2323.101405 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 312.779722 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000050 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.070895 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.009545 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.080491 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3944 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 920 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2666 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.120361 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 86925 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 86925 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 4317 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 894 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2664 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.120575 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 87043 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 87043 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 4315 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 34 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 4349 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 10 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 10 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 3 # 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number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 324 # number of UpgradeReq misses +system.cpu.l2cache.demand_hits::cpu.inst 4315 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 4354 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 4315 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits +system.cpu.l2cache.overall_hits::total 4354 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3522 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 428 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3950 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 345 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 345 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 1533 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 269302250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 150000500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 419302750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7837 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 462 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 8299 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 10 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 10 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 327 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 327 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 347 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 347 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1538 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1538 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 7830 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2013 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9843 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 7830 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2013 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9843 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.448659 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.907368 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.474895 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990826 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990826 # miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 7837 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2000 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9837 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 7837 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2000 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9837 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.449407 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.926407 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.475961 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.994236 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.994236 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996749 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.996749 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.448659 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.975658 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.556436 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.448659 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.975658 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.556436 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68540.421292 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75965.197216 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69351.800203 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66810.502283 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66810.502283 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68540.421292 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68819.501018 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68640.496622 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68540.421292 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68819.501018 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68640.496622 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.449407 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.980500 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.557385 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.449407 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.980500 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.557385 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76462.876207 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82911.799065 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77161.645570 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74699.445532 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74699.445532 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76462.876207 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76491.840898 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76473.235455 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76462.876207 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76491.840898 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76473.235455 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -877,118 +876,118 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3513 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 431 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3944 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 324 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 324 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3522 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 428 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3950 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 345 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 345 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1533 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1533 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3513 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1964 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5477 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3513 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1964 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5477 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 196758000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27393000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 224151000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3240823 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3240823 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 83086000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 83086000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 196758000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 110479000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 307237000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 196758000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 110479000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 307237000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.907368 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.474895 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990826 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990826 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3522 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1961 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5483 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3522 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1961 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5483 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 225343750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30127250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 255471000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6111844 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6111844 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 95336750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95336750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 225343750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125464000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 350807750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 225343750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125464000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 350807750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.926407 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.475961 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994236 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.994236 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996749 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996749 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.975658 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.556436 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.975658 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.556436 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56008.539710 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63556.844548 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56833.417850 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.540123 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.540123 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54198.303979 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54198.303979 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56008.539710 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56252.036660 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56095.855395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56008.539710 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56252.036660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56095.855395 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.557385 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.557385 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63981.757524 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70390.771028 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64676.202532 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17715.489855 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17715.489855 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62189.660796 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62189.660796 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63981.757524 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63979.602244 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63980.986686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63981.757524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63979.602244 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63980.986686 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 8632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 8631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 8647 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 8646 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 327 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 327 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 347 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 347 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1538 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1538 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15986 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4690 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 20676 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 501056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 630528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 327 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10507 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16021 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4704 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 20725 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 501504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 630144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 348 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10542 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 10507 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 10542 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10507 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5263999 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 10542 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5281499 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 12826749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 12941000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3560824 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3566845 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3943 # Transaction distribution -system.membus.trans_dist::ReadResp 3943 # Transaction distribution -system.membus.trans_dist::UpgradeReq 324 # Transaction distribution -system.membus.trans_dist::UpgradeResp 324 # Transaction distribution +system.membus.trans_dist::ReadReq 3949 # Transaction distribution +system.membus.trans_dist::ReadResp 3949 # Transaction distribution +system.membus.trans_dist::UpgradeReq 345 # Transaction distribution +system.membus.trans_dist::UpgradeResp 345 # Transaction distribution system.membus.trans_dist::ReadExReq 1533 # Transaction distribution system.membus.trans_dist::ReadExResp 1533 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11600 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11600 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11600 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 350464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 350464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11654 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11654 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11654 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 350848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 350848 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5800 # Request fanout histogram +system.membus.snoop_fanout::samples 5827 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5800 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5827 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5800 # Request fanout histogram -system.membus.reqLayer0.occupancy 7074000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5827 # Request fanout histogram +system.membus.reqLayer0.occupancy 7212001 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 51890176 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 29752405 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index d20d50993..0e62e6e73 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.250954 # Number of seconds simulated -sim_ticks 250953957000 # Number of ticks simulated -final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 250953957500 # Number of ticks simulated +final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 881800 # Simulator instruction rate (inst/s) -host_op_rate 1477977 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1675544377 # Simulator tick rate (ticks/s) -host_mem_usage 333860 # Number of bytes of host memory used -host_seconds 149.77 # Real time elapsed on the host +host_inst_rate 722726 # Simulator instruction rate (inst/s) +host_op_rate 1211354 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1373280924 # Simulator tick rate (ticks/s) +host_mem_usage 338728 # Number of bytes of host memory used +host_seconds 182.74 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,35 +29,10 @@ system.physmem.bw_inst_read::total 724276 # In system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 3160 # Transaction distribution -system.membus.trans_dist::ReadResp 3160 # Transaction distribution -system.membus.trans_dist::ReadExReq 1575 # Transaction distribution -system.membus.trans_dist::ReadExResp 1575 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4735 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4735 # Request fanout histogram -system.membus.reqLayer0.occupancy 4753500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 42633500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 501907914 # number of cpu cycles simulated +system.cpu.numCycles 501907915 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071193 # Number of instructions committed @@ -78,7 +53,7 @@ system.cpu.num_mem_refs 77165304 # nu system.cpu.num_load_insts 56649587 # Number of load instructions system.cpu.num_store_insts 20515717 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 501907913.998000 # Number of busy cycles +system.cpu.num_busy_cycles 501907914.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 12326938 # Number of branches fetched @@ -117,13 +92,122 @@ system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction +system.cpu.dcache.tags.replacements 41 # number of replacements +system.cpu.dcache.tags.tagsinuse 1363.457564 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457564 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 471 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits +system.cpu.dcache.overall_hits::total 77195831 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses +system.cpu.dcache.overall_misses::total 1905 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 7 # number of writebacks +system.cpu.dcache.writebacks::total 7 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17202000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17202000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84297000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84297000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 101499000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 101499000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 101499000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 101499000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.504587 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.504587 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53420.152091 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53420.152091 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53280.314961 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53280.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53280.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53280.314961 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2836 # number of replacements -system.cpu.icache.tags.tagsinuse 1455.296642 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1455.296636 # Cycle average of tags in use system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296636 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id @@ -147,12 +231,12 @@ system.cpu.icache.demand_misses::cpu.inst 4694 # n system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses system.cpu.icache.overall_misses::total 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 180319000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 180319000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 180319000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 180319000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 180319000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 180319500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 180319500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 180319500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 180319500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 180319500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses @@ -165,12 +249,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.784832 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 38414.784832 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.784832 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 38414.784832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.784832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 38414.784832 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.891351 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 38414.891351 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 38414.891351 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 38414.891351 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -185,34 +269,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4694 system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170931000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 170931000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170931000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 170931000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170931000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 170931000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 173278500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 173278500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 173278500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 173278500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 173278500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 173278500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.784832 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.784832 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36914.891351 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36914.891351 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36914.891351 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36914.891351 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36914.891351 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36914.891351 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2058.178686 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2058.178675 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978570 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178361 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy @@ -250,17 +334,17 @@ system.cpu.l2cache.demand_misses::total 4735 # nu system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses system.cpu.l2cache.overall_misses::total 4735 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 147697000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16641500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 164338500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 81900000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 81900000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 147697000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 98541500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 246238500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 147697000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 98541500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 246238500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149117500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16801500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 165919000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 82687500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 82687500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 149117500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 99489000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 248606500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 149117500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 99489000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 248606500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5021 # number of ReadReq accesses(hits+misses) @@ -285,17 +369,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.717533 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52005.985915 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52004.687500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.854430 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52005.985915 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52003.907075 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52005.985915 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52003.907075 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52506.161972 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.687500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52506.012658 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52504.012672 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52504.012672 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -315,17 +399,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4735 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 113600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 126400000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 113600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 189400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 113600000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 189400000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115020000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12960000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 127980000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63787500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63787500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115020000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 76747500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 191767500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115020000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 76747500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 191767500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.629357 # mshr miss rate for ReadReq accesses @@ -337,127 +421,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 41 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.457571 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 471 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits -system.cpu.dcache.overall_hits::total 77195831 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1905 # 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number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.152091 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution @@ -489,5 +464,30 @@ system.cpu.toL2Bus.respLayer0.occupancy 7041000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3160 # Transaction distribution +system.membus.trans_dist::ReadResp 3160 # Transaction distribution +system.membus.trans_dist::ReadExReq 1575 # Transaction distribution +system.membus.trans_dist::ReadExResp 1575 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 4735 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 4735 # Request fanout histogram +system.membus.reqLayer0.occupancy 4754000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 23694000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |